JPH0234969A - Input protective circuit - Google Patents

Abstract

PURPOSE:To prevent a thermal breakdown due to a current concentration by connecting a resistor in series to each of a plurality of MIS transistors between the connecting point of an input protective resistor and an internal circuit and a constant potential point, and connecting the series circuits in parallel. CONSTITUTION:Source electrodes 7, 7,... are led from the ends of sources 5, 5,... remote from a gate, diffused resistors 8, 8,... are interposed with source diffused layer at the source, and drain wirings 11 are connected between the terminal of input protective resistors 2 at the opposite input terminal side and the input of an internal circuit 12. Since a plurality of MIS transistors 31-3n are respectively connected in series with the resistors 8 and the series circuits are connected in parallel, thereby preventing a current concentration by the resistors. The transistors can be so formed as to generate an avalanche breakdown. Thus, a thermal breakdown due to a current concentration can be prevented.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Field of industrial application B1 Outline of the invention Prior art "Figure 4" Problems to be solved by the invention Examples of means and actions for solving the problems [Figure 1 to Figure 3] Effects of the invention (A. Field of Industrial Application) The present invention relates to an input protection circuit, and particularly to an input protection circuit provided in an MO3 type semiconductor integrated circuit.

(B. Summary of the Invention) In the input protection circuit described above, the present invention prevents current from concentrating locally in the bypass MIS transistor and causing thermal breakdown when an abnormal voltage such as a surge enters the input terminal. To prevent this, connect the connection point between the input protection resistor and the internal circuit,
M between a constant potential point (e.g. ground or power terminal)
A plurality of series circuits each consisting of an IS type transistor and a resistor are connected in parallel.

(C, Prior Art) [Figure 4] Figure 4 (A) is generally used as an input protection circuit for MO3LSI.
, (B) are used. 3A is a circuit diagram of the input protection circuit, and FIG. 1B is a plan view of the MIS transistor.

In the figure, a is an input terminal, b is an input protection resistor whose one end is connected to the input terminal a, C is an MIS type transistor whose drain is connected to the terminal on the opposite input terminal side of the input protection resistor, and its source is and the gate is grounded. d is an internal circuit that receives an input signal via an input protection resistor.

This input protection circuit suppresses the current by using an input protection resistor when an abnormally high voltage such as a surge that exceeds the gate breakdown voltage of the input MIS type transistor in the internal circuit d is applied to the input terminal a. The internal circuit d is protected by causing an avalanche breakdown to bypass the current.

(D. Problem to be solved by the invention) By the way, in the conventional input protection circuit described above, avalanche breakdown occurs locally in the MIS transistor C, and there is a risk of thermal breakdown due to current concentration. There was a problem. This is because when pressure is applied to the input terminal due to abnormality r7' and MIS type transistor C undergoes avalanche breakdown, if the breakdown occurs in the entire area of MIS type transistor C, the bypass current will flow through the inside of MIS type transistor C. It flows with uniform density and there is no risk of thermal breakdown. However, depending on the shape of the source, train, and gate of the MIS transistor C, the impurity concentration distribution, etc., avalanche breakdown may not necessarily occur in the entire region of the MIS transistor C. Avalanche breakdown may occur only in the area shown, and all of the bypass current may be concentrated there. In such a case, there is a risk that the concentrated portion may be thermally destroyed by the large current.

The present invention was made to solve these problems, and when abnormal voltage such as a surge enters the input terminal, the M
The first objective is to prevent current from concentrating locally in the IS type transistor and causing thermal damage.

(E. Means for Solving the Problems) In order to solve the above problems, the input protection circuit of the present invention connects the connection point between the input protection resistor and the internal circuit and the constant potential point (for example, ground or power supply terminal). It is characterized in that a plurality of series circuits each consisting of an MIS type transistor and a resistor are connected in parallel between them.

(F. Effect) According to the input protection circuit of the present invention, a resistor is connected in series to each of a plurality of MIS type transistors, and the series circuit of the MIS type transistor and the resistor is connected in parallel. concentration can be prevented, and avalanche breakdown can occur in each MIS type transistor. Therefore, thermal damage due to current concentration can be prevented.

LG, Embodiment) [FIGS. 1 to 3] The input protection circuit of the present invention will be described in detail below according to the illustrated embodiment.

FIGS. 1(A) and 1(B) show two embodiments of the input protection circuit of the present invention; FIG. 1(A) is a circuit diagram, and FIG. 1(B) is an M
FIG. 2 is a plan view of an IS type transistor. In the drawing, 1
is an input terminal, and 2 is an input protection resistor, one end of which is connected to the input terminal l. 3. ．． 32-3n (n is, for example, several, tens, or hundreds) is an MIS type transistor, and its drain 4.4, . . . is connected to the terminal on the opposite input terminal side of the input protection resistor 2. , source 5.5,・
...and the common gate 6 is grounded.

Sources 5.5, . . . have longer lengths in the channel direction [lengths in the downward direction in FIG. 1(B)] than drains 4.4, . ,・
. . is taken out from the end of the source 5.5, . There is. Note that 9 is a source wiring, which is grounded.

10. 10, . . . are drain electrodes, 11 is a drain wiring, and these are connected between D8f on the opposite input terminal side of the input protection resistor 2 and the input of the internal circuit 12.

This input protection circuit operates normally for each MrS type transistor 3. ．． 3. -3n is in the off state. and,
If a constantly high voltage is applied between the input terminal and the ground line, the abnormal voltage is applied to all MIS transistors 3I to 3o via the resistors 8.8, . Then, all MIS type transistors 31 to 3n undergo avalanche breakdown due to the voltage, and current is shunted to each MIS type transistor 3, to 3n. At that time, resistance 8.8...
・Prevents current concentration in one place. This point will be explained with reference to FIG. 2, which shows breakdown characteristics.

If there is an abnormal voltage, one MIS type transistor will have a relationship between voltage and current as shown by the solid line. In other words, when an abnormal voltage occurs, the terminal voltage increases and breakdown occurs.
When the pressure is reached, the play goes down, but the current at that time is approximately O.

Immediately, the terminal voltage suddenly drops to a certain extent, and then the current continues to increase while the terminal voltage hardly changes, and when the current value exceeds the breakdown value (for example, 10 mA), it is destroyed. However, in the present invention, since the resistor 8 is connected in series to each MIS transistor 3, the terminal voltage of the resistor 8 rises by one step due to the increase in current after the voltage suddenly drops due to avalanche breakdown. (see dashed line). Then, the increase in the terminal voltage causes the terminal voltage of another MIS type transistor 3 to increase. This is because the series circuits of transistors and resistors are connected in parallel with each other. If the terminal voltage of another MIS type transistor 3 exceeds the breakdown value before the MIS type transistor that has undergone avalanche breakdown is thermally destroyed, that other MIS type transistor also breaks down, and this other M[S type Current also flows through transistor 3. In this way, the MIS type transistors 3, 3, . . . undergo avalanche breakdown one after another in a chain reaction, and a current flows.

Stiffness and other movements occur in an extremely short period of time, almost instantaneously. Therefore, each MIS type transistor 3.3,...
・all undergo avalanche breakdown at almost the same time, and current due to abnormal voltage flows through MIS type transistors 3.3, ・・
・Will be diverted to Therefore, the internal circuit 12 can be protected without causing thermal damage.

FIG. 3 is a plan view showing another embodiment of the input protection circuit. In this input protection circuit, the sources and trains of a plurality of Mis-type transistors are each constituted by one diffusion layer, and an insulating film (LOGOS) 1 that crosses the gate 6 when viewed from above.
3.13, . . . are provided, and the insulating films 13.13, .
Each diffusion layer is substantially separated by *, so that a plurality of MIS type transistors are substantially formed.

In each of the above embodiments, the resistor 8 connected to each MIS type transistor 3 is connected to the source side, but it is not necessarily necessary to connect it in this way, and vice versa, it may be connected to the train side. . Further, a resistor may be connected to both the drain side and the source side.

In short, each MIS type transistor 3 has a resistor 8.
should be connected in series.

Incidentally, since the MIS transistor 3 in the above embodiment was an n-channel MIS transistor, the gate of each MIS transistor was grounded, but if it were a p-channel MIS transistor, the gate of each MIS transistor would be grounded. The gate will be connected to the power supply line (Vdd).

Furthermore, although the above embodiment protects the internal circuit from an abnormal voltage applied between the input terminal 1 and the ground side, the abnormal voltage applied between the power supply line (Vdd) and the input terminal 1 ? It goes without saying that the present invention can also be applied to an input protection circuit that protects internal circuits from high pressure.

(H, Effect of the Invention) As described in F below, the input protection circuit of the present invention includes an input protection resistor provided between the input terminal and the internal circuit, and a wiring connecting the input protection resistor and the internal circuit. A plurality of circuits in which MIS type transistors and resistors are connected in series are connected in parallel between and a constant potential point, and a predetermined potential is applied to the gate of the MTS type transistor. This is a characteristic feature.

Therefore, according to the input protection circuit of the present invention, a resistor is connected in series to each of a plurality of MIS type transistors, and the MIS type transistors are connected in series.
Since the series circuit of the S-type transistor and the resistor is connected in parallel, each resistor can prevent current concentration, and avalanche breakdown can occur in each MIS-type transistor. Therefore,
'It is possible to prevent thermal damage caused by τCC flow.

This figure shows one embodiment. Figure (A) is a circuit diagram, Figure (B) is a plan view of a group of MIS type transistors, Figure 2 is a breakdown characteristic diagram, and Figure 3 is a diagram of another Q embodiment. MIS to show
Figure 4 is a plan view of the type transistor group (A) and (I3).
1 shows a conventional example of an input protection circuit, where (A) is a circuit diagram and (B) is a plan view of a group of MIS type transistors.

Explanation of symbols■...Input terminal, 2...Input protection resistor, 3, ~3n
...Mis type transistor, 8...resistance.

[Brief explanation of the drawing]

Claims (1)

[Claims] (1) An input protection resistor is provided between the input terminal and the internal circuit, and an MIS transistor and the resistor are provided between the wiring connecting the input protection resistor and the internal circuit and one constant potential point. Multiple circuits connected in series are connected in parallel,
An input protection circuit characterized in that a predetermined potential is applied to the gate of the MIS type transistor.