JPH02340A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the degree of integration by forming a bipolar element on the upper surface of one of two buried layers of different conductivity type which are formed so as to be adjacent, and making the residual part a thermal oxide isolation region. CONSTITUTION:After a thin SiO2 film 12 and an oxidation-resistant Si3N4 film 13 formed on a P-type Si substrate surface are selectively eliminated, an N<+> type buried layer 14 is formed by introducing impurity, and further a thick SiO2 film 15 is formed by thermal oxidation. After the film 13 is eliminated, a P-type channel stopper 16 is formed by ion-implanting impurity. After the films 12, 15 are eliminated, an N<-> type epitaxial layer 14 and a thin SiO2 film 18 are formed, and further an Si3N4 film 19 is selectively formed. By heat treatment using the film 19 as a mask, a field oxide film 20 is formed to a depth not reaching the N<+> type buried layer 14. By selectively implanting ion, a collector connection region 21, a base region 22 and an emitter region 23 are formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device (hereinafter abbreviated as rc).
In particular, the present invention is directed to ICs including bipolar elements.

In bipolar ICs, it is essential to provide electrical isolation between elements, and one specific method for achieving this is to cover the semiconductor region with an oxide film called a field oxide film (because it allows for higher integration). The isoplanar method, in which the material is surrounded by a SiO2 film), is currently widely used.

In this isoplanar type IC, it is necessary to provide a channel stopper to prevent current from being conducted to other semiconductor regions by the semiconductor layer under the field oxide film. In forming this channel stopper, the channel stopper and the field oxide film are formed using the same mask according to a method known, for example, in Japanese Patent Publication No. 51-438. When forming this channel stopper, it is necessary to align the substrate and the buried layer of a different conductivity type, which have been previously formed on the surface of the substrate. For example, on a P-type Si substrate J as shown in FIG.
A type epitaxial layer is formed, and a field oxide film 3 formed by selective oxidation is used to form a P type base 4 and an N0 type collector (
When forming an NPN transistor separated from the contact portion (5), it is necessary to match the mask to N÷buried layer 2 in order to form the channel stopper 6, which has the disadvantage of impeding an increase in the degree of integration. Furthermore, if there is a mask misalignment under the field oxide film 3, an imbalance in isolation breakdown voltage will occur between the base side and the collector side of the transistor.To ensure the breakdown voltage value between adjacent buried layers, the channel stopper region 6 is required. It has drawbacks such as difficulty in improving the degree of integration because it cannot be made small.

Note that another conventional technique for forming a channel stopper under a field oxide film is disclosed in Japanese Patent Laid-Open No. 162978/1983. In this example, after sequentially forming a polycrystalline silicon film and a silicon nitride film (Si, N4) on a P-type semiconductor substrate, Si and N4 are selectively formed.

The film is removed, and using this as a mask, N-type impurities are implanted to form a buried layer. Subsequently, using the same mask, the polycrystalline silicon film is selectively oxidized to form an oxide film. After removing the nitride film that served as a mask, the polycrystalline silicon film is implanted. P-type impurities are implanted into the substrate surface to form a channel stopper, taking advantage of the difference in material between the film and the oxide film. However, according to this method, (1) N
Since polycrystalline silicon is used as a mask when forming the 10-type buried layer and oxide film, the N-type impurity diffuses greatly in the lateral direction. It is difficult to specify, and the withstand voltage between the collectors of adjacent elements is poor. (2) Heat treatment and oxidation of polycrystalline silicon can cause stacking faults and cluster dislocation on the silicon substrate surface, and the crystal size of polycrystalline silicon grows and increases, resulting in noticeable irregularities on the silicon substrate surface. I can't avoid it.

[Problems to be Solved by the Invention] An object of the present invention is to improve the degree of integration and breakdown voltage of a bipolar IC.

[Means to solve the problem] The present invention consists of the following steps.

(1) Step of preparing a semiconductor substrate having one main surface, (2
) selectively introducing a predetermined impurity into a part of the main surface of the semiconductor substrate to form a semiconductor region of a first conductivity type; (3) inside another part adjacent to the part of the main surface of the semiconductor substrate; selectively introducing a predetermined impurity into the semiconductor region to form a second conductivity type semiconductor region exhibiting a conductivity type opposite to the first conductivity type and having an impurity concentration lower than the impurity concentration of the first conductivity type semiconductor region. (4) forming a first conductivity type semiconductor layer on one main surface of the semiconductor substrate on which the first conductivity type semiconductor region and the second conductivity type semiconductor region are formed; selectively forming an oxidation-resistant film on the first conductivity type semiconductor layer through a thin oxide film so that at least a part of the oxidation-resistant film is removed on the second conductivity type semiconductor region; (6) ) The surface of the semiconductor device of the second conductivity type, on which the oxidation-resistant film is not formed, is heated without substantially etching the surface of the semiconductor device, using the oxidation-resistant film as a mask. (7) removing the oxidation-resistant film and forming a part of the thermal oxide film in the removed portion of the semiconductor layer; A step of introducing predetermined impurities to form a defined bipolar device region.

Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the drawings.

[Example] Figures 3A to 3 are cross-sectional views of each step showing the manufacturing process of a bipolar IC according to the present invention, and correspond to the following steps (A) to (I).

(A) A high resistance P-type Si substrate 11 is prepared, and a 900 thin SiO film 12 is formed on its surface by thermal oxidation. After forming an oxidation-resistant film of Si, N4[13] to a thickness of 1,500 nm using a CVD (chemical vapor deposition) method, plasma etching was performed using a photoresist as a mask, and a buried layer of N0 was formed. SiO of the part to be formed
, film 12, Si, and N4 film 13 are selectively removed.

CB) The surface impurity concentration is reduced to 10 by diffusing antimony (or arsenic) using the Si, N, and film 13 as a mask.
1g~202O20ato/a+? In addition, the surface of the substrate 11 is thermally oxidized. As a result, an N medium-sized buried layer 14 is formed to a depth of approximately 1.5 μm, and a thick SiO2 film 15 with a thickness of 4000 mm is formed on the surface of the substrate on the N0-shaped buried layer 14. That is, between the N medium-sized buried layer 14 and the Si○2 film 15,
defined by the mask.

(C) After removing the Si, N4 film 13, a P-type channel stopper 16 is formed using the difference in film thickness between the SiO2 film 15 and the film 12. That is, boron (or conductive boron) is ion-implanted into the entire surface of the substrate. At this time, since there is a difference in film thickness of 3100 between the SiO□ film 15 and the SiO2 film 12, the boron ions
In some areas, the n2 film 12 does not reach the substrate, while the Si
In certain areas, the O2 film 12 is implanted into the substrate through the film. Thereafter, a heat treatment is performed to form a P-type channel stopper 16 such that the surface impurity concentration becomes 10'' atoms/a+?.

In this way, the P-type channel stopper 16 is formed as a 5-layer SiO2 film. As mentioned earlier, S
Since the iO, film 15 and the N÷-type buried layer 14 are defined by the same mask, the position of the P-type channel stopper 16 is defined by the N-type buried layer 14, and therefore, , their mutual positions are defined in a self-aligned manner without alignment. 6 (D) All 25 inches of 239115 on the SiO□ film 12 are removed by etching using an HF-based etching solution. At this time, a step is generated on the surface of the substrate as shown in the figure. This is because the amount of silicon on the substrate used to form the oxide film differs.

(E) Form an N-type doped epitaxial silicon layer to a thickness of 1.5 μm to 2.0 μm over the entire surface of the substrate.

At this time, the above-mentioned step remains as it is in the epitaxial layer 17.
appears on the surface of

(F) The surface of epitaxial silicon 1517 is oxidized to 90% by heat treatment in a hydrogen atmosphere.
A thin SiO□ film 18 of 0 is formed. Sarani CV D
After forming the Si, N4 film 19 to a thickness of 1,500 nm by photo-etching, the Si, N4 film 19 is removed in the area where an isolation layer of SiO for insulating and isolating each semiconductor region is to be formed. Remove by etching.

(G) By performing heat treatment in an oxidizing (wet) atmosphere, the portion of the epitaxial layer M17 where the Si, N4 film 19 is not formed is selectively oxidized.

A field SiO2 film 20 is formed to a thickness of 10,000 layers. This is for insulating and separating each semiconductor region from each other. At this time, the channel stopper 16 is stretched and reaches the field SiO2 film 20, completing isolation.

(It) After removing Si and N4 [19], a new Si and N4 film 24 is formed to a thickness of 1400 nm over the entire surface by CVD. Then, the Si and N4 films in the portion where the collector connection region 21 is to be formed are selectively removed by etching, phosphorus is ion-implanted using the exposed field SiO2 film as a mask, and heat treatment is subsequently performed to form an N0 type collector. A connection region 21 is formed.

(1) After removing all Si and N411A24, a photoresist mask (not shown) is formed to cover the DL/ctor connection area 21, and boron ions are implanted into the entire surface to form a base, followed by heat treatment. A medium-sized P base region 22 is formed to a depth of approximately 0.6 μm. Then, after removing the photoresist mask, the PSG
A (phosphorus silicate glass) film 25 is formed to a thickness of about 3,500 mm by CVD, a part of the PSG film on the base surface is removed by photoetching, arsenic is ion-implanted, and then heat treatment is performed to deepen the film. 0.35μ
m N1 emitter regions 23 are formed.

(J) Finally, contact holes are opened in each region, aluminum is deposited by vacuum evaporation method, and then this is patterned into a desired shape to form aluminum electrodes E, B, and C that make ohmic contact with each region. By forming the selective oxide film 20 as shown in FIG.
An NPN type bipolar transistor is completed within the area partitioned by.

[Effects of the Invention] According to the present invention as described above, the following effects can be obtained.

(1) An IC including highly integrated bipolar elements can be obtained.

The reason is that the semiconductor substrate (high resistance P-type Si substrate 11)
A semiconductor region of a second conductivity type opposite to the first conductivity type (P green type buried layer 14 in the example) is in contact with the semiconductor region of the first conductivity type (the N type buried layer 14 in the example). This is because the embedded layer 16) is selectively provided. This is because the method described above eliminates the need for separate masks for forming a semiconductor region of the first conductivity type and a mask for forming a semiconductor region of the second conductivity type, so there is no need to consider mask alignment. . That is, there is no need for a mask alignment margin, and both buried layers overlap each other in a self-aligned manner, so that as a result, the degree of integration can be greatly improved. This point will be described in more detail below.

According to the method described above, the position of the P-type buried layer serving as a channel stopper is defined by the thick oxide film 15. On the other hand, the positions of the thick oxide film 15 and the N+ type buried layer 14 are defined by a common mask (SiO2 film and Si3N4 film).

Since polycrystalline Si is not used for the mask, there is no lateral spread of N0 type impurities due to N0 type buried diffusion.

P÷ type diffusion (channel stopper formation) into the substrate 11 can be performed with good control by utilizing the difference in film thickness between the thick oxide film 14 and the thin oxide film 12.

Therefore, the positions of the P-type buried layer are defined by the N0-type buried layer, and their positions match without alignment. The pre-formed N÷
There is no need for alignment when forming the P raw mold buried layer with respect to the mold buried layer, and therefore there is no need to provide mask alignment margin.

As a result, mask alignment margin is no longer necessary.

As is clear from the patterns shown in contrast in FIGS. 2 and 6, the elements can be made smaller and the degree of integration of the IC can be improved.

FIG. 2 shows the pattern of one transistor in the case of the present invention, and FIG. 6 shows the pattern of one transistor in the case of the prior art in a plan view. First, in Fig. 6, 8gl1QA is the mask alignment margin (=maximum alignment error'': 1 μm), and the distance QB is between the P-type base area (B) and the P-medium embedding calendar (
The distance aQc is the distance between the collectors of adjacent transistors to obtain the necessary withstand voltage. On the other hand, according to the present invention, as shown in FIG. 2, the base (B).

Although the collector (C) has the same dimensions as the conventional one, since both buried layers overlap each other in a self-aligned manner, only the mask alignment margin QA can be omitted.

(2) The process can be simplified.

As mentioned above, since the need for alignment is eliminated, the mask forming step for forming the second conductivity type semiconductor region (P type buried layer 16 in the example) can be omitted, simplifying the process. can.

(3) It is possible to achieve high integration and to improve breakdown voltage.

Due to the reason (1) above, there is no variation in the distance between the second conductivity type semiconductor region (P-type buried layer 16) and the bipolar-type element formation region (P-type base region), which improves breakdown voltage and reliability. You can improve your sexuality.

That is, the second conductivity type semiconductor layer (epitaxial layer 1
7) The semiconductor region of the second conductivity type (the P+ type buried layer 16) is better than the case where the second conductivity type semiconductor region (the P÷ type buried layer M16, which is a P+ type channel stopper) is formed after formation.
That is, the distance between the channel stopper and the bipolar element forming region (P-type base region) can be increased, and the breakdown voltage can be increased. The reasons for this will be explained in more detail below.

As is clear from the above step (D), after the removal of the SiO film 15.16 (FIG. 3D), the surface of the N0-type buried layer 14 and the P÷ type buried layer (P00-type channel stopper) are removed. ) 16 surface, and this difference also appears on the surface of the epitaxial layer 17. The existence of this difference causes the field Si○ on the edge of the N0-type buried layer 14 to be
Parts (20a, 20b) of the two films 2o are formed to be depressed. The field Si formed by this depression
○The two membrane portions 20a are attached to the base area 2 shown in the third construction drawing.
It expands the isolation margin with 2. That is, field S i O, film portions 20a, 20b
This suppresses the lateral expansion and diffusion of the P-type buried layer 16. Furthermore, as is clear from the manufacturing process of the present invention described above, since the N medium-sized embedded image 14 has a higher impurity concentration than the P÷-type embedded image 16, the P÷-type embedded image 16 expands in the lateral direction. It suppresses the spread.

Therefore, it is possible to improve the breakdown voltage while increasing the degree of integration.

(4) Substrate junction capacitance can be reduced.

That is, in accordance with (1) above, the PN junction area between the semiconductor substrate and the collector region can be reduced.
Junction capacitance (substrate junction capacitance ff1) can be reduced.

Further, as described above, the N0-type buried layer 14 is replaced by the P00-type buried layer [1
In other words, the P 10 type buried layer 16 has a lower impurity concentration than the N÷ type buried layer 14 . As evidenced by the fact that the channel stopper 16 is stretched in the above-mentioned step (G), the impurity concentration of the N- type semiconductor layer is lower than that of the P-type buried layer. An increase in the PN junction capacitance between the two can be avoided.

(5) No crystal defects occur in the semiconductor layer.

Introducing impurities to form a P-type buried layer is a thin Si
O, through the membrane and then S i O.

Since the film is removed and epitaxial growth is performed directly on the P÷ type buried layer, crystal defects in the semiconductor layer do not occur, and irregularities on the surface of the semiconductor layer due to growth of crystal size are reduced.

(6) According to the above-described embodiments of the present invention, in addition to the above-mentioned embodiments, there is a significant effect in improving the degree of integration.

That is, instead of the isobrener method, LOGO3 (Si
Since the elements are isolated using a SiO□ film formed by selective low-temperature oxidation, there is no under-etching of the silicon under the Si or N4 mask, and therefore there is no need to leave room for the mask, which increases the degree of integration. You can improve.

Isolation S as shown in Figures 3F to 3G
When forming the iO, film, the Si, N4 mask is formed in the recessed part of the epitaxial layer, so the formation of bird's heads (protrusions on the SiO, film) due to selective oxidation is alleviated, and the wiring formed on it is There will be no break in the steps. As described above, according to this embodiment, in addition to the above-mentioned effect of improving the degree of integration by omitting the mask alignment margin, a synergistic effect is produced, which is extremely effective in improving the degree of integration of bipolar ICs.

[Modification] Next, as a second embodiment of the present invention, If! between elements! a
An example using PN junction isolation as the isolation method will be described.

In this case, the process up to forming the epitaxial semiconductor layer 17 on the semiconductor substrate 11 described in the previous embodiment (FIGS. 3A to 3E) is the same process, and then the surface of the semiconductor layer 17 is - Window etching is performed on the SiO2 film by photoresist treatment, and boron or the like is selectively diffused or ion-implanted to obtain a P+ type insulating isolation region 26 extending from the semiconductor layer surface to the P medium-sized buried Jii16.

FIG. 4 shows an N-type epitaxial layer 17 surrounded by a P+-type isolation region 26 obtained by such a process.
P-shaped base region 22 on the surface. N+ side epitaxial region 23. A structure in which an N-type collector extraction portion 21 is formed is shown. According to this embodiment, the following effects can be obtained in addition to the effects obtained by the previously described embodiments. especially,
In ICs that require high speed performance, the epitaxial layer 17 is formed to be thin, for example, 1.5 to 2.0 μm, so the area of the insulating isolation region hardly changes even with the combination of isolation methods using PN junctions, making it possible to create highly integrated ICs. is obtained. Moreover, unlike the isolation method using an oxide film (isoplanar method), the surface becomes flat, which is effective in preventing disconnection of wiring layers.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of essential parts of a bipolar IC according to the present invention. FIG. 2 is a plan view of essential parts of the bipolar IC of the present invention. FIGS. 3A to 3D are cross-sectional views of each step to show the manufacturing process of an IC according to the present invention. FIG. 4 is a sectional view showing another form of the bipolar IC according to the present invention. FIG. 5 is a sectional view of essential parts showing an example of a bipolar IC manufactured by a conventional technique. FIG. 6 is a plan view of essential parts showing an example of a bipolar IC manufactured by the conventional technique. DESCRIPTION OF SYMBOLS 11... P- type silicon substrate, 12... Thin oxide film, 13... Silicon nitride film, 14... N0 type buried layer, 15... Thick oxide film, 16... P ÷ type channel stopper, 17...N- type epitaxial layer, 2o.
...Field oxide film for insulation isolation, 21...N+ type collector connection region, 22...P type base region, 23.
...N-type emitter region, 25...PSG film, 26...
- P-type separation area. Fig. 1 Fig. 38 Fig. 38 Fig. 2/θ Fig. 3C

Claims (1)

[Claims] 1. (1) A step of preparing a semiconductor substrate having one main surface; (2) selectively introducing a predetermined impurity into a part of the one main surface of the semiconductor substrate to form a first conductivity type. (3) selectively introducing a predetermined impurity into a part of the main surface of the semiconductor substrate adjacent to the other part to exhibit a conductivity type opposite to the first conductivity type, and forming a second conductivity type semiconductor region having an impurity concentration lower than the impurity concentration of the first conductivity type semiconductor region; (4) the first conductivity type semiconductor region and the second conductivity type semiconductor region are formed; (5) forming a semiconductor layer of a first conductivity type on one principal surface of the semiconductor substrate, at least a portion of which is on the semiconductor region of the second conductivity type; (6) substantially etching the surface of the second conductivity type semiconductor layer on which the oxidation-resistant film is not formed; (7) selectively forming a thick thermal oxide film having a depth that does not reach the semiconductor region of the first conductivity type by thermally oxidizing the surface of the semiconductor layer using the oxidation-resistant film as a mask; ) removing the oxidation-resistant film and introducing a predetermined impurity into the removed portion of the semiconductor layer in order to form a bipolar element region defined by a portion of the thermal oxide film; A method for manufacturing semiconductor integrated circuit devices. 2. In the step (4), after providing a stepped portion on one main surface of the semiconductor substrate in which the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type are formed, the semiconductor layer of the first conductivity type is formed. 2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the method comprises forming a semiconductor integrated circuit device.