JPH0234015A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of the circuit due to the conduction of a parasitic transistor(TR) by employing a resistor made of an n-channel impurity layer for a load resistor and generating the operating current from a current source circuit using a current mirror circuit. CONSTITUTION:A current mirror circuit is used for part of the current source circuit CS. That is, the current mirror circuit consists of a TR Q5 and a diode D3 to generate the operating current, which is fed to a current switch comprising TRs Q1-Q4 and resistors R1, R2. Thus, it is possible to eliminate the resistor connected directly to a power voltage VEE and to prevent the conduction of a parasitic TR. That is, even if the power voltage is fluctuated, the margin of the conduction of the parasitic TR is increased by a forward voltage VBE (nearly 0.8V) of the diode D3. For example, even when the power voltage is varied by 20%, the reverse bias voltage is 0.16V by taking the said voltage of 0.8V into account and the parasitic TR is not conducted.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to semiconductor integrated circuits and information processing devices, and particularly to circuits and information processing devices using resistors with small parasitic capacitance suitable as resistors for high-speed circuits.

[Conventional technology]

In conventional semiconductor integrated circuits, especially when speeding up the gate circuit as shown in Fig. 2, the transistors used are
In addition to improving the performance of Q5, the resistors R1 to R4 to be used
It is necessary to reduce the parasitic capacitance of This is because the speed of the gate circuit strongly depends on the time constant of the collector section of the transistor forming the current switch. For this purpose, resistors formed with n-type impurity layers (hereinafter referred to as n-layer resistors) are used for resistors R, R2, and the stray capacitance of the collector portion (the total value of the parasitic capacitance of the transistor and the resistor, the parasitic capacitance of the wiring, etc.) is ) is effective to reduce the time constant and speed up the process. First, the operation of this circuit will be explained. In this circuit, the input signal VIN is the reference voltage V! 3B, and depending on the level of the input signal, the output signal is an affirmative signal VOR and a negative signal V
NOR is obtained. In the current source circuit C8, the base of the current source transistor Q is connected to the resistor R1 and the diode Di.
, D2, and the operating current is determined by the current limiting resistor R4. The signal amplitude determined by this operating current and resistors R1 and R2 becomes the signal amplitude of the output signal. On the other hand, in order to stabilize the circuit operation, it is preferable that the resistor R3 is also formed of the same n-type resistor as R1 and R2. Next, an example of the configuration of an n-type resistor is shown in FIG. In this example,
n-type epitaxial layer n formed on substrate p-3ub
The ai1 layer is separated by an insulator l501, and an n-type impurity formed by diffusion or ion implantation is used as the resistance layer. Further, an n-layer is provided under the electrodes to reduce contact resistance with the electrodes N and N2. Furthermore, I so,
#@ is the ms film for the edge. An example in which a plurality of the above gate circuits are provided and driven with two types of power supply voltages will be explained with reference to FIG. First current source circuit C
81 is driven by the first power supply voltage VEE, and the second current source circuit C82 is driven by the second power supply voltage VEE2. The reason why two types of power supply voltages are used in this way is to drive at the lowest possible power supply voltage and reduce the overall power consumption. A semiconductor integrated circuit including this gate circuit can be converted into an electric gPS.
When driving with 1st. If the power source E1 and the second power source E2 operate independently, the changes in El and the changes in R2 may change inversely to each other. That is, a case may occur in which the lowest power supply voltage VEEl changes to become higher and the other power supply voltage VEE2 changes to become lower. A similar situation also occurs when testing the operating margin of a circuit. For example, VEE changes from -5.2V to L-4.16V by 20%, and vEE becomes -4.
It changes by +20% from Ov to -4.80V. At this point, the substrate is biased by VEE, so as shown in Figure 5, the parasitic transistor Qp, which has the substrate as its base and the first layer as its emitter, becomes conductive. Put it away. This parasitic transistor causes the electrode N1 to be the collector and the electrode N1 to be the collector.
A current bus is generated with 2 as the emitter, and the effective resistance value between the two electrodes becomes small. As a result, for example, an abnormality occurs in the operating current of the gate circuit, impairing normal circuit operation.

[Problem to be solved by the invention]

The above conventional technology uses a resistor formed with an n-type impurity layer, and takes into consideration the abnormal operation of the circuit due to conduction of a parasitic transistor based on the substrate in a semiconductor circuit driven by multiple power supply voltages. This made it difficult to realize a circuit with stable operation. The purpose of the present invention is to prevent abnormal circuit operation caused by parasitic transistors when using a resistor formed with an n-type impurity layer, and to provide a high-speed semiconductor integrated circuit that takes advantage of the resistor's small parasitic capacitance. be.

[Means to solve the problem]

The above object is achieved by using a current mirror circuit as part of an operating current generating circuit when a resistor formed of an n-type impurity layer is used as a load resistor.

[Operation 1] By using a current mirror circuit, the voltage applied to the electrode of the resistor formed of the n-type impurity layer is always higher than the power supply voltage that biases the substrate. As a result, the substrate and the n-type impurity layer can be reverse biased, thereby preventing malfunction of the circuit due to conduction of a parasitic transistor whose base is the substrate and whose emitter is the electrode of the resistor. (Embodiment) An embodiment of the present invention will be described below with reference to FIG. 1. In this embodiment, a current mirror circuit is used as a part of the current source circuit C8. That is, a transistor Q and a diode D , constitutes a current mirror circuit to generate an operating current, and supplies it to a current switch composed of transistors ~Q and resistors R1 and R2. This makes it possible to eliminate the resistance of the parasitic transistor, thereby preventing conduction of the parasitic transistor.In other words, even when the power supply voltage changes as described above, the parasitic transistor is reduced by the forward voltage VBE (approximately 0.8V) of the diode D. In this example, even when the power supply voltage is changed by +20%, this 0.8V
Considering this, the reverse bias voltage is 0.16V, and the parasitic transistor does not become conductive. In this embodiment, the current flowing through the diode D3 is generated only by the resistor R9. This resistor is preferably constructed of an n-type resistor in order to compensate for manufacturing variations in the load resistors R□ and R2. Of course, it is not limited to this. An example in which another method is applied to generate the current flowing through the diode DJ will be explained with reference to FIG. This example uses Transistoro 5. Resistor R,, R7, diode D4. D constitutes a current source. In this circuit, if transistor Q and diode D are configured with transistors having the same structure and the same emitter area, the operating current flowing through Q will be equal to the current flowing through diode D. In other words, the operating current is
The current determined by the current limiting resistor R6 and the diodes D4 and D
, is the total current flowing through . If the current flowing through D4 and D is made small, the current flowing through D will be approximately determined by the resistor R5. Therefore. By configuring resistor R6 with an n-type resistor in this circuit,
It becomes possible to compensate for variations in the manufacturing process of the same resistor. Furthermore, since the value of the resistor Rr can be designed to be approximately the same value as the load resistors R1 and R2 of the gate circuit, it is possible to compensate for manufacturing variations due to layout. Next, considering the current flowing through the diodes D, D,
Another embodiment is shown in FIG. In this circuit, the current flowing through the diodes D4, D, and the transistor Q7.
A current source composed of resistors R, , R9 and diodes D6 and D7 is used to bypass the electric FA voltage VEH. Further, a diode D7 is inserted in series with the diode DJ, and a diode DG is inserted in series with the transistor Q5. As a result, the operating current flowing through the transistor Q can be determined by the n-type resistor R6, and it becomes possible to compensate for the n-type resistor with higher accuracy. Note that the diodes Ds and D are used to prevent saturation of the transistor Q7, and it is also possible to connect the anode of D3 and the emitter of Q to make the diodes common. As described above, according to this embodiment in which an n-type resistor and a current mirror circuit are combined, conduction of the parasitic transistor can be prevented. Another embodiment for obtaining the same effect will be described with reference to FIG. 4. Conventionally, the first power source E1 and the second power source E2 were provided independently. For this reason, when these power supplies are used to drive a semiconductor integrated circuit using an n-type resistor, they have the disadvantage that the above-mentioned height is likely to be reversed. For this reason, in this embodiment, a control circuit pc is provided between both power supplies. This control circuit pc prevents the two power supplies from changing independently, and operates so that, for example, when the power source E1 changes by +20%, the power source E2 also changes by +20%. This makes it possible to use n-type resistors even in semiconductor integrated circuits that use a plurality of power supply voltages, and the small parasitic capacitance of the resistors makes it possible to speed up the circuit. Note that the same effect can be obtained by separately providing a dedicated power source for biasing the substrate. [Effects of the Invention] According to the present invention, a resistor formed of an n-type impurity layer with a small parasitic capacitance can be used as a load resistor for a gate circuit, etc., so a semiconductor integrated circuit can be realized with higher speed by reducing the parasitic capacitance. effective.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a gate circuit according to an embodiment of the present invention, Figure 2 is a circuit diagram of a gate circuit using an n-type resistor in a conventional circuit example, and Figure 3 is a circuit diagram of a gate circuit formed with an n-type impurity layer. A cross-sectional view of a resistor, Figure 4 is a circuit diagram of a conventional current source for a semiconductor integrated circuit using multiple power supplies, and Figure 5 is a resistor formed with an n-type impurity layer to explain the conduction of a parasitic transistor. 6 is a current source circuit diagram of one embodiment of the present invention, and FIG. 7 is a current source circuit diagram of another embodiment of the present invention. Explanation of symbols Q1-Q7...Transistor, R-R7...Resistor, D1-D7...Diode, C8...Current source circuit, PC...Control circuit, E1-E2...Power supply ,QP・
... Parasitic transistor, N1-N2 ... Electrode, r S
o, ~I So2...Insulator] Figure 4 Figure 7 ylr: Figure 7 @

Claims (1)

[Claims] 1. In a semiconductor integrated circuit that uses a voltage generated by passing an operating current through a load resistor as a signal voltage, the load resistor has n
1. A semiconductor integrated circuit characterized in that the operating current is generated by a current source circuit that uses a resistor formed of a shaped impurity layer and a current mirror circuit in a part of the circuit. 2. In the current mirror circuit according to claim 1, a resistor formed of an n-type impurity layer having the same structure as the load resistor according to claim 1 is used as the current limiting resistor that determines the current value. semiconductor integrated circuit. 3. In an information processing device that uses a circuit whose signal voltage is a voltage generated by passing an operating current through a load resistor as an internal circuit, and also uses a semiconductor integrated circuit driven by a plurality of power supply voltages, at least one power supply: An information processing device characterized in that a semiconductor integrated circuit is driven by a power source that is controlled to make the same changes as changes in a power source that biases a substrate.