JPH0233172B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a shift circuit having a check function.

(2) Description of Prior Art Conventionally, in this type of shift circuit, there is no regular relationship between the bit array of input data and the bit array of output data extracted from an arbitrary bit position of the input data, and generally Since the parity check method used as a circuit check method cannot be used, the circuits are either duplicated and checked, or no check means are used at all.

Therefore, shift circuits without checking means lack reliability, and shift circuits with duplicated circuits have the drawback of requiring too much metal for checking.

(3) Description of the purpose of the invention The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology. Therefore, the purpose of the present invention is to provide a new method that can realize a check function with a small amount of metal material. The purpose of the present invention is to provide a shift circuit that provides a shift circuit.

(4) Structure of the Invention In order to achieve the above object, the shift circuit according to the present invention includes a first logical means that takes the exclusive OR of all input parity bits, and a first logical means that calculates the exclusive OR of all input parity bits, and Shift bit number output means for outputting a number q indicated by the upper bits obtained by removing the lower 3 bits from the number r and the shift bit number;
A first shift means for shifting input data by q bytes to take out (m+1) bytes of data, and rotatingly shifting the (m+1) bytes of output data of the first shifting means by r bits to obtain the shift result m.
The second part that separates and outputs the byte and the remaining 1 byte
, a second logical means that takes the exclusive OR of m bytes of this result, and a third logical means that takes the exclusive OR of this remaining 1 byte, corresponding to n bytes of input data. (n-m-1) bits excluding the (m+1) parity bits corresponding to the (m+1) byte data outputted from the first shifting means by shifting q bits using the n-bit parity bits as input. a third shift means for outputting the parity bit of
and a check means for determining the normality of the operation based on the result of the exclusive OR of the outputs of the first, second, third, and fourth logic means.

(5) Description of Embodiments of the Invention Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a shift circuit according to the present invention. In the figure, one embodiment of the present invention has a shift bit number storage register 1.
, shift section 2, A detection section 3, and B detection section 4
, a C detection section 5 , and a judgment section 6 .

The shift bit number storage register 1 is a 6-bit register, which can be shifted by the shift unit 2 from 0 to 63.
Indicates the bit value.

The shift section 2 is a shifter specialized for the left shift section with an input of 16 bytes, 128 bits, and an output of 8 bytes, 64 bits. When the number of shift bits is 0, bits 0 to 63 of the input data are output, and when the number of shift bits is maximum 63, bits 63 to 126 of the input data are output.

The A detection section 3 performs an exclusive OR on the 128-bit data input to the shift section 2 and sends the result to the judgment section 6.

The B detection section 4 takes the exclusive OR of the 64-bit data output from the shift section 2 and sends the result to the judgment section 6.

The C detection section 5 performs an exclusive OR operation on the 128-bit data input to the shift section 2 excluding the output 64 bits, and sends the result to the judgment section 6.

The judgment section 6 assumes that if the operation of the shift section 2 is normal, the 128-bit data input to the shift section 2 will always be detected by either the B detection section 4 or the C detection section 5. , the normality of the operation is determined from the outputs from the A detection section 3, the B detection section 4, and the C detection section 5.

FIG. 2 is a specific circuit configuration diagram of the shift section 2. As shown in FIG.

The shift section 2 is composed of 16 shift circuit elements 7. This shift circuit element 7 has a 16-bit input and a 9-bit output, and can perform a left shift from 0 bits to 7 bits in response to a 3-bit shift bit number instruction. This element is used to shift from 0 to 63 bits in a two-stage configuration. In the first stage, n times 8 (n=
0 to 7) A bit shift, that is, a shift in units of bytes, is performed, and in the second stage, a 0 to 7 bit shift is performed.

To perform a byte-by-byte shift, in the first stage, the input data is divided into bits 0, 8, and 16 so that a 1-bit shift on the element becomes an 8-bit shift of the input data.
... are input to the shift circuit element in this order. By this byte-by-byte shift, 9 bytes from the byte position indicated by the upper 3 bits of shift bit number storage register 1 out of 16 bytes of input data are selected as bytes containing bits that will become output data.
This indicates that the other 7 bytes are part of the input data that is not output. In the second stage, 64 bits from the bit position indicated by the lower 3 bits of shift bit number storage register 1 are selected as output data from among the input 9 bytes and 72 bits. At this time, by concatenating the 72-bit MSB and LSB input to the second stage, it is possible to output 8 bits of input data that do not become output input data to bits 64 to 71 of the second stage output.

Figure 3 shows an A detection section 3, a B detection section 4, and a C detection section 5.
This is a specific circuit of the determination unit 6.

The A detection unit 3 includes 16 inverters 9 that invert odd parity bits of input data, and 16 inverters 9 that invert odd parity bits of input data.
It is composed of three 8-input exclusive OR circuit elements 8 that take the exclusive OR of odd parity bits. The inverted odd parity bits are equivalent to the exclusive OR of 8-bit data, and the output obtained by exclusive ORing the inverted 16-bit odd parity bits is the same as the exclusive OR of the 128-bit input data. This becomes the output.

The B detection section 4 is composed of nine 8-input exclusive OR circuit elements 8 that take the exclusive OR of 64-bit output data. Of these, eight exclusive OR circuit elements 8 can be excluded from the metal quantity of the shift circuit check means by performing an exclusive OR on each byte and using the output as a parity bit.

The C detection section 5 includes a shift circuit element 7 which inputs the 16-bit inverted odd parity bit produced by the detection section 3 and outputs 7 bits, and a shift circuit element 7 which outputs 7 bits and the two stages of the shift circuit shown in FIG. It is composed of three 8-input exclusive OR circuit elements 8 which take the exclusive OR with the 8 bits 64 to 71 of the second output. As shown in FIG. 4, the shift circuit element 7 inputs the odd parity bits inverted in the order of bits 9 to 15, 0, and 1 to 8 of the input data, and inputs the bit number indicated by the upper three bits of the shift bit number storage register 1. and outputs the input bits to 7 bits of output bits 0 to 6. This output becomes the inverted odd parity bits of bytes 9 to 15 when the number of shift bits is 0, and the inverted odd parity bits of bytes 0 to 6 when the shift bit number is the maximum 7. These are the bytes that are not output by the first stage output of the shift circuit shown in FIG. 2, ie, 7 bytes out of 8 bytes of input data that are not output.
Bytes 64 to 71 of the second stage output of the shift circuit are 8 bits that are not output out of the 9 bytes of the first stage output, and exclusive ORing of these bits with the 7 bits of the output of the shift circuit element 7 is as follows. , to take the exclusive OR of 64 bits of data that are not output out of the 128 bits of data input to the shift unit 2.

The judgment unit 6 receives the output of the A detection unit 3 and the B detection unit 4.
It is composed of an 8-input exclusive OR circuit element 8 that takes the exclusive OR of the output of the C detector 5 and the output of the C detection section 5.

As a criterion for determining whether or not the operation of the shift section 2 is normal, it is assumed that if the operation is normal, the input 128-bit data will always be detected by either the B detection section 4 or the C detection section 5. Since this assumption is made, the output of the judgment unit 6 which takes the exclusive OR of these three inputs will be logic "0" if the operation is normal.

(6) Description of Effects of the Invention As explained above, the present invention includes the following: the result of the exclusive OR of the input data of the shift circuit, the result of the exclusive OR of the output data of the shift circuit, and the input data to the shift circuit. By checking the shift circuit based on the result of the exclusive OR of the portion of the input data that does not become the output data, there is an effect that the shift circuit can be checked with a small amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the shift section shown in FIG. 1,
Figure 3 shows the A detection section, B detection section and C
FIG. 4 is a circuit diagram of the detection section and judgment section, and is a bit arrangement diagram of input data and output data of the shift circuit element shown in FIG. 3. 1...Shift bit number storage register, 2...Shift section, 3...A detection section, 4...B detection section, 5...
. . . C detection section, 6 . . . judgment section, 7 . . . shift circuit element, 8 . . . exclusive OR circuit element, 9 .

Claims (1)

[Claims] 1 Input data consisting of n (n≧3) bytes and n parity bits added to each byte, and extract m (m≦n-2) bytes of data starting from an arbitrary bit position. The target shift circuit includes a first logical means that takes the exclusive OR of all input parity bits, a number r indicated by the lower three bits of the number of shift bits, and a number r that removes these lower three bits from the number of shift bits. A shift bit number output means for outputting a number q indicated by the upper bits, a first shift means for shifting input data by q bytes to extract (m+1) bytes of data, and a (m+1) number of the first shift means. a second shift means that rotationally shifts byte output data by r bits and separates and outputs the shift result m bytes and the remaining 1 byte; and a second shift means that takes an exclusive OR of the resultant m bytes. a logic means, a third logic means that performs an exclusive OR of the remaining 1 byte, and the first shift means that shifts q bits using n parity bits corresponding to n bytes of input data as input. a third shift means for outputting (n-m-1) parity bits excluding (m+1) parity bits corresponding to (m+1) bytes of data output from the third shift means; and an output of the third shift means. and a check means for determining the normality of the operation from the result of the exclusive OR of the outputs of the first, second, third and fourth logic means. A shift circuit comprising: