JPH05135482A - Parallel storage controller - Google Patents

Abstract

PURPOSE:To prevent increase of number of a memory and to constitute a compacter hardwear. CONSTITUTION:By a data converting circuit 123, 1 byte data 110 is bisected to upper 4 bits and lower 4 bits, and 4 bits data 111 is outputted to a data selected-circuit 124. At this time, by a parity generating circuit 122, a parity is generated at every the input of the 4 bits data 111, and by a 4 bits shift register 121, the parity is stored successively while being shifted till a parity bit is generated to 4 bits. By the data selecting circuit 124, the 4 bits data 111 by 4 column is written on a magnetic disk 104 from the magnetic disk 101, and in 5th column thereafter, a parity column 112 is selected and written on the magnetic disk 104 from the magnetic disk 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel storage control device, and more particularly to a parallel storage control device for storing a data string in separate storage devices for each bit forming the data string.

[0002]

2. Description of the Related Art Conventionally, as a parallel storage control device of this type, there has been known a structure shown in FIG. 2 in which a magnetic disk is used as a storage device. In the configuration shown in FIG.
When the data string is stored in different storage devices for each bit forming the data string, the data conversion circuit 221
Converts a 4-bit data string into a parallel bit string and stores each bit in the magnetic disks 201-204.
The parity calculation circuit 220 calculates the parity of the data string and stores the calculated parity bit in another magnetic disk 205.

[0003]

In the above-mentioned conventional parallel storage control device, another storage device is required for storing the parity bit, and the number of storage devices increases, which makes implementation difficult. There was a problem that it might become.

The present invention has been made in view of the above problems, and provides a parallel storage control device capable of storing bits constituting a data string in separate storage devices with a more compact hardware configuration. To aim.

[0005]

In order to achieve the above object, the present invention according to claim 1 provides a parallel storage control device for storing a data string in a separate storage device for each bit forming the data string. Parity calculating means for obtaining the parity for the data string, temporary storing means for sequentially storing the parity calculated by the parity calculating means by the number of bits forming the data string, and the data string is formed in the temporary storing means. When the parity is stored by the number of bits to be stored, the parity storage control means for storing the parity stored in the temporary storage means in a separate storage device similar to the storage for each bit is provided.

[0006]

In the invention according to claim 1 configured as described above, when the parity calculating means obtains the parity for one data string, the temporary storage means uses the parity calculated by this parity calculating means as the data. The parity storage control means sequentially stores the parity stored in the temporary storage means when the parity is stored in the temporary storage means by the number of bits forming the data row. It is stored in a separate storage device as well as storage.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a parallel storage controller according to an embodiment of the present invention. In this embodiment, data of 1 byte width is divided into 4 bit width and 4 magnetic disks 1 are used.
01 to 104 are stored.

In the figure, the binary counter 120 counts up each time the data selection circuit 124 writes data to the magnetic disks 101 to 104, and outputs the count result to the data selection circuit 124.

A data conversion circuit 123 and 4-bit shift registers 121 and 125 are connected to the data selection circuit 124, and the data selection circuit 124 selects one of the output bit strings based on the count result of the binary counter 120. Then, the data is written on the magnetic disks 101 to 104.

The data conversion circuit 123 uses 1-byte data 1
10 is converted into two columns of 4-bit data 111 and sequentially output to the data selection circuit 124 and the parity generation circuit 122. The parity generation circuit 122 calculates a parity for a 4-bit data string, and the 4-bit shift register 12
Output to 1,125. Here, the 4-bit shift register 121 shifts and stores sequentially input parity bits, and outputs them to the data selection circuit 124 and the parity generation circuit 122 when 4 bits are input.

On the other hand, the 4-bit shift register 125 is
When the parity generation circuit 122 inputs the output of the 4-bit shift register 121 and calculates the parity bit, the parity bit is sequentially shifted and stored, and when 4 bits are input, it is output to the data selection circuit 124.

Next, the operation of this embodiment having the above structure will be described. The data conversion circuit 123 uses 1-byte data 11
The 0 is divided into upper 4 bits and lower 4 bits, and the 4-bit data 111 is output to the data selection circuit 124. The data selection circuit 124 of the binary counter 120 is 4
Every time the bit selection data 114 is output, the count is incremented. Here, the parity generation circuit 122 generates a parity for each input of the 4-bit data 111. The 4-bit shift register 121 sets the parity to 2
Sequential storage is performed while shifting until the value of the binary counter 120 becomes 3 (until 4 parity bits are generated).

During this period, the data selection circuit 124 selects the 4-bit data 111 and writes the 4-bit data 111 as it is from the magnetic disk 101 to the magnetic disk 104.
Subsequently, the data selection circuit 124 selects the parity column 112 until the binary counter 120 reaches 4, and writes the parity column 112 to the magnetic disk 104. And
The 4-bit shift register 125 stores the parity of the parity column 112 while shifting each time the parity column 112 is generated. This operation is repeated until the value of the binary counter 120 reaches 19 (until 4 bits of parity in the parity column 112 are generated).

The data selection circuit 124 selects the parity column 113 until the binary counter 120 reaches 21. Two
4 when the binary counter 120 is 20 and 21
The contents of the bit shift register 125 are shifted by 1 bit. Therefore, every time four columns of 4-bit data 111 are written, one parity column 112 is written, and every twenty data columns, two parity columns 113 are written.

The reason why the parity is shifted by the shift register and written on the magnetic disk is that even if one of the magnetic disks fails, the parity required to restore the data on the failed magnetic disk has failed. This is because there is no magnetic disk.

For example, if the magnetic disk 101 fails, the parity P written on the magnetic disk 101 is written.
P1 and PP2 cannot be used, but magnetic disk 1
The parity PP2 from 02 and the parity PP1 from the magnetic disk 104 can be used. The existence of parity is guaranteed even when another magnetic disk fails. Parity P1 using these parities PP1 to PP4
~ P6 can be obtained and the data can be restored.

Although the magnetic disk is used as the storage device in the above-mentioned embodiment, other storage devices such as an optical disk may be used.

[0018]

As described above, according to the present invention, the parity bits are collectively stored in the storage device for storing the data string, so that an increase in the number of storage devices is prevented and a more compact hardware configuration is provided. It is possible to provide a parallel storage controller capable of

[Brief description of drawings]

FIG. 1 is a block diagram of a parallel storage control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a parallel storage controller.

[Explanation of symbols]

 101 to 104 ... Magnetic disk 120 ... Binary counter 121, 125 ... 4-bit shift register 122 ... Parity generation circuit 123 ... Data conversion circuit 124 ... Data selection circuit

Claims (1)

[Claims] 1. A parallel storage control device for storing a data string in a separate storage device for each bit forming the data string, and a parity operation means for obtaining a parity for one data string, and the parity operation means. Temporary storage means for sequentially storing the calculated parity by the number of bits forming the data string, and the temporary storage means storing the parity when the number of bits forming the data string is stored in the temporary storage means. And a parity storage control means for storing the parity in a separate storage device in the same manner as the storage for each bit.