JPH0232641B2 - - Google Patents
Info
- Publication number
- JPH0232641B2 JPH0232641B2 JP55129693A JP12969380A JPH0232641B2 JP H0232641 B2 JPH0232641 B2 JP H0232641B2 JP 55129693 A JP55129693 A JP 55129693A JP 12969380 A JP12969380 A JP 12969380A JP H0232641 B2 JPH0232641 B2 JP H0232641B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- input voltage
- input
- output
- zener diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
Description
【発明の詳細な説明】
本発明は入力電圧の変化に応じて出力電圧を変
化させることにより、入力電圧が高くなつた場合
に制御用トランジスタのコレクタ損失の増加を少
なくさせた直流電源回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DC power supply circuit that reduces the increase in collector loss of a control transistor when the input voltage increases by changing the output voltage in response to changes in the input voltage.
第１図は従来の直流安定化電源回路の例を示す
回路図で、TR1は電流制御用トランジスタ、A1
は誤差増幅器、CD1は基準電圧用のツエナーダイ
オード、R1はベースバイアス用の抵抗、R2はツ
エナーダイオードCD1のバイアス用の抵抗、R3，
R4は出力電圧分圧用の抵抗、RLは負荷抵抗、C1
は交流除去用のバイパスコンデンサである。 Figure 1 is a circuit diagram showing an example of a conventional DC stabilized power supply circuit, where TR 1 is a current control transistor, A 1
is an error amplifier, CD 1 is a Zener diode for reference voltage, R 1 is a resistance for base bias, R 2 is a resistance for bias of Zener diode CD 1 , R 3 ,
R 4 is the output voltage dividing resistor, RL is the load resistor, C 1
is a bypass capacitor for AC removal.
次に動作について、入力電圧VioがΔVio増加し
たときの出力安定化作用を説明する。入力電圧が
ΔVio増加すると、抵抗R1を通してトランジスタ
TR1のベース電流が増加し、これにともない出力
電流が大となり負荷抵抗RLの端子出力電圧も
VOUT増加する。同時に出力電圧は抵抗R3および
抵抗R4によつて分圧され、誤差増幅器A1の誤差
検出用の端子に加えられる。また出力電圧は抵抗
R2を介してツエナーダイオードCD1にかかり、こ
れが誤差増幅器A1の一定の基準電圧Vsとなつて
いる。従つて誤差増幅器A1では基準電圧Vsと誤
差検出電圧を比較し、誤差分が検出されこれがト
ランジスタTR1のベースに加わる。誤差分が正の
ときはベース電流を小に、誤差分が負のときはベ
ース電流を大にするようにしてトランジスタTR1
のエミツタ出力電流が一定になるように制御す
る。このときのトランジスタTR1のコレクタ損失
は次式で表わされる。 Next, regarding the operation, the output stabilizing effect when the input voltage V io increases by ΔV io will be explained. As the input voltage increases ΔV io , the transistor through resistor R1
The base current of TR 1 increases, the output current increases, and the terminal output voltage of the load resistor RL also increases.
V OUT increases. At the same time, the output voltage is divided by resistor R3 and resistor R4 and applied to the error detection terminal of error amplifier A1 . Also, the output voltage is a resistance
It is applied to the Zener diode CD 1 via R 2 , and this serves as a constant reference voltage V s for the error amplifier A 1 . Therefore, the error amplifier A1 compares the reference voltage Vs with the error detection voltage, detects the error amount, and applies this to the base of the transistor TR1 . When the error amount is positive, the base current is made small, and when the error amount is negative, the base current is made large .
The emitter output current is controlled to be constant. The collector loss of the transistor TR1 at this time is expressed by the following equation.
Pc＝Ip×（Vio＋ΔVio−Vput ……(1)
＝Ip×（Vio−Vput）＋Ip×ΔVio ……(2)
ただし、Pc：TR1のコレクタ損失（Ｗ）
Ip：出力電流(A)
Vio：入力電圧の最低値（Ｖ）
ΔVio：入力電圧の変化分（Ｖ）
Vput：出力電圧（Ｖ）
トランジスタTR1は(1)式又は(2)式によるPc（Ｗ）
の発熱を十分に放散できるような放熱器を必要と
する。普通、入力電圧は大きく変動しΔVioが
（Vio−Vput）に比べて相当大きな値となるので最
悪条件を考えて大容量の放熱器が使用される。P c = I p × (V io + ΔV io −V put …(1) = I p × (V io −V put ) + I p ×ΔV io …(2) However, P c : Collector loss of TR 1 (W) I p : Output current (A) V io : Minimum value of input voltage (V) ΔV io : Change in input voltage (V) V put : Output voltage (V) Transistor TR 1 can be calculated using formula (1) or P c (W) according to formula (2)
A radiator is required that can sufficiently dissipate the heat generated by the Normally, the input voltage fluctuates widely and ΔV io becomes a considerably larger value than (V io −V put ), so a large-capacity heatsink is used considering the worst case conditions.
例えば、Vio＝24V、ΔVio＝7.2V（Vioの30％
増）、Vput＝22V、Ip＝1AのときTR1のコレクタ
損失Pcは(2)式から
Pc＝１×（24−22）＋１×7.2＝9.2（Ｗ）
となる。ところがΔVioが無ければPcは2Wです
む。即ち、本来2Wしかないはずのコレクタ損失
が入力電圧の30％増加によつて9.2Wと4.6倍にも
なる。 For example, V io = 24V, ΔV io = 7.2V (30% of V io
When V put = 22 V and I p = 1 A, the collector loss P c of TR 1 is calculated from equation (2) as follows: P c = 1 x (24-22) + 1 x 7.2 = 9.2 (W). However, if there is no ΔV io , P c is only 2W. In other words, the collector loss, which should originally be only 2W, increases by 4.6 times to 9.2W due to a 30% increase in input voltage.
本発明はこの欠点を解決するために、入力電圧
の変化（上昇）に応じて出力電圧を変化（上昇）
させることによつてTR1のコレクタ損失の増加を
従来よりも少なくし、使用するトランジスタ及び
放熱器を小形にすることを目的とする。 In order to solve this drawback, the present invention changes (increases) the output voltage according to changes (increases) in the input voltage.
The purpose of this is to reduce the increase in the collector loss of TR 1 compared to the conventional one, and to downsize the transistor and heat sink used.
第２図は本発明による直流電源回路の動作の一
部を説明するために示す回路図で、第１図と同一
記号は同一部分を示す。R5およびR6は本発明の
要部で、入力電圧を分圧して誤差増幅器A1の基
準電圧入力端に加えるためのバイアス抵抗、C2
は交流除去用のバイパスコンデンサである。 FIG. 2 is a circuit diagram shown to explain part of the operation of the DC power supply circuit according to the present invention, and the same symbols as in FIG. 1 indicate the same parts. R 5 and R 6 are the main parts of the present invention, and are bias resistors for dividing the input voltage and applying it to the reference voltage input terminal of the error amplifier A 1 , and C 2
is a bypass capacitor for AC removal.
動作は第１図とほぼ同じであるが、第２図では
入力電圧が抵抗R5およびR6によつて分圧され誤
差増幅器A1の基準電圧端子に加わる。従つて基
準電圧VsはツエナーダイオードCD1の端子電圧
に、抵抗R6によつて決まる電圧を加えた値とな
る。また誤差増幅器A1の誤差検出用端子には、
第１図と同じように出力電圧を抵抗R3およびR4
で分圧したものが入力される。従つて誤差増幅器
A1は入力電圧によつて変動する基準電圧Vsと出
力電圧を分圧した値を比較して誤差分を検出し、
これをトランジスタTR1のベース電流に加える。
これにより出力電圧が制御される。 The operation is substantially the same as in FIG. 1, but in FIG. 2 the input voltage is divided by resistors R5 and R6 and applied to the reference voltage terminal of error amplifier A1 . Therefore, the reference voltage V s is the sum of the terminal voltage of the Zener diode CD 1 and the voltage determined by the resistor R 6 . In addition, the error detection terminal of error amplifier A1 is
Connect the output voltage to resistors R 3 and R 4 as in Figure 1.
The divided pressure is input. Therefore the error amplifier
A1 detects the error by comparing the reference voltage V s that varies depending on the input voltage and the divided output voltage.
Add this to the base current of transistor TR1 .
This controls the output voltage.
次に、この場合についてのトランジスタのコレ
クタ損について説明する。まず入力電圧がΔVio
だけ変化するとA1の端子の電圧は
ΔVs＝R6／R5＋R6×ΔVio ……(3)
だけ変化する。 Next, the collector loss of the transistor in this case will be explained. First, the input voltage is ΔV io
If the voltage at the terminal of A1 changes by ΔV s = R 6 /R 5 + R 6 ×ΔV io ……(3).
ゆえに、出力電圧もそれに比例して次式の
ΔVputだけ変化する。 Therefore, the output voltage also changes proportionally by ΔV put in the following equation.
ΔVput＝R3＋R4／R4×ΔVs
＝R3＋R4／R4×R6／R5＋R6ΔVio ……(4)
＝ｋ×ΔVio ……(5)
ただし
ｋ＝R6（R3＋R4）／R4（R5＋R6） ……(6)
この場合のTR1におけるコレクタ損失Pc′は次
式のようになる。 ΔV put =R 3 +R 4 /R 4 ×ΔV s =R 3 +R 4 /R 4 ×R 6 /R 5 +R 6 ΔV io ...(4) =k×ΔV io ...(5) However, k=R 6 (R 3 + R 4 )/R 4 (R 5 + R 6 )...(6) In this case, the collector loss P c ' in TR 1 is expressed as follows.
Pc′＝Ip｛（Vio＋ΔVio）−（Vput＋ΔVput）｝
＝Ip（Vio−Vput）＋IpΔVio−IpΔVput ……(7)
＝Ip（Vio−Vput＋IpVio（１−ｋ） ……(7)′
(2)式と(7)式を比較すると、本発明によればIp
ΔVput（Ｗ）だけTR1のコレクタ損失を従来の方法
よりも小さくできることが判る。P c ′=I p {(V io + ΔV io )−(V put + ΔV put )} = I p (V io −V put )+I p ΔV io −I p ΔV put ……(7) = I p (V io −V put +I p V io (1-k) ...(7)' Comparing equations (2) and (7), according to the present invention, I p
It can be seen that the collector loss of TR 1 can be made smaller by ΔV put (W) than in the conventional method.
例えば、入力電圧Vio：24V、入力電圧の変化
ΔVio：7.2V（＋30％）、出力電圧Vput：22V、出力
電流1Aの安定化電源を考える。出力電圧の変動
ΔVputが0Vの場合（従来の方式）のコレクタ損失
Pcと、ΔVputを2.2V（＋10％変動）にした場合
（本発明による方式）のコレクタ損失Pc′を求める
と、前者の場合(2)式からPcは9.2Wとなり、後者
の場合(7)式からPc′は7Wとなる。即ち、損失が従
来に比べて76％に低減できるのでTR1を小形にで
き、放熱器も小さなものですむ。 For example, consider a stabilized power supply with input voltage V io : 24V, input voltage change ΔV io : 7.2V (+30%), output voltage V put : 22V, and output current 1A. Collector loss when output voltage fluctuation ΔVput is 0V (conventional method)
P c and collector loss P c ' when ΔV put is set to 2.2 V (+10% fluctuation) (method according to the present invention), in the former case P c is 9.2 W from equation (2), and in the latter case, P c is 9.2 W. In this case, P c ′ becomes 7W from equation (7). That is, since the loss can be reduced to 76% compared to the conventional one, TR 1 can be made smaller, and the heat sink can also be made smaller.
第３図は本発明の一実施例を示す回路図で第２
図の回路に対して定電圧ダイオードただし、本発
明はCD3を使用せずCD2のみを使用することも可
能であり、以下両者について説明する。 FIG. 3 is a circuit diagram showing one embodiment of the present invention.
However, in the present invention, it is also possible to use only CD 2 without using CD 3 , and both will be explained below.
(イ) CD3を使用しない場合
CD2は入力電圧（Vio＋ΔVio）が一定限度電
圧VTを超えたときに初めて電流が流れるよう
なツエナー電圧を有するものにする。入力電圧
がVT以下のときはCD2が非導通状態にあるた
め、本回路は第１図に示される従来の回路と同
様な動作となつて、入力電圧を変化しても出力
電圧Vputは一定に保たれ、その代りにTR1のコ
レクタ損失が入力電圧の上昇と共に増加する。
入力電圧がVTを超すとCD2が導通するので、
第２図に示される本発明の回路と同様の動作と
なつて出力電圧Vputが少しづつ上昇することに
よつてTR1のコレクタ損失の増加割合が小さく
なりTR1が保護される。(B) When CD 3 is not used CD 2 should have a Zener voltage such that current flows only when the input voltage (V io + ΔV io ) exceeds a certain limit voltage VT . When the input voltage is below V T , CD 2 is in a non-conducting state, so this circuit operates in the same way as the conventional circuit shown in Figure 1, so that even if the input voltage changes, the output voltage V put is kept constant and instead the collector loss of TR 1 increases with increasing input voltage.
When the input voltage exceeds V T , CD 2 becomes conductive, so
The operation is similar to that of the circuit of the present invention shown in FIG. 2, and by increasing the output voltage Vput little by little, the rate of increase in the collector loss of TR 1 becomes smaller and TR 1 is protected.
(ロ) CD3を使用する場合
CD3は入力電圧が一定限度電圧VT′以下のと
きは前記(イ)の場合の動作をし、入力電圧の上昇
と共に出力電圧も上昇するが、出力電圧が一定
値に達した場合はそれ以上に出力電圧が上昇し
ないように制限して負荷回路を保護することを
目的とする。ただしVT′は前記VTより高い電圧
に選ぶ。(b) When using CD 3 CD 3 operates as in case (a) above when the input voltage is below a certain limit voltage V T ', and the output voltage increases as the input voltage increases, The purpose is to protect the load circuit by limiting the output voltage from increasing further when it reaches a certain value. However, V T ′ is selected to be a higher voltage than the above-mentioned V T .
入力電圧がVT′よりも低いときはCD3の両端
にかかる電圧がCD3のツエナー電圧値よりも小
さく、CD3は非導通状態であつて本回路は前記
(イ)と同様の動作をする。しかし、入力電圧が
VT′よりも高くなるとCD3が導通して両端の電
圧を一定値に保つので出力電圧は入力電圧が上
昇しても一定に保たれて従来の回路（第１図）
と同様に動作する。 When the input voltage is lower than VT', the voltage applied across CD 3 is smaller than the Zener voltage value of CD 3 , CD 3 is in a non-conducting state, and this circuit operates as described above.
The operation is similar to (a). However, the input voltage
When it becomes higher than V T ', CD 3 becomes conductive and keeps the voltage at both ends at a constant value, so the output voltage remains constant even if the input voltage increases.
works the same way.
以上説明したように、本発明は入力電圧に応じ
て基準電圧を変化させることによつて出力電圧を
変化させて、入力電圧が上昇しても制御用トラン
ジスタのコレクタ損失の増加程度を減少させるこ
とができるので、制御用トランジスタおよびその
放熱器を小形にできる。 As explained above, the present invention changes the output voltage by changing the reference voltage according to the input voltage, thereby reducing the degree of increase in the collector loss of the control transistor even if the input voltage increases. Therefore, the control transistor and its heat sink can be made smaller.
第１図は従来の直流電源回路、第２図は本発明
による直流電源回路の動作の一部を説明するため
の回路図、第３図は本発明の一実施例を示す回路
図である。
TR1……制御用トランジスタ、A1……誤差増
幅器、CD1，CD2，CD3……ツエナーダイオード、
R3，R4，R5，R6……分圧用抵抗、C1，C2……バ
イパスコンデンサ。
FIG. 1 is a conventional DC power supply circuit, FIG. 2 is a circuit diagram for explaining part of the operation of the DC power supply circuit according to the present invention, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. TR 1 ... Control transistor, A 1 ... Error amplifier, CD 1 , CD 2 , CD 3 ... Zener diode,
R 3 , R 4 , R 5 , R 6 ... Voltage dividing resistor, C 1 , C 2 ... Bypass capacitor.
Claims (1)
力端とする電流制御用トランジスタと、エミツタ
出力を分圧してそれぞれ出力検出電圧および基準
電圧とする分圧用抵抗およびツエナーダイオード
と、該ツエナーダイオードによる基準電圧と出力
検出電圧を比較して誤差分を検出し、これを前記
トランジスタのベースに加え出力を制御する誤差
増幅器とを備えた直流電源回路において、コレク
タ入力電圧を分圧して前記基準電圧に加える入力
電圧分圧用抵抗を設け、さらに入力電圧が一定値
を越えたとき導通する第２のツエナーダイオード
を前記入力電圧分圧用抵抗に直列に設けたことを
特徴とする直流電源回路。 ２ 特許請求の範囲第１項記載の直流電源回路に
おいて、入力電圧が一定値を越えたとき導通する
第３のツエナーダイオードを前記誤差増幅器の基
準電圧入力端子に設けたことを特徴とする直流電
源回路。[Claims] 1. A current control transistor having a collector and an emitter as input and output terminals, respectively, a voltage dividing resistor and a Zener diode that divides the emitter output into an output detection voltage and a reference voltage, respectively, and the Zener diode. In a DC power supply circuit equipped with an error amplifier that compares a reference voltage and an output detection voltage, detects an error, and adds this to the base of the transistor to control the output, the collector input voltage is divided to obtain the reference voltage. 1. A DC power supply circuit comprising: an input voltage dividing resistor added to the input voltage dividing resistor, and further comprising a second Zener diode which becomes conductive when the input voltage exceeds a certain value and is connected in series with the input voltage dividing resistor. 2. The DC power supply circuit according to claim 1, wherein a third Zener diode that becomes conductive when the input voltage exceeds a certain value is provided at the reference voltage input terminal of the error amplifier. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12969380A JPS5755426A (en) | 1980-09-18 | 1980-09-18 | Direct current power supply circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12969380A JPS5755426A (en) | 1980-09-18 | 1980-09-18 | Direct current power supply circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5755426A JPS5755426A (en) | 1982-04-02 |
| JPH0232641B2 true JPH0232641B2 (en) | 1990-07-23 |
Family
ID=15015849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12969380A Granted JPS5755426A (en) | 1980-09-18 | 1980-09-18 | Direct current power supply circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5755426A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4731830A (en) * | 1985-10-04 | 1988-03-15 | Gte Communication Systems Corporation | Nonsaturating interface supply |
| CN104850163B (en) * | 2015-05-12 | 2016-07-06 | 苏州工业职业技术学院 | A kind of DC-stabilized circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128420B2 (en) * | 1973-03-17 | 1976-08-19 | ||
| JPS5337037B2 (en) * | 1974-04-17 | 1978-10-06 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128420U (en) * | 1974-08-23 | 1976-03-01 | ||
| JPS5337037U (en) * | 1976-09-07 | 1978-04-01 |
-
1980
- 1980-09-18 JP JP12969380A patent/JPS5755426A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128420B2 (en) * | 1973-03-17 | 1976-08-19 | ||
| JPS5337037B2 (en) * | 1974-04-17 | 1978-10-06 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5755426A (en) | 1982-04-02 |
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