JPH0232552A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize low resistivity of a semiconductor layer and to prevent low concentration of a semiconductor region which has impurity by injecting impurity with energies different according to the depth direction of a semiconductor layer. CONSTITUTION:A semiconductor region 1 which has impurity is composed of source/drain regions 1a, 1b on a substrate 11, and an electrode 2 which consists of a semiconductor layer is composed of polysilicone electrodes 2a, 2b which are buried inside a contact hole. Impurity is injected into sections 31a, 31b, 32a, 32b with energies different according to the depth direction of a semiconductor layer 22.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Summary of the invention]

The present invention provides a method for manufacturing a semiconductor device having an electrode made of a semiconductor layer on a semiconductor region containing impurities, by implanting impurities with different energies in the depth direction of the semiconductor layer. In addition to achieving low resistance, it is also possible to prevent the impurity-containing semiconductor region from becoming low in concentration.

[Conventional technology]

In the field of semiconductor devices, there is a demand for smaller and more integrated layers, and for this reason, miniaturization is progressing further. With such miniaturization, when forming a contact hole in the manufacture of a semiconductor device, the opening size of the contact hole is becoming smaller and the aspect ratio of the contact hole is increasing. For this reason, it has become difficult to make contact by burying a wiring material such as metal in such a contact hole. This is because there may be cases where the wiring material is not sufficiently filled to the bottom of the contact hole.

One way to solve this problem is to use a material with good coverage (e.g. polysilicon) and fill the contact hole with a polysilicon film by, for example, the LP (low pressure)-CVI) method. A conceivable method is to flatten the surface using an etch bank and then conduct wiring using metal or the like to make contact.

In this case, in order to lower the resistance of the polysilicon film used for making contact, there is a method of activating the polysilicon by performing high concentration ion implantation. However, depending on the impurity to be ion-implanted, it may not be sufficiently implanted into the polysilicon, making it impossible to lower the resistance. especially,
When ions are implanted into a material buried in an opening with a large aspect ratio, the impurity may not be sufficiently implanted into the opening, and as a result, the resistance may not be lowered sufficiently and contact may not be established. For example, with boron, which has a low solid solubility limit and a small diffusion coefficient in polysilicon, when the polysilicon film is thick (when the aspect ratio is large), a pure polysilicon layer remains under the polysilicon, making it difficult to make contact. There are things I can't do.

Figure 3 shows the measurement results of the spreading resistance when boron ions were implanted into an 8,000-layer thick polysilicon layer.
From this data, it will be understood that there are cases where a pure polysilicon layer remains and the resistance of the polysilicon layer cannot be sufficiently lowered. That is, in Figure 3, the horizontal axis shows the depth and the vertical axis shows the ion implantation amount, and the higher the vertical axis, the larger the ion implantation and the lower the resistance. B for film thickness 8000 people
High-concentration ion implantation at 60KeV and 2X10'6/cot was performed using "Ft", followed by lamp annealing at 110
The figure shows the spreading resistance measurement profile when applied at 0°C for 10 seconds (in Nz). It is clear from the figure that ion implantation is performed in the portion I of polysilicon up to a depth of 6,400 mm; It can be seen that a pure polysilicon portion remains in the 1,600-person region (2) below the silicon film. In this experiment, in order to eliminate the influence on the polysilicon layer of the mounting area lv, the SiO,j+l area ■
was formed with a thickness of 300θ.

Another problem associated with miniaturization is that over-etching during RIE for forming contact holes (to completely etch the interlayer film, etc. in which holes are to be formed is excessively etched), / Diffused impurities in the drain diffusion layer are absorbed, resulting in so-called erosion of the diffusion layer, which may lead to a decrease in impurity concentration.

This can be explained as follows using FIG.

FIG. 4 shows t31-'! on an N-type (100) substrate. After forming the source/drain regions by ion implantation under the conditions of 20KeV and 3X10"/ct, over-etching of I (IE) for forming contact holes was carried out by 50, 100, and 200 people, respectively. Then, a further 8,000 polysilicon films were deposited and heated at 60 KeV and 2
10"/aJi" ion implantation and lamp annealing for 11
The results of measuring the spreading resistance after conducting the test at 00° C. for 10 seconds are shown below.

From Figure 4, in the case of 50 artificial sonography, ■, in the case of etching of 100 people, ■, and also in the case of etching of 200 people.
However, it can be seen that the impurity concentration in the source/drain region (2) has decreased. It can be seen from this that the source/drain region is eaten away by the amount of overetching, resulting in a decrease in concentration.

That is, in this case, the impurity concentration of the polysilicon layer decreases as it approaches the source/drain region, and the resistance value increases, but the greater the etching, the more impurities are absorbed into the polysilicon from the source/drain region. It can be seen that this results in a reduction in the concentration of the source and drain regions.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and when obtaining a structure in which an electrode made of a semiconductor is formed on a semiconductor region containing impurities, it is possible to reduce the resistance of the semiconductor for the electrode and achieve a uniform impurity distribution. This makes it possible to make good contact even when manufacturing miniaturized semiconductor devices, and even when a contact hole is formed and an electrode made of the semiconductor is embedded in the structure, the contact hole It is an object of the present invention to provide a method for manufacturing a semiconductor device that can also compensate for the influence on an underlying impurity-containing semiconductor layer, such as a source/drain region, during over-etching when forming a semiconductor device.

[Technical Means for Solving the Problems] In order to solve the above-mentioned problems, the method for manufacturing a semiconductor device according to the present invention includes a manufacturing method for a semiconductor device having an electrode made of a semiconductor layer on a semiconductor region containing impurities. In the manufacturing method, a technical measure is taken to implant impurities with different energies in the depth direction of the semi-quartet layer.

The configuration of the present invention will be described below using the upper diagram of FIG. 1 showing an embodiment of the present invention, which will be described in detail later.

That is, the present invention is a method for manufacturing a semiconductor device having an electrode made of a semiconductor layer on a semiconductor region containing impurities. The semiconductor region 1 having the above structure is a source/drain region 1a, lb on a substrate 11, and the electrode 2 made of a semiconductor layer is a polysilicon electrode 2a, 2b buried in a contact hole. In the present invention, impurities are implanted with different energies in the depth direction of the semiconductor layer 22, as illustrated in FIGS. 1(d) and 1(e).

That is, in the illustrated example, first, shallow initial stage ion implantation is performed as shown in FIG. 1(d) (the implanted portion is denoted by 31a).

31b), then a second stage of ion implantation is performed deeper than that as shown in FIG.
a, 32 b).

In the above example, the semiconductor region 1 containing impurities is the source/drain region 1a, lb of the substrate 11, but is not limited thereto, and may be, for example, a polysilicon resistor containing an impurity. Further, although the electrode 2 made of a semiconductor layer is polysilicon formed as a contact electrode in FIG. 1, it is of course not limited to this form, and any electrode formed of a semiconductor layer may be used.

[Effect]

As described above, the method for manufacturing a semiconductor device of the present invention includes the electrode 2
Since impurities are implanted with different energies in the depth direction of the semiconductor layer forming the semiconductor layer, for example, in FIG. By lowering the resistance of the semiconductor layer 22 and then performing a deep second-stage high-energy ion implantation as shown in FIG. In this way, impurities are introduced into the areas where the electrodes are formed to ensure sufficient contact as electrodes, and at the same time, the so-called erosion caused by the absorption of impurities in the underlying semiconductor regions 1 (source/drain regions 1a, 1b) containing impurities is compensated for. can do.

As a result, the conventional problem of non-conducting parts (such as pure polysilicon layers) remaining under the semiconductor layer even after ion implantation, and impurity-containing semiconductor regions 2 (source/drain regions 2a, 2b, etc.). ) can be prevented from decreasing in impurity concentration. Therefore, a highly reliable semiconductor device with good electrical connections can be obtained.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. It should be noted that, as a matter of course, the present invention is not limited to the examples described below.

FIGS. 1(a) to 1(g) sequentially show cross-sectional views of the manufacturing process of a semiconductor device according to this embodiment.

In this embodiment, as shown in FIG. 1(a), the substrate 11
After forming the gate electrode 12 on the (silicon substrate in this example),
Source/drain regions 1a and 1b are created. In this embodiment, the source/drain regions 1a and lb are
0 corresponding to semiconductor region 1 containing impurities of the present invention In this example, boron ions were implanted to form the P channel source/drain region, but the ions to be implanted are arbitrary, and the N channel source/drain region It may be specified as However, in the case of boron ion implantation, conventional problems were serious, so the present invention can be effectively used for boron ion implantation, and therefore boron is used in this example. Thereafter, an interlayer insulating film 14 is formed, and contact holes 13a and 13b are opened therein. In this example, the contact holes 13a and 13b were formed using dry etching, which is a typical method, and in particular by RIE, but in this case, in order to complete the openings, over-etching was unavoidable. Therefore, the impurity-containing semiconductor regions 1 underlying the contact holes 13a and 13b are overetched, and in this example, these are the source/drain regions 1a and 1b, so the absorption of impurities due to this, the so-called " In the figure, 15 is a gate oxide film (Stow in this case), and 16 is an element isolation region (LOGO3). Formation of gate electrode 12, formation of source/drain regions 1a and lb forming impurity-containing semiconductor layer 1, contact holes 13a and 13b
For the formation, etc., ordinary means in this type of technology can be used as appropriate. For example, the gate electrode can be formed of polysilicon by CVL), and the contact hole 13a
, 13b can be formed using dry etching, typically RIE as in this example.

Next, as shown in FIG. 1(b), a semiconductor layer 21 on which the electrode 2 is to be formed is formed. In this example, polysilicon was used as the semiconductor, and the semiconductor (polysilicon) layer 21 was formed particularly by LP (low pressure)-CVD. This forms a contact hole 13a.

13b is filled with the semiconductor. In this example, since this is polysilicon, the filling can be done well with good coverage. In this example, this polysilicon will eventually form the electrode 2 that will be connected to the wiring (metal wiring 4°, see FIG. 1(g)).

Next, an etch bank is performed to planarize the semiconductor 22 only in the contact holes 13a and 13b as shown in FIG.
(polysilicon) is embedded.

Furthermore, in this embodiment, as shown in FIG. 1(d), the semiconductor 22 (
A first stage of ion implantation is performed to lower the resistance of polysilicon 22). This is done by high-concentration ion implantation, for example, using Bh'z" as ions, 60KeV, 2X10"
Ion implantation is performed under /- conditions. The first stage ion implantation parts 31a and 31b are schematically indicated by X marks.

Next, using the same mask as in the first stage of ion implantation,
A second stage of ion implantation is performed. This is performed with higher energy than the first stage ion implantation, and the ions are implanted deeper. As a result, the structure of FIG. 1(e) is obtained. In FIG. 1, the second stage high-energy ion implantation parts 32a and 32b are also schematically indicated with x marks. In the ion implantation, ions are also implanted into the non-implanted part (the part considered to be pure polysilicon) below the buried semiconductor 22 to lower the resistance there, and to reduce the resistance of the first part.
In Figure (a), the erosion of the underlying impurity-containing polysilicon layer 1 (source/drain regions 1a, lb) due to overetching when contact holes 13a, 13b are opened using dry etching is compensated for. For example, if the polysilicon film that is the embedded semiconductor 22 is 8,000 thick, the second stage of high-energy ion implantation is performed at 240 KeV and 1 x 101 s/- for B0 ions.
This can be done under the following conditions.

Thereafter, activation annealing is performed to obtain the structure shown in FIG. 1(f). Reference numeral 2 in the figure indicates an electrode made of a semiconductor, and in this example, it is made up of two polysilicon snow scrapers 2a and 2b.

Next, as shown in FIG. 1(g), wiring 4 is formed of metal (for example, aluminum) or the like. By obtaining a semiconductor device in this manner, a low resistance and uniform impurity distribution can be obtained, and therefore, stable contact can be made.

When the spreading resistance of the buried semiconductor electrode 2 (polysilicon) and the source/drain regions 1a and lb, which are semiconductor regions containing impurities, in this example formed as described above was measured, the data shown in FIG. 2 was obtained. It was done. As shown in FIG. 2, the spreading resistance curve (2) shows that a very uniform impurity distribution is obtained. That is, the polysilicon electrode (portion indicated by 1 in FIG. 2) has a sufficiently low resistance and is not eaten away by impurities in the source/drain region (portion indicated by V in FIG. 2).

As described above, in this embodiment, a buried polysilicon film is used as the semiconductor of the electrode 2, and the present invention is used to realize contact between the P channel source/drain ion-implanted layer, which is the underlying impurity-containing semiconductor region l, and the metal wiring 4. However, even if the thickness of the buried polysilicon film forming the electrode 2 is 6000 Å or more, and there was a problem with making contact in the past,
High concentration ion implantation (first stage ion implantation. Figure 1(d)
As a result of implanting impurities at different energies according to the present invention in a manner that combines high-energy ion implantation (see FIG. 1(e)) and high-energy ion implantation (second-stage ion implantation, see FIG. 1(e)), The pure polysilicon portion at the bottom of the film is eliminated, and the etching process is performed while compensating for the erosion of la and lb of the underlying source/drain region due to over-etching of dry etching (l (IM)) when forming contact holes 13a and 13b. We were able to make contact.

In addition to the above-described embodiments, the present invention can be applied to the formation of parts that require ion implantation at a uniform concentration. It can be applied to the manufacturing of semiconductor devices having processes such as the formation of

〔Effect of the invention〕

As described above, according to the present invention, when manufacturing a semiconductor device having an electrode made of a semiconductor layer, ion implantation at a uniform concentration can be achieved, and for example, when the electrode is a contact electrode, good contact can be made. , even if the electrode is embedded by forming a contact hole,
It is possible to reduce the influence on the base.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(g) are cross-sectional views showing an embodiment of the present invention in the order of steps. FIG. 2 is a diagram showing the effect of this embodiment. FIGS. 3 and 4 are diagrams for explaining problems in the conventional technology. 1... Semiconductor region containing impurities (source/drain region), 2... Electrode made of semiconductor layer (polysilicon layer), 31a, 31b... First stage (initial stage) ion implantation (high concentration ion implantation), 32a, 32b...second stage ion implantation (high energy ion implantation).

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device having an electrode made of a semiconductor layer on a semiconductor region containing impurities, characterized in that impurities are implanted with different energies in the depth direction of the semiconductor layer. A method for manufacturing a semiconductor device.