JPH023149A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To unnecessitate a sense amplifier of high sensitivity even when a device is high-integrated and to secure a noise margin by specifying a back gate electric potential to change the threshold voltage of a transistor with the holding electric potential of a cell capacitor. CONSTITUTION:A writing word line WWL is made into 'H' selectively, a transistor Q1 is made on, a voltage based on the writing data of a writing bit line WBL is impressed on a cell capacitor C2 and is held, and writing is executed. Then, a back gate electric potential VBG for a memory Q2 held by the C2 changes, the threshold voltage of the Q2 changes with the change of the electric potential VBG, and information is stored. Next, a word line RWL is made into 'H', the current change of a reading bit line RBL by the threshold voltage change of the Q2 by the change of the electric potential VBG is detected, and reading is executed. The electric potential of the C2 specified by the electric potential VBG becomes approximately the electric potential of writing data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory cell of a semiconductor memory device constituted by MIS type transistors.

[Conventional technology]

FIG. 4 is a cross-sectional view showing one memory cell of a semiconductor memory device constituted by a conventional MIS type transistor. An n-diffusion region 2.3 is formed on the inner surface of the upper part of the n-diffusion region 2.3, and a gate electrode 4 made of polycrystalline silicon or the like is formed on the semiconductor substrate 1 between the n-diffusion regions 2.3 via a gate dielectric film 5. . Further, a hill plate 7 made of polycrystalline silicon or the like is formed from above the end of the n-diffusion region 3 to an interlayer insulating F16 formed protruding into the surface of the semiconductor substrate 1 via a gate dielectric M8. . In addition, a bit line BL (not shown) is provided in the n diffusion region 2.
However, a word IWL (not shown) is electrically connected to the gate electrode 4. Further, the p-semiconductor substrate 1 is at a potential ■. It is set to 0.

FIG. 5 is an equivalent circuit diagram of FIG. 4. As shown in the figure, the gate electrode 4. The selection transistor Q1 is formed by the n-diffusion region 2.3, and the n-diffusion region 3.3 on the cell plate 7°, the gate dielectric film 8, and the semiconductor substrate 1. ffi insulation 11
The region 9 between the regions 6 and 6 forms a cell capacitor C1.

In such a configuration, writing is performed by applying an "H" level to the word line WL selected by a row decoder or the like to turn on the selection transistor Q1, and writing is applied to the bit line BL via an input/output line (not shown). This is performed by applying a voltage based on data to the cell capacitor C1 and accumulating charges in the cell capacitor C1.

On the other hand, in reading, the selected word line WL becomes "H", the transistor Q1 is turned on, and the charge accumulated in the cell capacitor C1 is drawn out to the bit line F3L, and is detected by a voltage sensing type amplifier (not shown). It is done by

Note that the accumulated charge IQ is determined by Q=CVo. C
is the container value of the capacitor C1, and vo is the potential applied to the cell capacitor C1 during writing.

[Problem to be solved by the invention]

A semiconductor memory device constructed using conventional MIS type transistors is constructed as described above, and data reading is performed by taking charge accumulated in a cell capacitor onto a bit line and detecting minute potential changes appearing on this bit line. In the voltage sense type, comparison and judgment were performed using a voltage sense amplifier.

However, as the integration of memories progresses, the capacitance of cell capacitors becomes smaller and the amount of charge stored decreases, so a highly sensitive sense amplifier is required and the circuit becomes complicated. Furthermore, since a smaller potential change is detected, the noise margin deteriorates. Furthermore, as the circuit becomes more complex, there is a problem in that the readout time becomes slower.

This invention was made in order to solve the above-mentioned problems, and its purpose is to obtain a semiconductor memory device that does not require a highly sensitive sense amplifier and does not deteriorate the noise margin even though the device is integrated. do.

(Means for Solving the Problems) A semiconductor memory device according to the present invention selectively activates a data input line for receiving write data from the outside and a data output line for outputting read data to the outside. A write word line, a write bit line that is selectively connected to the data input line during writing, a read word line that is selectively activated during reading, and a current sensing type sense amplifier that is selectively connected during reading. a first MI having a read bit line connected to the data output line, a gate connected to the write word line, and a drain connected to the write bit line.
an S type transistor, a second MIS type transistor whose gate is connected to the read word line, whose drain is connected to the power supply, and whose source is connected to the read bit line; the source of the first MIS type transistor; and the second MIS type transistor. a cell capacitor inserted between the back gates of the transistors, the back gate potential of the second MIS transistor is defined by the potential held in the cell capacitor, and the threshold value of the second MIS transistor is defined by the potential held in the cell capacitor; Information is stored by changing the mechanical bias according to the value of the back gate potential.

[Effect]

In this invention, the back gate potential that changes the threshold voltage of the second MIS transistor is defined by the potential held in the cell capacitor, and is therefore not affected by the maximum capacitance of the cell capacitor.

〔Example〕

FIG. 1 is a sectional view showing one memory cell of a MIS semiconductor memory device which is an embodiment of the present invention. As shown in the figure, an n-diffusion region 2.3 is formed on the inner surface of the p-semiconductor substrate 1. The entire surface of the semiconductor substrate 1 including the tops of these n diffusion regions 2.3 is covered with a gate dielectric ff! Covered with J5. A gate bridge 4 is formed between the n diffusion regions 2 and 3 via the gate dielectric film 5.

Further, p
A silicon (alpha silicon) layer 10 is deposited. An n diffusion region 11 is provided inside the surface of this p silicon layer 10.
．． 12 is formed, and a gate electrode 14 made of polysilicon is formed on the p silicon layer 10 between the n-type failure regions 11 and 12 with a gate dielectric film 13 interposed therebetween.

Although not shown, the gate electrode 4 also has a write word line W.
A write bit line WBL is connected to the L and n diffusion regions 2, a read word line RWL is connected to the gate electrode 14, a read bit line RBL is connected to the n diffusion region f412, and a power supply (2) is connected to the n diffusion region 11. 0 is connected. Note that the write word line WWL is selectively activated by a row decoder or the like during writing, and the write bit line WBL is selectively connected to an input/output line (not shown) during writing. Read word line R
WL is selectively activated during reading, and is selectively connected to the above-mentioned input/output line via a current sensing type sense amplifier (not shown) during reading of read pit line RB L IcL. Note that the input/output lines are write data.

Transfers read data between the outside and memory cells.

FIG. 2 is an equivalent circuit diagram of FIG. 1. As shown in the figure, the gate electrode 4. The selection transistor Q1 is formed by the n-diffusion region IJi, 2.3, and the p-silicon layer 10, the n-diffusion region 3.3. The goo 1 to the dielectric film 5 under the p silicon layer 10 form a cell capacitor C2. Furthermore, the gate electrode 14 and the n-diffusion regions 11.12 form a memory transistor Q2.

In such a configuration, writing is performed by selectively setting the write word line WWi to "HI" by a row decoder (not shown) or the like.
I, turn on the transistor Q1, apply a voltage based on write data applied to the write bit line WBL via an input/output line (not shown) to the cell capacitor C2, and hold this voltage in the cell capacitor C2. .

At this time, the back gate potential vB6 of the memory transistor Q2 held in the cell capacitor C2 changes, and the threshold voltage of the memory transistor Q2 changes with the change in the back gate potential vB6. This memory transistor Q
Information is stored by changing the threshold voltage "th" of 2.

On the other hand, for reading, the read word line RWE is selectively set to H'.
', and read bit line R due to change in threshold voltage of memory transistor Q2 due to change in back gate potential BG.
This can be done by detecting changes in the current flowing through the BL with a current sense sensor.

The potential of the cell capacitor C2 that defines this back gate potential ■BG is independent of the capacitance value of the cell capacitor C2.
It becomes the potential of the write data.

FIG. 3 is a graph showing changes in back gate potential VBG and drain current r of memory transistor Q2.

The channel length of this memory transistor Q2 is 3. Ou+
+, drain voltage ■. is 5. OV.

Gate voltage v6 is 5. It is Ov.

As shown in the figure, the memory cell capacitor C2 is
Drain current of about 1.5 mA during writing (V8o=O, O) ■. flows, and when writing “1” (V86=-5,
0), a drain current of about 0.5771A flows through the drain current.

This difference in drain current of 1° can be sufficiently sensed by a normal current sensing type sense-up without complicating the circuit. Therefore, the noise margin and read time are not deteriorated.

In this way, the threshold voltage vth of the memory transistor Q2
Drain current I due to change. is the normal II HIT
, u L 11 level difference of about 5 V, which is the normal ? There is an effect of changing to a sufficiently detectable level by ti flow sense type sense up. Furthermore, since the back gate potential vBG has no relation to the capacitance value of the cell capacitor C2, there is no problem even if the capacitance value of the cell capacitor C2 becomes smaller due to higher integration.

In this embodiment, both transistors Ql and Q2 are of n-channel conductivity type, but may be set to p-channel conductivity type.

〔Effect of the invention〕

As explained above, according to the present invention, the back gate potential that changes the threshold voltage of the second MIS transistor that stores information is defined by the potential held in the cell capacitor. It is not affected by the capacitance value, does not require a highly sensitive sense amplifier due to the integration of the device, and does not deteriorate the noise margin.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a MIS type semiconductor memory device 1 memory layer which is an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is a memory transistor Q shown in FIG. 1.
2 back gate voltage ■BG and drain current■. 4 is a cross-sectional view showing one memory cell of a conventional MIS type semiconductor memory device, and FIG. 5 is an equivalent circuit diagram of FIG. 4. In the figure, Ql is a selection transistor, C2 is a memory transistor, C2 is a cell capacitor, WWl is a write word line, WBL is a bit line for every write, RWL is a read word line, and RBL is a read bit line. Note that the same reference numerals in each figure do not indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A data input line that takes in write data from the outside, a data output line that outputs read data to the outside, a write word line that is selectively activated during writing, and a data input line that selectively connects to the data input line when writing. a write bit line connected to the gate; a read word line that is selectively activated during reading; a read bit line that is selectively connected to the data output line via a current sensing type sense amplifier during continuous reading; and a gate. a first MIS type transistor having a gate connected to the write word line and a drain connected to the write bit line; and a second MIS type transistor having a gate connected to the read word line, a drain connected to a power supply, and a source connected to the read bit line. , the source of the first MIS type transistor, and the source of the second MIS transistor.
a cell capacitor interposed between the back gates of the second MIS transistor; the back gate potential of the second MIS transistor is defined by the potential held in the cell capacitor; A semiconductor memory device characterized in that information is stored by changing the threshold voltage of an MIS type transistor according to the value of the back gate potential.