JPH02312333A - Scrambler device and descrambler device - Google Patents

Abstract

PURPOSE:To secure proper data transmission by adding M-bit random data to N-bit parallel data to convert it to random data. CONSTITUTION:A scrambler device consists of an A/D converter 2, a parallel scrambler 3A, a P/S converter 4A, an electro/optical transducer 5, an optical transmission line 6, a random data generating circuit 19, and a frame synchronizing signal generating circuit 20. Though N-bit data related to input has parallel bit patterns equal to one another with respect to time series, bit patterns inputted to the parallel scrambler are changed by addition of M-bit random data, and as the result, scrambled data is different in individual frames. Thus, proper data transmission is secured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scrambler device and a descrambler device in an image transmission system.

[Conventional technology]

In the transmission of digital data, randomization of transmitted data,
That is, scrambling is performed.

A third image transmission system that performs such scrambling
As shown in the figure. In this system, an analog image signal arrives at the A/Di converter 2 via a signal fill, is digitized, and is output as N-bit parallel data. This parallel data is randomized by a parallel scrambler 3 and sent to a P/S converter 4. P
The /S converter 4 converts the parallel data and a frame synchronization signal provided via the signal line 13 and having a predetermined bit pattern into serial data having a frame format as shown in FIG. It is sent to the optical converter 5. In FIG. 4, F represents a frame synchronization signal, and I represents an image signal field consisting of N bits. The electrical/optical converter 5 converts the serial image signal into an optical signal and sends it to the optical transmission line 6. The image signal transmitted through the optical transmission line 6 reaches the optical/electrical converter 7 on the receiving side, is converted into an electrical signal, and is sent to the synchronization detection circuit 8 and the S/P converter 9. The synchronization detection circuit 8 detects a frame synchronization signal F from data in the frame format shown in FIG. 4, and supplies the S/P converter 9 with a synchronization signal indicating the division of one frame. Based on the Domei signal, the S/Pa converter 9 sends one frame of N-bit image signals as a parallel signal to the parallel descrambler 10, while sending out a frame synchronization signal F from the signal line 14. The parallel scrambler 10 performs a conversion process opposite to that on the transmitting side to return the data from the randomized state to the original state, and sends this N-bit parallel data to the D/A converter 11. The D/A converter converts the digital signal into an analog signal and sends it as serial data to a monitor device (not shown) via a signal line 12.

By the way, the parallel scrambler 3 used on the transmitting side is designed to change the scrambled data in chronological order if the incoming parallel data does not change over time (if the same bit pattern arrives). However, the scrambled data is usually randomized but has the same bit pattern over time (this type of method is called fixed mode).

On the other hand, as the optical/electrical converter 7, one of an AC coupling type is used. Such an optical/electrical converter has a mark rate of an input digital signal (ratio of the period of "1" in the total period of the mark period in which the digital signal is "1" and the space period in which the digital signal is "0"). If it deviates from 50%, reception sensitivity deteriorates. More specifically, it is known that the reception sensitivity of an optical/electrical converter depends on the long-term average of the mark rate, and the time width of this long-term average is the time constant of the optical/electrical conversion. (responsiveness). This time width is normally an order of magnitude longer than the transmission time (period) of one frame of data to be transmitted.

[Problem to be solved by the invention]

Therefore, when the parallel scrambler is of a fixed mode and the optical/electric converter is of an AC coupling type, the image signal has the same bit pattern every N bits and the mark rate is long. time! If the bit pattern is such that the μ average deviates from 50%, there is a problem in that the reception f/2 sensitivity deteriorates, resulting in adverse effects such as noise in reproduced images.

Therefore, the present invention fixes the output to a predetermined bit pattern as long as the same bit pattern arrives by the scrambler, and when serial digital data is received and optical/electrical conversion is performed, the mark ratio in the data is It is an object of the present invention to provide a scrambler device and a descrambler device that can ensure proper data transmission even when using an optical/electrical converter whose reception sensitivity deteriorates when the time average deviates from 50%.

[Means to solve the problem]

A scrambler device according to the present invention includes a parallel scrambler that randomizes N+M bits of parallel digital data, and a random data generation circuit that generates M bits of randomized data and supplies it to a predetermined input bit terminal of the parallel scrambler. and the incoming data is N
It is characterized in that each bit is converted into parallel data and applied to an input terminal other than a predetermined input bit terminal of the parallel scrambler.

Further, the descrambler device according to the present invention includes an S/P converter that receives serial digital data sent and converts it into parallel data every N+M bits, and
The present invention is characterized in that it includes a parallel descrambler that descrambles the output signal of the P converter, and extracts a predetermined N bits from the output signal of the parallel descrambler and uses them for original signal reproduction.

[Effect]

Since the scraping device according to the present invention is configured as described above, even if the N-bit data related to the input has the same parallel bit pattern in time series, the randomized N-bit data , the bit pattern entering the parallel scrambler changes, and eventually,
The scrambled data becomes data that changes every frame.

Further, since the descrambler device according to the present invention is configured as described above, it first descrambles the N+N bit data sent from the transmitting side, returns it to the N+M bit data before being scrambled, and this house,
Since the original signal is reproduced by extracting the N-bit data excluding the N-bit data added so that the mark rate is 50%, it is possible to guarantee the transmission of different bit patterns over time on the transmitting side.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A scrambler device and a descrambler device according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2 of the accompanying drawings. In the description of the drawings, the same elements are given the same reference numerals and redundant description will be omitted.

FIG. 1 shows an image transmission system. In this embodiment, the parallel scrambler 3A is for input/output of N+1 bits, the N bit data is output from the A/D converter 2, and the remaining 1 bit is transmitted through the signal line 17. The data is obtained from the random data generation circuit 19 via the random data generating circuit 19. Here, the random data generation circuit 19 generates 1, 0, 1, . . . in synchronization with the data acquisition timing of the parallel scrambler 3A. Data consisting of alternating signals O, . . . is generated and applied to the parallel scrambler 3A via the signal line 17. The frame synchronization signal generation circuit 20 generates a frame synchronization signal with a predetermined bit pattern, and sends it to the P/S converter 4A via the signal line 13 at the data acquisition timing of the P/S converter 4A. In addition,
The signal line 17 is applied to a predetermined (appropriate bit, not limited to the most significant or least significant bit) input bit terminal of the parallel scrambler 3A.

As a result of the transmission side being configured in this way, even if the output signal of the A/D converter 2 has the same parallel data pattern in time series, the N+1 bit data given to the parallel scrambler 3A is parallel data. will be different for each acquisition, the scrambled data will be randomized, and the mark rate will approach 50%. The output signal of the scrambler 3A is converted into serial data by the P/S converter 4A, and a frame synchronization signal F is added to the information field I consisting of N+1 bits as shown in FIG. The data is converted into one frame of data, converted into an optical signal, and sent out.

On the receiving side, an S/p6 converter D9A and a parallel descrambler 10A are used to descramble the scrambled data with the addition of 1-bit data as described above and return it to the original signal. When the synchronization detection circuit 8 detects the frame synchronization signal F and sends a synchronization signal indicating the delimitation of one frame to the S/P converter 9A,
At this time, one frame of data is prepared in the S/P converter 9A, of which N+1 bits of information field 1 are sent to the parallel disk clamp IOA, and a frame synchronization signal F of predetermined bits is sent out from the signal line 14. The parallel descrambler IOA descrambles the given N+1 bit data and converts it into an N-pit image signal.
The 1-bit data added by the data generation circuit 19 is output. Among these, the N-bit image signal is D/
The 1-bit data sent to the A converter 11 and added by the data generation circuit 19 is separated by the signal line 21. The N-bit image signal supplied to the D/A converter 11 is converted into an analog signal, and the original image signal is reproduced.

The configuration of the present invention is not limited to the above, and various modifications are possible.

For example, the data added to the data to be transmitted is not limited to one bit, but may be any two or more bits.

Additionally, the data of the bits to be added changes over time to 1.0°1.
0. . . . In addition to the alternating signal that changes as follows, a pseudo-randomized signal or the like may be used. That is, if the data to be added is data that changes in a short period with respect to the time constant of the optical/7jS air converter 7, the mark rate of the scrambled data will approach 50%.

〔Effect of the invention〕

As explained in detail above, according to the present invention, since M-bit randomized data is added to N-bit parallel data for randomization, incoming N-bit parallel data is the same data in time series. Even in this case, the output data will be different in chronological order, and appropriate data transmission can be guaranteed.

Further, according to the present invention, after descrambling on the receiving side, N0 M bits are added on the transmitting side.
To remove the bit-randomized data, the original IJ code on the sending side can be regenerated to ensure proper data transmission.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a transmission system using a scrambler device and a descrambler device according to an embodiment of the present invention,
Fig. 2 is a diagram showing the frame format of data transmitted by a transmission system using the device of the present invention, Fig. 3 is a block diagram of a transmission system using a conventional scrambler device and a descrambler device, and Fig. 4 1 is a diagram showing a frame format of transmission data used in a conventional transmission system. 2A... A/D converter, 3A... Parallel scrambler, 4A... P/S converter, 5... Electric/optical converter, 6... Optical transmission line, 7... Optical/electrical converter, 8.
...Synchronization detection circuit, 9A...S/P converter, IOA
...Parallel descrambler, 11...D/A converter, 19...Random data generation circuit, 20...Frame synchronization signal generation circuit.

Claims (1)

[Claims] 1. A parallel scrambler that randomizes N+M-bit parallel digital data, and a random data generator that generates M-bit randomized data and supplies it to a predetermined input bit terminal of the parallel scrambler. What is claimed is: 1. A scrambler device comprising: a circuit for parallel converting incoming data every N bits and applying the parallel scrambler to an input terminal other than the predetermined input bit terminal of the parallel scrambler. 2. Equipped with an S/P converter that receives incoming serial digital data and converts it into parallel data of every N+M bits, and a parallel descrambler that descrambles the output signal of this S/P converter, From the output signal of this parallel descrambler, a predetermined N
A descrambler device characterized by extracting bits and using them for original signal reproduction.