JPH02312278A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02312278A JPH02312278A JP13395789A JP13395789A JPH02312278A JP H02312278 A JPH02312278 A JP H02312278A JP 13395789 A JP13395789 A JP 13395789A JP 13395789 A JP13395789 A JP 13395789A JP H02312278 A JPH02312278 A JP H02312278A
- Authority
- JP
- Japan
- Prior art keywords
- source
- grooves
- semiconductor device
- groove
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 230000015654 memory Effects 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000000059 patterning Methods 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、半導体装置の製造方法に関し、特に高集積化
のための技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technique for increasing integration.
〈従来の技術〉
メモリなどの半導体装置を製造する方法において、集積
度を高めるために、先ずソース・ドレイン領域を複数個
平行に形成し、これと直交するようにゲート電極を複数
個形成することにより、トランジスタを格子状に配列す
る方法がとられている。第2図はこの方法により作成さ
れた半導体装置の断面構造を示しており、第3図はその
A−A’断面構造を示している。St基Fi+に複数本
のソース・ドレイン領域4が平行に形成され、表面にゲ
ート酸化膜5が形成され、その上に複数本の平行なゲー
ト電極6がソース・トレイン領域4と直交する方向に形
成されている。<Prior art> In a method of manufacturing semiconductor devices such as memories, in order to increase the degree of integration, first a plurality of source/drain regions are formed in parallel, and a plurality of gate electrodes are formed perpendicularly to the source/drain regions. Therefore, a method has been adopted in which transistors are arranged in a grid pattern. FIG. 2 shows a cross-sectional structure of a semiconductor device manufactured by this method, and FIG. 3 shows its A-A' cross-sectional structure. A plurality of source/drain regions 4 are formed in parallel on the St-based Fi+, a gate oxide film 5 is formed on the surface, and a plurality of parallel gate electrodes 6 are formed thereon in a direction perpendicular to the source/train regions 4. It is formed.
〈発明が解決しようとする課題〉
半導体装置を高集積化するためのL記従来の方法では、
パターンの微細化はフォトの解像度とトランジスタの能
力で制限され、フォトの解像限界を越えて微細化するこ
とは不可能であった。<Problem to be solved by the invention> In the conventional method of increasing the integration of semiconductor devices,
The miniaturization of patterns is limited by the resolution of the photo and the ability of the transistor, and it has been impossible to miniaturize the pattern beyond the resolution limit of the photo.
く課題を解決するための手段〉
L記課題を解決するために、本発明による半導体装置の
製造方法においては、半導体基板に複数本の溝を形成し
、溝の側面に保護膜を形成し、溝と溝との間および溝の
底部にソース・ドレイン領域を形成し、ソース・ドレイ
ン領域の上にゲート酸化膜を形成し、溝と直交するよう
にゲート酸化膜の上にゲート電極を形成することを特徴
とじている。Means for Solving the Problems> In order to solve the problem L, in the method for manufacturing a semiconductor device according to the present invention, a plurality of grooves are formed in a semiconductor substrate, a protective film is formed on the side surface of the grooves, Source/drain regions are formed between the trenches and at the bottom of the trenches, a gate oxide film is formed on the source/drain regions, and a gate electrode is formed on the gate oxide film so as to be orthogonal to the trenches. It is characterized by
〈作用〉
本発明による半導体装置の製造方法においては、半導体
基板の表面に平行に複数個の溝を形成し、その後、溝の
側面に保護膜を形成した上で、自己整合的に溝と溝との
間および溝の底部にソース・ドレイン領域を形成し、こ
れと直交するようにゲート電極を複数個形成することに
より、溝の側壁をゲート領域とし、立体的にトランジス
タを配置することによって、フォトの解像度を上げる必
要なく、また、トランジスタの能力を低下させることな
く、高集積化を可能とする。<Operation> In the method for manufacturing a semiconductor device according to the present invention, a plurality of grooves are formed in parallel on the surface of a semiconductor substrate, and then a protective film is formed on the side surfaces of the grooves, and then the grooves are formed in a self-aligned manner. By forming a source/drain region between the source and drain regions and at the bottom of the trench, and by forming a plurality of gate electrodes perpendicular to the gate electrode, the side wall of the trench is used as a gate region, and transistors are arranged three-dimensionally. High integration is possible without increasing photo resolution or reducing transistor performance.
〈実施例〉
第1図は本発明の製造方法の各段階の断面構造を示して
いる。図において、1はシリコン基板、2はウェル、3
はSiO□膜、4はソース・ドレイン領域、5はゲート
酸化膜、6はゲート電極、7はフォトレジスI・、8は
溝である。<Example> FIG. 1 shows a cross-sectional structure at each stage of the manufacturing method of the present invention. In the figure, 1 is a silicon substrate, 2 is a well, and 3 is a silicon substrate.
4 is a SiO□ film, 4 is a source/drain region, 5 is a gate oxide film, 6 is a gate electrode, 7 is a photoresist I·, and 8 is a groove.
(alでは、Si基板1上に深さ1.5μm以上でウェ
ル2を形成した後、0.5〜1.0μmの間隔で幅及び
深さが約1.0μmの溝8を形成する。(For Al, after forming a well 2 to a depth of 1.5 μm or more on a Si substrate 1, grooves 8 having a width and depth of about 1.0 μm are formed at intervals of 0.5 to 1.0 μm.
(b)では、化学気相成長法及び異方性エツチング技術
を用いて溝8の側面8aに5iozJI夕3を形成する
。このSiO□膜3は、後工程のイオン注入に対する保
護膜を形成する。In (b), 5iozJI layer 3 is formed on the side surface 8a of the groove 8 using chemical vapor deposition and anisotropic etching. This SiO□ film 3 forms a protective film against ion implantation in a later process.
(C1では、S + 02膜3で覆われていない溝8と
溝8との間および溝8の底部にイオン注入によりソース
・ドレイン領域4を形成し、溝8の側壁8aからSin
、膜3を除去した後、高温酸素雰囲気中でゲート酸化膜
5を形成する。(In C1, the source/drain regions 4 are formed by ion implantation between the trenches 8 not covered with the S + 02 film 3 and at the bottom of the trenches 8, and the
After removing the film 3, a gate oxide film 5 is formed in a high temperature oxygen atmosphere.
(dlでは、ゲート酸化膜5の上にa8と直交する方向
にゲート電極6をフォトリソグラフィ及びエツチング技
術を用いてパターン化形成する。(elはこの(dlの
段階における[3−13’断面構造を示している。(In dl, the gate electrode 6 is patterned and formed on the gate oxide film 5 in the direction perpendicular to a8 using photolithography and etching techniques. (el is the [3-13' cross-sectional structure at the stage of (dl) It shows.
以上の工程によりメモリセルアレイが完成する。A memory cell array is completed through the above steps.
その後、このメモリセルアレイに情報を書き込むときに
は、ff)に示すように、表面にフォトレジストアを形
成し、対象とするトランジスタの上のフォトレジスト7
をフォトリソグラフィ技術によって開口した後、イオン
注入する。After that, when writing information to this memory cell array, as shown in ff), a photoresist is formed on the surface, and a photoresist 7 is formed on the target transistor.
After forming an opening using photolithography, ions are implanted.
〈発明の効果〉
以上説明したように本発明においては、溝を利用するこ
とによってソース・ドレイン領域を自己整合的に形成す
ることができ、トランジスタを立体的に配置することに
より、フォトリソグラフィの解像限界に制限されず、ま
たトランジスタの能力を低下させることなく、容易に高
集積化を実現することができる。<Effects of the Invention> As explained above, in the present invention, source/drain regions can be formed in a self-aligned manner by using grooves, and photolithography solutions can be improved by arranging transistors three-dimensionally. High integration can be easily achieved without being limited by image limits or reducing transistor performance.
第1図は本発明実施例の断面構造を示す図、第2図と第
3図は従来例の断面構造を示す図である。
1・・・Si基板
2・・・ウェル
3・・・5iOz膜
4・・・ソース・ドレイン領域
5・・・ゲート酸化膜
6・・・ゲート電極
7・・・フォトレジスト
8・・・溝FIG. 1 is a diagram showing a cross-sectional structure of an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing a cross-sectional structure of a conventional example. 1...Si substrate 2...well 3...5iOz film 4...source/drain region 5...gate oxide film 6...gate electrode 7...photoresist 8...groove
Claims (1)
形成し、溝と溝との間および溝の底部にソース・ドレイ
ン領域を形成し、ソース・ドレイン領域の上にゲート酸
化膜を形成し、溝と直交するようにゲート酸化膜の上に
ゲート電極を形成することを特徴とする半導体装置の製
造方法。A plurality of trenches are formed in a semiconductor substrate, a protective film is formed on the side surfaces of the trenches, source/drain regions are formed between the trenches and at the bottom of the trenches, and a gate oxide film is formed on the source/drain regions. A method of manufacturing a semiconductor device, comprising forming a gate electrode on a gate oxide film so as to be perpendicular to the groove.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13395789A JP2708878B2 (en) | 1989-05-26 | 1989-05-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13395789A JP2708878B2 (en) | 1989-05-26 | 1989-05-26 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02312278A true JPH02312278A (en) | 1990-12-27 |
JP2708878B2 JP2708878B2 (en) | 1998-02-04 |
Family
ID=15117032
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13395789A Expired - Fee Related JP2708878B2 (en) | 1989-05-26 | 1989-05-26 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2708878B2 (en) |
-
1989
- 1989-05-26 JP JP13395789A patent/JP2708878B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2708878B2 (en) | 1998-02-04 |
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