JPH02310962A - Three dimensional memory element - Google Patents

Abstract

PURPOSE:To enlarge capacity of a section for charge storage and to enable increase of memory capacity by constituting the charge storage section by a diffusion layer formed along a surface of a groove provided on a semiconductor substrate surface, an insulating film covering a groove surface on the diffusion layer, and a conductive polycrystalline body deposited to fill up the groove on the insulating film. CONSTITUTION:A charge storage section 14 is provided with an N-type diffusion layer 21 on a surface region of a groove shaped on a surface of a silicon substrate 13. An oxide film 22 is formed on a surface of the N-type diffusion layer 21. A polycrystalline silicon layer 23 is formed in a fixed thickness on the oxide film 22. A silicon oxide film (SiO2) 24 is formed to fill up a groove on the polycrystalline silicon layer 23. An occupation area of the charge storage section is made small and a surface area of a charge storage region is enlarged; accordingly, it is possible to hold charge sufficiently large compared with a tunnel switch section even with a small occupation area, thereby realizing high integration and increase of memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] “The present invention relates to a three-dimensional memory device applicable as a memory integrated circuit.

[Conventional technology]

2. Description of the Related Art Conventionally, memory elements have been considered that utilize the voltage history phenomenon of a nonlinear conductivity element having an MIM structure in which metal (M), insulator (1), and metal (M) are laminated in this order.

FIG. 12 is a diagram showing the configuration of this type of memory element.

This memory element connects a nonlinear conductivity element 1 having an MIM structure and a charge storage part C8, applies a write voltage Vln to the nonlinear conductivity element 1, stores charges in the charge storage part C8, and stores information. At the same time as storing, the read voltage V o
The structure is such that the charges stored in the charge storage section CS can be read out by applying ut. Note that FIG. 13 shows the voltage history characteristics of the nonlinear conductivity element 1 shown in FIG. 12. Here, since the nonlinear conductivity element 1 exhibits such a voltage history characteristic by tunneling charge, the nonlinear conductivity element 1 will be referred to as a "tunnel switch section" hereinafter.

Next, the memory phenomenon will be explained with reference to FIG. When the voltage Vp is applied to the terminal 2 with the peak value Vp of the rectangular wave AC voltage applied to the terminal 2 being higher than the rising voltage vth of the tunnel switch section 1, the tunnel switch section 1 enters a high conductivity state. Therefore, current flows into the charge storage section C3, and V out, which is the voltage across the charge storage section CS, increases. Thereafter, when the applied voltage V1n is lowered, the tunnel switch section 1 is initially in a high conductivity state, so the charge in the charge storage section C5 flows out and Vout decreases. enters a low conductivity state, and the flow of charge stops. Even if Vln becomes O, V out maintains Vm. Also, Vln is −Vp
Similarly to the above, even if Vln becomes 0, V
ouL will hold -Vl.

By the way, similar to general memories, in response to demands for increased memory capacity and higher integration, many of the above-mentioned memory elements are fabricated two-dimensionally on a semiconductor substrate as memory cells. It is being said.

Furthermore, recently, three-dimensional structure in which memory cells are stacked is being considered as one means of achieving high integration.

However, in conventional 3D memory, the number of stacked layers that can withstand practical use is limited to about 3 layers, and the degree of planar integration is also lower than that of a single layer, and as a result, the effect of 3Dization is not so much. The reality was that it was not.

[Problem to be solved by the invention]

By the way, the present inventors have developed a memory element in which memory cells can be stacked in three dimensions, and have filed a patent application No. 63-21416.
It has already been applied for as No. 9 etc. The memory devices shown in these applications include, as an insulator in a MIM structure,
Three-dimensionality is achieved by using a monomolecular film such as a Langmuir-Project film (hereinafter referred to as rLB film). Such a three-dimensional memory element has memory cells that have an MIM structure and consist of a tunnel switch section that tunnels charge and a charge storage section that are arranged three-dimensionally in the vertical, horizontal, and depth directions, and each memory cell is arranged three-dimensionally in the vertical, horizontal and depth directions. The cell is configured to include a voltage application circuit for charge transfer, as well as a write circuit and a read circuit.

In the three-dimensional memory element configured as described above, a predetermined write pulse is applied from the write circuit, and a transfer pulse is applied from the charge transfer circuit via the charge storage section to tunnel the charge to each memory. Write information to the charge storage section of the cell. Then, by applying a read pulse from the read circuit, the information stored in the charge storage section is read out, for example, as a current.

However, in such a three-dimensional memory element, the capacity of the charge storage section directly determines the memory capacity, so a charge storage section with as large a capacity as possible is desired. A conceivable way to increase the capacity of the charge storage section is to reduce the thickness of the insulator and increase the area of the conductive layer sandwiching the insulator.

However, due to the demand for higher integration, severe restrictions are imposed on the area occupied by the charge storage section, so it has been difficult to increase the area larger than the current size.

Furthermore, since the transfer pulse is applied to the tunnel switch section via the charge storage section, if the capacitance of the tunnel switch section is smaller than the capacitance of the charge storage section, the predetermined voltage will not be applied to the tunnel switch section 1. There is a problem in that charge cannot be transferred sufficiently. Furthermore, if the amount of charge accumulated in the charge storage section is small, there is a problem that reading cannot be performed with a good S/N ratio.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a three-dimensional memory element that can increase the capacity of a charge storage section while occupying a small area, thereby increasing the memory capacity.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a tunnel switch section in which conductive layers are arranged opposite to each other with an insulating film interposed therebetween and charges are tunnel-transmitted through the insulating film, and a charge electrically connected to the tunnel switch section. In a three-dimensional memory element in which a memory cell is constituted by a storage part and a plurality of these memory cells are stacked on a substrate, the charge storage part is formed by diffusion formed along the surface of a groove provided on the surface of the semiconductor substrate. layer and
It consisted of an insulating film formed to cover the surface of the groove in which the diffusion layer was formed, and a conductive polycrystalline body deposited on the insulating film so as to fill the groove.

Further, the charge storage section may include a first insulating film formed to cover a surface of a groove provided on a surface of a semiconductor substrate;
a first conductive polycrystalline body deposited to a predetermined thickness on an insulating film; a second insulating film formed to cover the surface of this first conductive polycrystalline body; A second conductive polycrystalline body was deposited on the second insulating film so as to fill the groove.

The charge storage section may be formed of a first insulating film formed on a semiconductor substrate, a first conductive polycrystalline body having a large surface area formed on this ml insulating film, and this first insulating film formed on the semiconductor substrate. 1
It consisted of an insulating film of m2 formed to cover the surface of the conductive polycrystalline body, and a second conductive polycrystalline body deposited to cover the second insulating film.

Further, the charge storage section has a structure in which an insulating film made of Ta2O5 is sandwiched between conductive layers.

[Effect]

By taking the above measures, the following effects are achieved.

In other words, since the charge storage section is a trench-type capacitor, the area of the capacitor can be increased without increasing the exclusive area of the charge storage section, and a large amount of charge can be stored. Since the bonding surface between the insulator and the insulator is shaped to have a large surface area, the capacitance can be increased without increasing the occupied area.
Since the insulating film made of 2O5 is sandwiched between conductive layers, the capacity of the charge storage section can be increased as described above.
Memory capacity can be increased.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a three-dimensional memory element according to a first embodiment. This three-dimensional memory element includes a MOS type write switch 11 operated by a write column designation circuit (not shown), a charge transfer path 12 in which a plurality of tunnel switch sections for tunneling charge are stacked, and a charge transfer path 12 for each tunnel switch section. Trench-type charge storage sections 14a to 14d are correspondingly formed in the silicon substrate 13, and a charge transfer address line is connected at one end to each charge storage section 14 and at the other end to a level mix circuit (not shown). 15a-15
d, and a MOS readout switch 16 connected to a readout shift register (not shown) and used to read charges from the charge storage section 14d. In addition,
In reality, a plurality of such configurations are provided in a two-dimensional direction. Further, in this embodiment, for convenience, the tunnel switch section is shown as having three layers stacked, but if an LB film is used, even three or more layers can be stacked on the container.

The tunnel switch section forming the charge transfer path 12 has an MIM structure in which LB films are alternately laminated as insulators. Note that by applying the LBBi12 voltage, it becomes a tunnel junction surface that tunnels charges. A conductive layer 12a, which is the uppermost layer of the charge transfer path 12, is connected to the write switch 11 and also to the charge storage section 14a. One electrode of the charge storage section 14a is connected to the conductive layer 12a, and the other electrode is connected to the charge transfer address line 15a. The charge storage section 14b has one electrode connected to the charge transfer address line 15.
b, and the other electrode is connected to M along with the conductive layer 12a.
It is connected to the other conductive layer 12b forming the IM structure. Similarly, the charge storage section 14c has one electrode connected to the charge transfer address line 15c and the other electrode connected to the conductive layer IC. One electrode of the charge storage section 14d is connected to the charge transfer address line 15d, and the other electrode is connected to the conductive layer 12c, one of the conductive layers of the uppermost tunnel switch section, and the readout switch 16. Further, an interlayer insulating film 18 is formed between each of the conductive layers 12a to 12c, and a surface protection film 19 is formed on the uppermost conductive layer 12a.

In the charge storage section 14, an N-type diffusion layer 21 is formed in the surface region of a groove dug in the surface of the silicon substrate 13, and an oxide film 22 is formed on the surface of this N-type diffusion layer 21.

Furthermore, a polycrystalline silicon layer 23 is formed to a certain thickness on the oxide film 22, and on the polycrystalline silicon layer 23,
A silicon oxide film (Si02) 24 is formed to fill the trench. N-type diffusion layer 21 and silicon oxide film 24
An AI main electrode is formed in a part of the polycrystalline silicon layer 23 that is drawn out further outside the groove.

Next, a method for manufacturing the three-dimensional memory element configured as described above will be described.

First, the charge storage section 14 is fabricated on the silicon substrate 13 by a method described later, and peripheral circuits such as a write column designation circuit, a level mix circuit, a signal transfer shift register, and a read shift register are provided.

Next, the silicon substrate 13 in which the charge storage section 14 is formed
The surface is planarized, a through hole is formed at a position opposite to the portion where the A11 electrode of each charge storage section 14 and one electrode of the write switch 11 are formed, and a metal conductor is formed to conduct to the polycrystalline silicon layer 23. Pads 25a to 25e are provided. Then, sputtering method that can form a film at low temperature or E
An interlayer insulating film 18 for the purpose of reducing parasitic capacitance and interlayer insulation is deposited by CR plasma method, and a through hole is formed in a region where a tunnel switch portion is to be formed.

Next, an LB film is attached to the entire surface of the substrate and selectively removed so that the LBBi 12 remains at least in the area where the tunnel switch portion is to be formed. Furthermore, a metal film that will become the conductive layer 12c is deposited and patterned to form a tunnel junction surface that becomes an MIM structure in the tunnel switch section, and connects this tunnel switch section and the charge storage section 14d. Furthermore, metal pads 25cc to 25ee are formed on the other metal pads 25c to 25e for conducting electrical connection with each metal pad and aligning the surface positions. After that, similar operations are repeated one after another until the tunnel switch section is laminated.
The structure is such that a charge storage section 14 is electrically connected to each tunnel switch section.

In addition, when manufacturing the charge storage section 14, a silicon oxide film (Si
02) Silicon nitride film (S
After forming a pattern by photolithography, a thick oxide film 33 is formed by selective oxidation (as shown in FIG. 2(a)).

Next, after removing the silicon nitride film 32, a PSG film 34 is deposited to a thickness of about 1 μm using the CVD method. Then, the PSG in the region where the groove is to be formed on the silicon substrate 13 is
The film 34 and the thin oxide film 31 are removed (see FIG. 2(b)
).

Next, using the PSG film 34 as a mask, the silicon substrate 13 is subjected to reactive ion etching (RIF) to form the grooves 35.
form. Thereafter, the PSG film 34 is removed, and As'' is formed using the thick oxide film 33 as a mask.

An N-type impurity such as sb+ is ion-implanted to form an N-type diffusion layer 36 doped with the N-type impurity on the surface of the trench 35 and directly under the thin oxide film 31a (as shown in FIG. 2(c)).

Next, after removing the thin oxide film 31a formed on the surface of the silicon substrate 13, the surface of the diffusion layer 36 is oxidized again to form a thin insulating film 37. Then, a polycrystalline silicon layer 38 is deposited to a predetermined thickness on the thin insulating film 37, and a silicon oxide layer (Si02) 39 is further formed on the polycrystalline silicon layer 38 by CVD to fill the grooves. (Illustrated in FIG. 2(d)).

Next, the silicon oxide layer 39 is etched back over the entire surface, leaving only the groove portion (as shown in FIG. 2(e)).

Then, the opening region of the trench is masked with photoresist 40 so that a portion of the polycrystalline silicon layer 38 is drawn out from the trench, and the polycrystalline silicon layer 38 is etched with reactive ions.
A polycrystalline electrode pattern 38a is formed (as shown in FIG. 2(f)).

The operation of the three-dimensional memory element configured in this way will be explained with reference to FIG. 3. FIG. 3 is a diagram showing the structure of an equivalent circuit of the three-dimensional memory element shown in FIG. 1, and shows a case where the charge transfer paths 12 are arranged in three rows in the two-dimensional direction. Note that TW1 to TW3 in the figure are tunnel switch sections, and each tunnel switch section TW and each charge storage section 14 connected thereto constitute a memory cell.

Note that the tunnel switch section TW has a tunnel conduction mechanism whose conductance G Tao exp (-t/V) is variable with respect to the applied voltage.

This three-dimensional memory element applies a write pulse VW from the write column specifying circuit 51 at the timing shown in FIG. A transfer pulse VT is applied from the mix circuit 53 at the timing shown in FIG. 4(b) to transfer the charges accumulated in the charge accumulation section 14a to the charge accumulation sections 14b and 14c. Then, the read pulse VR is transmitted from the read shift register 54 to the charge storage units 14d and 14e at the timing shown in FIG. 4(C).
14f to read the stored information.

For example, when writing information "1" to the memory cell in the first row and first column, the sl side of the write switch 11 is turned on, a negative voltage ■ is applied to one electrode of the charge storage section 14a, and the other electrode is A voltage VTI (high level) is applied to the electrode of the charge storage section 14a.In other words, a voltage of VTI-V is applied to the charge storage section 14a, and as a result, the charge storage section 14a1.
The charge of TI-V)/co is accumulated, and information "1" is written. Note that co is the capacitance of the charge storage section 14g. In addition, when writing information "0"-, the write switch S2 is turned on, a positive voltage V is applied, and VTI is set to high level, so that a voltage of (VTI-V) to 0 is applied to both ends of the charge storage section 14a. is applied to the charge storage section 14a.
Eliminate the accumulation of charge in the memory and write information "0".

Next, the charge accumulated in the memory cell in the 1st row and 1st column is 1
When transferring to the memory cell in the second row and column, the transfer pulse V
TI is set to high level, and transfer pulse vT2 is set to low level. Then, a level voltage of (H+L) is applied to the tunnel switch section TWI in the first row and first column, and the tunnel switch section TWI is turned on (conductive state). Therefore, the charges accumulated in the charge accumulation section 14a are:
It is transferred to the charge storage section 14b. Next, charge storage section 14b
When transferring the charges stored in the charge storage section 14c to the next stage charge storage section 14c, vT2 is set to high level and vT3 is set to low level. Note that at this time, a negative voltage pulse slightly lower than the low level is applied to the VTI for the purpose of clearing the charge remaining after transfer and preventing the charge from returning.

In addition, as shown in FIG. 4(b), VA is VTl, VT4,
VB indicates VT2, and VC indicates VT3.

Reading is performed by applying a low-level transfer pulse VT4 to the memory cell in the last column, turning on the read switch 16 from the read shift register 54, and measuring the current flowing through the load resistor RL. Charge storage section 14
Since the current flowing through the load resistor RL differs depending on the amount of charge accumulated in d, the amount of current flowing is
Os can be determined.

According to the first embodiment, since the tunnel switch section is formed using LBBi12, memory cells can be easily fabricated in a three-dimensional direction, dramatically improving memory capacity and integration. be able to. In addition, since the charge storage section 14 is a trench-type capacitor, the surface area of the charge storage region can be expanded even though it occupies a small area (flat area on the chip), and the memory capacity can be increased to about 10 times that of a conventional tunnel junction capacitor. can be increased to

Therefore, it is possible to reduce the chip area when constructing a high-density three-dimensional memory element.

Moreover, since the capacity of the charge storage section 14 can be increased, the stored charges can be read out with a good S/N ratio.

Furthermore, since the charge storage section 14 can be manufactured using a silicon process, the manufacturing process of the charge storage section 14 can be changed to the write switch 1.
1. It can be included in the manufacturing process of peripheral circuits such as the read switch 16, and the manufacturing process of the memory element can be simplified. Also, the charge storage section 14 is used for memory access and write switch/edge 11. It can be formed on the same chip as peripheral circuits such as the read switch 16.

An example in which the charge storage section 14 shown in the first embodiment is improved will be described below.

As a modification of the charge storage section shown in the first embodiment, the charge storage section has a configuration shown in FIG. 5(a).

The charge storage section shown in this modification is a trench-type capacitor, and an N-type diffusion layer 36 is formed on the surface of a groove dug in the surface of the P-type silicon substrate 13.

The surface of the N-type diffusion layer 36 is coated with an insulating film 37, and N+ doped polycrystalline silicon 61 is further deposited to fill the groove. And N type diffusion layer 3
6 and polycrystalline silicon 61 are provided with terminals 62 and 63.

Next, a method for manufacturing the charge storage section configured as described above will be described.

The process up to forming the diffusion layer 36 on the surface of the groove dug in the silicon substrate 13 is shown in FIG. 2 (a) explained in the first embodiment.
) to FIG. 2(C).

Next, the thin oxide film 31a is removed, and the thin oxide film 37 for forming a capacitance is formed by annealing and thermal oxidation of the N-type diffusion layer 36.
grow. Then, N+ doped polycrystalline silicon 61 is deposited by low pressure CVD method, and this polycrystalline silicon 61
The groove 35 is filled with (as shown in FIG. 5(b)).

Next, the polycrystalline silicon 61 is etched back over the entire surface of the wafer, leaving the polycrystalline silicon 61 only in the grooves 35 (as shown in FIG. 5(c)).

After that, terminals 63 and 62 are provided on the N-type diffusion layer 36 and the polycrystalline silicon 61, and the manufacturing process of the charge storage section is completed.

Next, another modification of the charge storage section shown in the first embodiment will be described. The charge storage section shown in this modification example is shown in FIG.
), conductive polycrystalline silicon 6 is stacked in two layers and buried in a groove formed in a silicon substrate 13.
5.66 and the insulating film 67 formed between both polycrystalline silicon 65.66 constitutes a capacitor.

When producing the charge storage section configured in this way, first, a groove is formed on the surface of the silicon substrate 13, and after forming an insulating film 71 on the surface of the groove for insulation, the first polycrystalline silicon 65 is deposited, and its surface is further thermally oxidized to form a thin oxide film 72 (as shown in FIG. 6(b)).

Next, a second polycrystalline silicon 66 is deposited on the oxide film 72 to fill the trench (as shown in FIG. 6(c)).

Next, the second polycrystalline silicon 66 is etched using a photoresist mask 73 to form one electrode pattern 66a of the charge storage section (as shown in FIG. 6(d)).

Then, a photoresist 74 is additionally applied to form an oxide film 67.
Then, a part of the first polycrystalline silicon 65 is etched to form the other electrode pattern 65a (as shown in FIG. 6(e)).

In this way, the trench-type charge storage section shown in FIG. 6(a) can be manufactured.

Next, a second embodiment of the present invention will be described.

This embodiment is an example in which the charge storage section is a stacked capacitor. As shown in FIG. 7(a), the charge storage section shown in this embodiment covers a first conductive polycrystalline silicon 81 having a T-shaped cross section with an insulating film 82, and further covers this insulating film 82 with a first conductive polycrystalline silicon 81 having a T-shaped cross section. It has a structure in which it is coated with conductive polycrystalline silicon 83 of No. 2.

When manufacturing a charge storage section configured in this way, first, the silicon substrate 13 is thermally oxidized to form a silicon thermal oxide film (
An insulating film having a higher etch rate than the thermal oxide film 84, such as PS, is formed on the thermal oxide film 84.
Deposit G84.

Then, a hole 86 reaching the thermal oxide film 84 is formed in the PS, and a first polycrystalline silicon 81 is deposited in this hole and on the PSG layer 85. And polycrystalline silicon layer 81
A resist pattern 87 having a diameter somewhat larger than the diameter of the hole 86 is formed at a position above and facing the hole 86 (as shown in FIG. 7(b)).

Next, the polycrystalline silicon 81 is etched while being masked with a resist pattern 87 to form a first polycrystalline silicon 81 having a T-shaped cross section (as shown in FIG. 7(c)).

Next, the resist 87 is removed and PS is further removed using an HF solution.
G layer 85 is selectively removed. Thereafter, a thin oxide film 82 is formed on the surface of the first polycrystalline silicon layer 81 (as shown in FIG. 7(d)).

Next, polycrystalline silicon is deposited by low pressure CVD on the first polycrystalline silicon layer 81 on which the oxide film 82 has been formed, and a second polycrystalline silicon layer covering the first polycrystalline silicon layer 81 is formed. A silicon layer 83 is formed (as shown in FIG. 7(e)).

Then, the second polycrystalline silicon 8 is coated with a resist mask 88.
3 is etched to form a charge storage portion having the shape shown in FIG. 7(a) (as shown in FIG. 7(f)).

According to the charge storage section shown in the second embodiment, the charge storage region has a T-shaped cross section and its surface area is increased, so that the charge storage capacity can be increased, and therefore the charge storage region according to the first embodiment The same effects can be obtained.

FIG. 8 is a diagram showing a modification of the second embodiment.

In this modification, the first polycrystalline silicon layer 91. Insulator 9
2. This is an example in which the shape of the charge storage region made of the second polycrystalline silicon layer 93 is H-shaped in cross section.

The manufacturing process of this charge storage section will be explained.

First, the silicon substrate 13 is oxidized to form an oxide film 9 on its surface.
After depositing a first polycrystalline silicon layer on this oxide film 94, a pattern is formed by photolithography to form a polycrystalline silicon layer 95 having the width shown. and,
PSG is deposited, a hole 96a communicating with the polycrystalline silicon 95 is opened from above the 286 layer 96, and the 286
Polycrystalline silicon 97 is deposited on the sixth layer 96 (as shown in FIG. 8(b)).

Next, the polycrystalline silicon layer 97 is patterned using a resist mask 98 with a remaining pattern having a width larger than the diameter of the hole 96a (as shown in FIG. 8(c)).

Next, the resist 98 and PSG 96 are selectively removed, and a first polycrystalline silicon layer 91 having an H-shaped cross section is formed.
A thin oxide film 92 is formed by thermal oxidation on the surface of the
Figure (d) (illustrated).

Next, a second polycrystalline silicon layer 93 is deposited on the entire insulating film 92, and an electrode pattern covering the first polycrystalline silicon layer 91 is formed using a resist mask 99 (as shown in FIG. 8(e)). .

According to the charge storage section configured in this way, the charge storage section shown in FIG.
) can store a larger amount of charge than the charge storage section shown in FIG.

FIG. 9 is a diagram showing another modification of the second embodiment. This modification is an example in which the charge storage region has a cross-sectional shape in which two T-shapes are stacked one on top of the other. That is, T
A first polycrystalline silicon layer 101 having a cross-sectional shape of two stacked letters, an insulating 7 film 102 formed on the surface of this first polycrystalline silicon layer 101, and a first polycrystalline silicon layer 101. A charge storage region is formed from the second polycrystalline silicon layer 103 formed to cover the second polycrystalline silicon layer 103.

When manufacturing a charge storage section having such a configuration, the silicon substrate 13 is oxidized to form an oxide film 104, and the first PSG 105 is deposited on this oxide film 104. Then, a hole 105a communicating with the oxide film 104 is formed in the PSG layer 105 by photolithography.
Polycrystalline silicon is deposited in a and on the PSG layer 105.

Next, a resist mask 1 larger than the hole diameter of the hole 105a is placed in the polycrystalline silicon layer 106 at a position opposite to the hole 105a.
07 is formed, and the polycrystalline silicon layer 105 is etched (as shown in FIG. 9(b)).

Next, a second PSG 108 is deposited, and a hole 105a is formed in the polycrystalline silicon layer 108 at a position opposite to the hole 105a.
A hole 108a having a hole diameter equivalent to that of is formed, and polycrystalline silicon 109 is deposited in this hole and on the PSG layer 108 (as shown in FIG. 9(C)).

Next, the polycrystalline silicon layer 10 facing the hole 108a
A resist mask 110 having a diameter larger than that of the hole 108a is formed in a predetermined region on the polycrystalline silicon layer 109, and the polycrystalline silicon layer 109 is etched (as shown in FIG. 9(d)).

And resist 110 and PSGI? After removing J108, the first section has the shape of two stacked T-shapes.
A polycrystalline silicon layer 101 is formed, and the surface of the first polycrystalline silicon layer 101 is oxidized to form a thin oxide film 102 as an insulating film (as shown in FIG. 9(e)).

Then, a second polycrystalline silicon 102 is deposited and the first
Then, a part of the second polycrystalline silicon layer 103 is etched using a resist mask 111 to form an electrode pattern (see FIG. 9(f)).
).

According to such a charge storage section, more charges can be stored than the charge storage section shown in FIG.

Next, a third embodiment of the present invention will be described.

This embodiment is an example in which a charge accumulation section shown in FIG. 10(a) is used in place of the charge accumulation section 14 shown in the first embodiment. This charge storage part has a large dielectric constant (dielectric constant ε-27) T
An insulating film 121 made of a2O5 is formed into conductive layers 122 and 123.
It has a structure sandwiched between.

When producing the charge storage section configured in this manner, a thermal oxide film 124 is formed on the silicon substrate 13, and Ta 122 is further deposited on the thermal oxide film 124 by electron beam evaporation or sputtering.

Then, silicon oxide 1 is deposited on the Ta layer 122 by the CVD method.
25 is deposited, and a Ta layer 1 is deposited on this silicon oxide layer 125.
A hole 125a communicating with 22 is opened. Next, hole 125a
The exposed Ta is converted to Ta2O5121 by anodic oxidation. Note that the thickness of the Ta2O5 layer 121 can be changed by changing the applied voltage (as shown in FIG. 10(b)).

Next, with a resist mask 126, the silicon oxide layer 125,
The Ta layer 122 is etched to form a lower electrode pattern (as shown in FIG. 10(c)).

Next, the resist 126 is removed, and the metal 1 that will become the upper electrode is removed.
'l'a2 is deposited using resist mask 127.
The Os 121 is etched between the Ta layer 122 and the metal layer 123 to form an upper electrode. Then, a contact hole is made in the silicon oxide layer 125, and a terminal 128 connected to the Ta layer 122, which will become the lower electrode, is drawn out.

Note that the contact hole may be opened using a resist mask before forming the upper electrode, or may be opened after the metal layer 123 is deposited (as shown in FIG. 10(d)).
.

According to this embodiment, Ta2O with a large dielectric constant
Since the insulating film 121 made of 5 is sandwiched between the conductive layers 122 and 123, the amount of charge storage can be increased without increasing the area of the charge storage region.

Next, a modification of the third embodiment will be described. In this modification, as shown in FIG. 11(a), a metal layer 13 of Ta2O5 formed by sputtering or anodic oxidation is used.
3 and a conductive layer 133 made of Ta or other metal.

When manufacturing the charge storage section shown in this modification, first, an oxide film 134 is formed on the silicon substrate 13. When Ta2O5 is formed by sputtering, Ta or other metal 133 is deposited by vapor deposition or sputtering, and Ta2O5131 is formed thereon by sputtering. In addition, when forming by anodic oxidation method, Ta1
33 is deposited by vapor deposition or sputtering, and Ta2O5131 is formed thereon by anodic oxidation (the first
(Figure 1(b) shown).

Then, a metal 132 as an upper electrode is deposited, and the metal layer 132 is etched using a resist mask 135 to form an upper electrode. After that, apply additional resist and T
A2O5131 and a part of the conductive layer 133 are etched to form a lower electrode (as shown in FIG. 11(d)).

Then, terminals are provided on the metal layer 132 and the conductive layer 133 made of Ta or other metal, thereby producing the charge storage section shown in FIG. 11(a).

〔Effect of the invention〕

According to the present invention, the area occupied by the charge storage section is kept small;
In addition, since the surface area of the load storage region is increased, it can hold a sufficiently large charge compared to the tunnel switch section even though it occupies a small area, making it possible to achieve high integration and increase memory capacity, and to achieve an extremely high S/N ratio. The stored information can be read out in good condition.

Furthermore, since the insulating film made of Ta2O5, which has a high dielectric constant, is sandwiched between conductive layers, the memory capacity can be increased.

[Brief explanation of the drawing]

1 to 4 are diagrams showing a first embodiment of the present invention.
The figure is a cross-sectional view of a three-dimensional memory element, Figures 2 (a) to (f)
3 shows the circuit configuration of the three-dimensional memory element, FIG. 4(a) shows the waveform of the write pulse, and FIG. 4(b) shows the waveform of the transfer pulse. Figure, 4th
Figure (c) is a waveform diagram of the readout pulse.
FIG. 5 is a configuration diagram of a modification of the charge storage section shown in the embodiment.
FIGS. 6(b) to (e) are diagrams showing the manufacturing process of another modified example shown in FIG. 7(a), and FIG. A configuration diagram of the charge storage section shown in the second embodiment, FIGS. 7(b) to (f) are diagrams showing the manufacturing process of the charge storage section shown in the second embodiment, and FIG. 8(a) is a diagram showing the manufacturing process of the charge storage section shown in the second embodiment. Configuration diagrams of modified examples of the charge storage section shown in the example, FIGS. 8(b) to (e)
) is a diagram showing the manufacturing process of a modified example shown in FIG. 9(a), and FIG. Block diagram of charge storage section, 10th
11(b) to (d) are diagrams showing the manufacturing process of the charge storage section shown in FIG. 11(a), FIG. 11(a) is a configuration diagram of a modification of the charge storage section shown in the third embodiment, 11(b) to (d) are diagrams showing the manufacturing process of the modified example shown in FIG. 11(a), FIG. 12 is a block diagram of a conventional nonlinear conductivity element, and FIG. 13 is a diagram of a nonlinear conductivity element. FIG. 3 is a diagram showing hysteresis characteristics. 12... Charge transfer path, 13... Silicon substrate, 14
...charge storage section, 21...N-type diffusion layer, 22...
Oxide film, 23... polycrystalline silicon layer. Applicant's agent Patent attorney Jun Tsuboi Figure 4 <c> Rattan 5 Figure s6 Figure 7 Figure 8 Figure 12 Figure 13 Figure 08a 9th! Figure 10 Figure 11 Procedural Amendment 1. Display of the case Japanese Patent Application No. 1-131862 2, Name of the invention Three-dimensional memory device 3, Person making the amendment Relationship to the case Patent applicant (037) Olympus Optical Industry Co., Ltd. 4, Agent 3, Kasumigaseki, Chiyoda-ku, Tokyo Chome 7-2 Address: 100 Phone: 03 (502) 3181 (main representative)
7. Details of the amendment (1) From line 13 to line 14 of page 5 of the specification, the phrase "Langmuir-Prodgett membrane" is corrected to "Langmuir-Prodgett membrane." (2) In the second line of page 7 of the specification, the phrase "if the capacity is small" is corrected to "if the capacity is large." (3) From page 11, line 11 to line 12 of the specification, the phrase "on the conductive layer 1c" is corrected to "on the conductive layer 12C." (4) On page 11, line 14 of the specification, the phrase "on the conductive layer 12C and the uppermost layer" is corrected to "on the lowermost layer." (5) On page 14, line 13 of the specification, rRI FJ is corrected to rRI El. (6) Insert the phrase "Here, t is the insulating film thickness of the tunnel switch, and ■ is the voltage applied to the tunnel switch" after "has" on page 16, line 6 of the specification. do. (7) In the 8th line of page 16 of the specification, the phrase "Fig. 4 (a)" is corrected to "Fig. 4." (8) In the 11th line of page 16 of the specification, the phrase "Fig. 4 (b)" is corrected to "Fig. 4." (9) In the 15th line of page 16 of the specification, the phrase "Fig. 4 (C)" is corrected to "Fig. 4." (10) On page 17, line 16 of the specification, the word "high level" is corrected to "low level." (11) On page 17, line 17 of the specification, "low level" is corrected to "high level." (12) In the fourth line of page 18 of the specification, the phrase "high level" is corrected to "low level." (13) On page 18, line 5 of the specification, "low level" is corrected to "high level." (14) From lines 5 to 8 of page 18 of the specification, the statement ``At this time...... is being applied.'' is deleted. (15) From line 8 to line 9 of page 18 of the specification, the phrase "Fig. 4 (b)" is corrected to "Fig. 4." (16) From line 8 to line 10 of page 32 of the specification, [Figure 4 (a) is a pulse waveform diagram] was replaced with ``Figure 4 is a write pulse, transfer Pulse. A diagram showing a timing chart of read pulses,” is corrected. (17) Figures 3 and 4 of the drawings will be corrected as shown in the attached sheet.

Claims (4)

[Claims] (1) A memory cell is constituted by a tunnel switch section in which conductive layers are placed opposite to each other with an insulating film interposed therebetween and charges are tunnel-conducted through the insulating film, and a charge storage section electrically connected to the tunnel switch section. However, in a three-dimensional memory element formed by stacking a plurality of memory cells on a substrate, the charge storage section includes a diffusion layer formed along the surface of a groove provided on the surface of the semiconductor substrate, and a diffusion layer formed by the diffusion layer. A three-dimensional memory element comprising: an insulating film formed to cover the surface of the groove; and a conductive polycrystal deposited on the insulating film so as to fill the groove. (2) The charge storage section includes a first insulating film formed to cover the surface of a groove provided on the surface of the semiconductor substrate;
a first conductive polycrystalline body deposited to a predetermined thickness on an insulating film; a second insulating film formed to cover the surface of this first conductive polycrystalline body; 2. The three-dimensional memory element according to claim 1, further comprising a second conductive polycrystalline body deposited on the second insulating film so as to fill the groove. (3) The charge storage section includes a first insulating film formed on a semiconductor substrate, and a first conductive polycrystalline body formed on the first insulating film and having a shape with a large surface area; This first
a second insulating film formed to cover the surface of the conductive polycrystalline body, and a second insulating film deposited to cover the second insulating film.
2. The three-dimensional memory element according to claim 1, wherein the three-dimensional memory element is comprised of a conductive polycrystalline body. (4) The three-dimensional memory element according to claim 1, wherein the charge storage section has a structure in which an insulating film made of Ta_2O_5 is sandwiched between conductive layers.