JPH02310642A - Data write system - Google Patents

Abstract

PURPOSE:To terminate writing even at the time of abnormality in a memory so as to completely prevent the hang-up of a system by supervising the termination of writing with a state signal outputted from the memory and supervising data write time. CONSTITUTION:The head address in an area where there is a write request is subtracted and it is held as a result 1. Then, the result 1 is subtracted from the byte of a data string which is to be written, and it is set to be a result 2. When the result 2 is '0' or negative at that time, the previous number of bytes is used as the number of collective bytes. If not, the result 2 is used. Then, the previous number of bytes is subtracted from the number of write bytes and it is held as the new number of write bytes. Then, a write timer is preset. Data for the number of the collective write bytes are sequentially written into EEPROM 2 from the write head address.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data writing method of a semiconductor memory used as a data memory of an IC card, etc.
Especially, for example, Ready/Busy (Ilus)
y) relates to a method for writing data into a memory with signals and the like.

(Prior Art) Recently, as a semiconductor memory, EEPROM, which can electrically erase and rewrite data, has replaced EPROM.
is attracting attention. However, since the data writing time of EEPROM is longer than that of EPROM, various improvements have been made.

As one of these, an EEFROM has been developed which is designed to output a status signal to notify the outside of the completion of internal writing, thereby reducing the external writing processing load. That is, after sending write data to the EEPROM from the outside, it can be easily determined whether or not writing has been completed by simply monitoring the write completion status signal output from the EEFROM.

(Problem to be solved by the invention) However, with such a system, for example, EEPRO
If there is an error in M, write data is sent from the outside, internal writing is performed, and when the write end status signal does not reach the level indicating completion, the external side not only does not know that the write has ended. There is a problem in that the process ends up being stopped.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a data writing method that can terminate the writing process even if there is an abnormality in the memory, and can completely prevent a system using the system from hanging up.

[Structure of the Invention] (Means for Solving the Problems) The data writing method of the present invention includes a means for accepting write data, a writing means for writing the data accepted by the means into a memory, and a method for writing data output from the memory. a determining means for determining whether data writing is completed based on the status signal;
and time monitoring means for monitoring data writing time by the writing means, and the data writing process to the memory is terminated based on the judgment result of the judgment means and the monitoring result of the time monitoring means.

(Function) By monitoring the completion of writing based on the status signal (for example, write end status signal) output from the memory, and also monitoring the data write time, it is possible to detect if there is some abnormality in the memory, for example, by the write end status signal. Even if the write process does not reach a level that indicates termination, the write process can be terminated, and hang-up of the system using this can be completely prevented.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 shows an example of the configuration of a microcomputer system, such as an IC card, to which the data writing method according to the present invention is applied, for example, using a 280 type manufactured by Zilog as a CPU. That is, 1 is the CPU,
2 is EEPROM that stores various data, 3 is CPU
A ROM (for example, a mask ROM) in which program data for performing operations is stored, and a RAM 4 serving as a work memory during operations are connected by an address bus 5 and a data bus 6. .

The above three types of memories 2, 3.4 are arranged on the memory map of the CPUI, and the decoder 7 is activated by address data supplied from the CPUI to the address bus 5 and an MREQ (memory request) signal from the CPUI. Each CE (chip enable) signal is generated by

The EEPROM2 uses an internal write operation signal, namely R (Ready) / B (Busy) as its status signal.
) signal is output from the R/B terminal. This R/B signal is
It is supplied to the input terminal of the tristate gate 8. The tri-state gate 8 receives l0RQ (
It is controlled by the output of an OR circuit 9 which receives input/output request) signals and RD (read pulse) signals.

As a result, the tri-state gate 8 responds to the I ORQ signal and the RD double signal from the CPUI, and the gate changes from non-conductive to conductive for the time period when both these two signals become "L", and the gate changes from non-conductive to conductive. It is configured such that the supplied R/B signal is supplied to the Oth bit of the data bus 6.

Next, in such a configuration, CPU1
The first step is to write the data string on RAMJ to M2.
This will be explained with reference to the flowchart shown in the figure. First, the start address of the area where the write request is made (write start address)
is subtracted from the first address of the page next to the page to which that address belongs, and the result is held as result 1 (31).
2 i; L, for example, assuming that it is 32 bytes/page. For example, if $AOOO is the write start address, the start address of the next page is $AO20,
Result 1 is 32 bytes, and if $AO82 is the write start address, the start address of the next page is $AOAO.
, result 1 is 30 bytes, and so on.

Next, the result 1 is subtracted from the number of bytes of the data string to be written, and the result is set as the result 2 (S2). At this time, if result 2 is "0" or negative (S3), the previous write byte count is used as the batch write byte count (S4)
, otherwise use result 2 (S5).

Now, in step S6, the number of batch write bytes to be used in the previous step S4 or S5 is subtracted from the number of write bytes and held as a new number of write bytes. Next, in step S7, a write timer is preset.

Next, in step S8, data corresponding to the number of batch write bytes is sequentially written from the write start address to the EEFROM 2 using a page write procedure.

Next, in step S9, the LSB of the data obtained by the I10 gravimetric force command is checked, and if it is "1° (ready state)", it means that the writing is completed, so step S12
If it is “0° (busy)”,
The write timer is decremented (510), and it is checked whether the timer has reached "0" (S11). As a result of this confirmation, if it is not "0", the process returns to step S9, and if it is "0", it is assumed that the state has not changed from the busy state to the ready state within the specified time, and the process moves to error processing.

Now, in step S12, a verify check is performed using the write start address, the number of batch write bytes, and the write data string targeted in step S8,
If the check result is negative (S13), the process moves to error processing. If the above check result is positive (S13), it is determined whether the number of written bytes updated in step S6 is "0" (514), and if it is "0".
If so, the operation ends. If it is other than "0", the next address of the current batch write area is set as the write start address (S15), and the process returns to step S1.

In this way, the R/B signal (
By monitoring the completion of writing using the write completion status signal (write completion status signal) and also monitoring the data write time using the write timer, even if there is some kind of abnormality in the EEPROM and the R/B signal becomes busy, The write process can be terminated, and system hang-ups using this can be completely prevented.

Note that the specifications of the EEFROM in the above embodiment are as follows:
Although an example using the R/B signal from the R/B terminal has been shown, for example, so-called data polling (Data Polling)
ing) method may also be used.

Further, in the flowchart of the embodiment, an example is shown in which a soft timer is realized in step S10, but a similar function may be realized by, for example, a hard timer.

Further, in step Sll, regarding error processing after the timer reaches "0", it is desirable to change the busy state to the ready state by some method depending on the specifications of the EEPROM.

[Effects of the Invention] As detailed above, according to the present invention, even if there is an abnormality in the memory, the write process can be completed, and the system using the data can be completely prevented from hanging up. Write method can be provided.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention; FIG. 1 is a flowchart explaining data writing processing, and FIG. 2 is a block diagram showing an example of a hardware configuration. 1-CPU, 2-EEPROM <1-E-U), 3
...ROM (memory), 4...RAM (memory), 5...address bus, 6...data bus, 7.
··decoder. Applicant's representative Patent attorney Takehiko Suzue 11tl! 1(a) II 1 am(b)

Claims (1)

[Scope of Claims] Means for accepting write data; writing means for writing the data accepted by the means into a memory; and determining means for determining whether data writing is completed based on a status signal output from the memory. and time monitoring means for monitoring data writing time by the writing means, and the data writing process to the memory is terminated according to the judgment result of the judgment means and the monitoring result of the time monitoring means. Writing method.