JPH02310475A - Detecting circuit for clock interruption - Google Patents

Abstract

PURPOSE:To prevent an erroneous clock signal inputting to a device by selecting one transmitting signal out of a 1st and 2nd AND circuits to output by a selection circuit. CONSTITUTION:The plural 1st time limit circuits 1, 2 which are respectively furnished with different times of the time limit operate in response to the clock signal at the time when any one among the clock signals having plural kinds of cycle is inputted. These circuits 1, 2 are utilized, and further a time limit circuit 11 to monitor the condition of output signal from the circuit 2, AND circuit 31 to take a logical product of the output signal from circuit 1 and the output signal from circuit 11, inversion circuit 21 to invert a logical level of the output signal from circuit 11, and AND circuit 32 to take a logical product of the output signal from circuit 2 and the output signal from circuit 21 are additionally connected. Then, either one of the output signals from the circuits 31 and 32 is selected by the selection circuit 5 in accordance with the selection signal and sent out as the output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock interruption detection circuit, and more particularly to a clock interruption detection circuit in which a plurality of clock signals having different frequencies are selected and inputted by switching or the like.

[Conventional technology]

In this conventional clock interruption detection circuit, it is necessary not only to detect the interruption of the clock signal but also to detect the presence or absence of clock interruption at the desired timing according to the frequency of the input clock signal. A clock interruption detection means is provided for each frequency of the clock signal, and each of these output signals is selected and outputted by a selection circuit.

FIG. 2 is a block diagram illustrating a conventional clock disconnection detection circuit having this more structured structure, in which one of two types of clock signals having different frequencies arrives as an input signal. In the figure, the time limit circuits 1 and 20 are each set to have a length longer than one period of the corresponding clock signal in a normal state, and are constructed of, for example, a retriggerable monostaple multivibrator. Is the selection circuit 5 a time limit circuit 1s? and 2 is selected according to the selection signal and sent out as the output signal. Time limit circuits 1 and 2 are triggered at the rising point of the input clock signal, and each outputs a logic level "1" within a predetermined time limit, and continues beyond the time limit until the next trigger is input. During this period, a logic level "O" is output. The time limit times of time limit circuits 1 and 2 are longer than the period of the corresponding clock signal, so if the normal lock signal is input,
It continues to send out the logic level @1". When the clock signal is disconnected, the logic level is inverted to 0"K after the time limit has elapsed from the time when it was triggered by the last input clock pulse, and the disconnection of the clock signal is detected. do. Therefore, if the time limit circuits 1 and 20 time limits T1 and T2 are set to values that satisfy the following equations (1) and (2), it is possible to detect the loss of one bit of the corresponding input clock.

tx < Ts < 2 tl (1
)tx < Tx < 2 tz・・・・・・(
2) Here, tl is the period of the first clock signal, and tz is the period of the second clock signal.

[Problem to be solved by the invention]

In the conventional clock disconnection detection circuit described above, when the higher frequency clock signal of the two types of clock signals is input, the period of the clock signal is changed to the time limit circuits 1 and 2.
Since the output signal of both timer circuits continues to send out the logic level ""1" indicating the normal state, the selection signal is used to select the timer circuit l.
No matter which output signal of 2 or 2 is selected, a logic level of 01''' indicating a normal state is always sent out.In other words, a selection signal is added depending on the type of input clock signal, and The output signal of one of the timer circuits 1 and 2 is selected and output, but as mentioned above, no matter which output signal is taken out, the same state, that is, the state of logic level "1". When you say that, is this the result of adding the correct selection signal according to the type of clock signal that is being input, or is it true that this is the case even though a selection signal that does not correspond to the type of input clock signal is added to the button? , it is not possible to distinguish from the output signal of the selection circuit 5 whether the logic level 'm1' is obtained or not. Therefore, even if there is an inappropriate correspondence between the input clock signal type actually input to the circuit and the selection signal, no alarm is generated, so an incorrect clock signal is supplied to the device that uses the clock signal. There are drawbacks that seriously affect the operation of the device.

An object of the present invention is to provide a clock that can issue an alarm even when the correspondence between the input clock signal type and the selection signal is inappropriate and prevent an incorrect clock signal from being input to a device using a simple circuit configuration. An object of the present invention is to provide a disconnection detection circuit.

[Means to solve the problem]

The circuit of the present invention includes a plurality of first timer circuits that are activated in response to input of any one of clock signals of plural types of cycles each having a different timer, and a plurality of first timer circuits that are activated in response to the input of any one of clock signals having different periods, and at least one second timer circuit activated in response to a sending signal of the first timer circuit other than the first timer circuit having a longest time limit; Sending out an AND signal of both transmission ratio signals of a timer circuit and one second timer circuit that is activated by the sending signal of one of the first timer circuits having the second length of the timer circuit; one first AND circuit, one of the 41 time limit circuits having a time limit other than the longest time limit, and one second time limit circuit activated by the first time limit circuit's send signal. at least one second AND circuit that sends out an AND signal with an inverted signal of the signal; and a selection circuit that selects and outputs a sending signal of one of the first and second AND circuits. It is equipped with.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and shows a case where one of 2\M clock signals having different frequencies is input. Time limit circuit 1'
J? and 2 are used in the same way as in the conventional circuit shown in FIG. An AND circuit 31 that performs AND with the output signal of the timer circuit 11; and an inverter circuit 21 that inverts the logic level of the output signal of the timer circuit 11. Output signal of time limit circuit 2 and inverting circuit 2
An AND circuit 32 that performs an AND with the output signal of 1 is additionally connected. The selection circuit 5 includes AND circuits 31 and 3
selecting one of the two output signals according to the selection signal;
This is sent out as an output signal. Timing circuits 1.2 and 110 are timed at T1. T2 and 'I'll are set to satisfy the following equations (4) to (6) when the periods t, , t2 of the two clock signals that can be input have the relationship shown in the following equation (3). .

tl>t2...(3) t1<
T1...(4)t2<T2<t
s...(5) t2<Tll...
-(6) Next, the operation of this embodiment will be explained.

First, if the input signal is a clock signal with a lower frequency, the period t! of the input clock signal! is the above formula (4),
(As shown in 51, since it is shorter than the time limit T1 and longer than the time limit T2, the output signal of the time limit circuit 1 maintains the logic level "1", and the output signal of the time limit circuit 2 has a period of 11
The deity ratio is T2/l.

It becomes a police box signal. The timer circuit 11 receiving this alternating signal has a cycle of 1. Since it is activated every time, its output signal maintains the logic level "1". Therefore, the output signal of the AND circuit 31 maintains the logic level "1". At this time, if a selection signal for selecting the output signal of the AND circuit 41 is given, the output signal sent out by the selection circuit 5 maintains the logic level "1", indicating that the input signal is normal. .

When a disconnection failure occurs in the input clock signal, the output signals of timer circuits 1 and 11 are inverted and become 0'' after time T and Tll have elapsed after the clock pulse just before the disconnection is input, respectively. The output signal of the circuit 31 is also inverted and becomes 0'' after time T1 or 'I'll. In response to this, the output signal of the selection circuit 5 becomes a logical level "0", indicating a clock disconnection failure.

Furthermore, if a selection signal instructing to detect the disconnection of the clock signal of period t2 is erroneously given to the selection circuit 5 when the clock signal of period tl is input, the output signal of the AND circuit 32 is selected and the output signal is becomes. In this case, as described above, the output signal of the time limit circuit 2 is an alternating signal with a period tl, and the output signal of the time limit circuit 11 maintains the logic level ``1''.

The output signal of the timer circuit 11 passes through the inversion circuit 21 and its logic level becomes inverted ``0'', so the output signal of the AND circuit 32 maintains the logic level ``0''. Therefore, the output signal of the selection circuit 5 becomes a logic level @0'', indicating a clock disconnection failure.In other words, even when the correspondence between the input clock signal type and the selection signal is mismatched, an incorrect clock signal is input to the device. It is possible to prevent this from happening.

Next, when the input signal is a clock signal with a higher frequency, the period t2 of the input clock signal is determined from the time limit times T15p and T2 of time limit circuits 1 and 20, as in equations (3) or 5) above. is also short, so timed circuits 1 and 2
The output signals of both are at logic level "1". Further, in this state, the time limit circuit 11 is not activated, so its output signal becomes a logic level "O"'. Therefore, the AND circuit 31
The output signal of the AND circuit 32 becomes ``0'', and the output signal of the AND circuit 32 becomes ``1''. Since the output signal of the circuit 32 is selected and output, the output signal of the selection circuit 5 is at logic level "1".When a disconnection failure occurs in the input clock signal, the time limit circuit 2
Since the output signals of and 11 are inverted after time T2 and Tll have passed after the input of the clock pulse just before the cutoff, respectively, and become "+", the output signal of the AND circuit 32 is also inverted and becomes the logic level *Ow. This is selected by the selection circuit 5 and sent out as an output signal, and clock interruption is detected.

Further, when the clock signal of period t2 is input, the selection circuit 50
Incorrect selection signal in period 1. When a selection signal instructing to detect a clock signal disconnection is applied, the output signal of the AND circuit 31 is selected and becomes the output signal of the selection circuit 5, but as described above, this signal is at the logic level "0". This indicates that the clock is disconnected. That is, it is possible to detect a mismatch between the input clock signal type and the selection signal, and it is possible to prevent an incorrect clock signal from being input to the device.

In this way, not only a disconnection failure of the input clock signal but also a case where a clock signal different from the selected clock signal type is input can be detected based on the logic level of the output signal.

FIG. 3 is a block diagram showing a second embodiment of the present invention, and shows an example of application to a case where any one of n clock signals having different frequencies is input. The input signal is input to timer circuits l~n, among which timer circuits 2~
+1 sending signal is each timed circuit 11S1 (n-1)
sent to. Furthermore, the sending signals of each timer circuit 1 to n are 8! Sent to product times S3t~3n, timed times w111~
1 (n-1) transmission signals are respectively connected to AND circuits 31 to 3.
(n-1) and the inversion circuits 21 to 2 (n-1). Further, the output signals of the inverting circuits 21 to 2 (n-1) are sent to AND circuits 32 to 3n, respectively.

Each output signal from the AND circuits 31 to 3n is input to the selection circuit 50, and the selection circuit 50 selects one of them according to the selection signal.
Select one and send it as an output signal. The time limit times T, %Tn of the time limit circuits 1 to n, and the time limit times T1t to TDn-8) of the time limit circuits 11 to 1 (n-1) are calculated by the following formula ( 7), the following equations (8) to (14) should be satisfied.

t l>t 2>...>1k-x>tk>
tk+1>・"tH-1> tn...(7) 1, <Tyu...(8) t2<
T2<tl...(9)tk
kuTkkutk-1...(10) tk+l<Tk+l
<tk...(11)tn-□<
Tl-1< tn-2 (12) tn<Tn<
tn-1...(13) tl<T, □<...<Tx
(k-z)<Tx(k-x)<Tlk<...<Tx(
n-z)<Tt(n-1)...(14) Third
Focusing on the AND circuit 3kVC in the prison, the input/output state at the time of inputting the clock signal with period t is expressed as tK
, when the period t is longer than tk, and when the period t is shorter than tk.According to Table 1, when a clock signal with a period ik is input, the AND circuit 3 of the AND circuits 31 to 3n Only the output signal is at logic level "1", and the other output signals are at logic level "1".
In addition, when the human clock signal is cut off, all the output signals of the AND circuits 31 to 3n become logic level "0".This prevents not only the cutoff of the input clock signal but also the input signal from the selection signal. Even if a clock signal of a different type is input, this can be detected.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, with a simple circuit configuration, it is possible to prevent not only input clock disconnection failures but also
Even if a clock signal different from the selected clock signal type is input, this can be detected, and an effect of preventing erroneous operation of the device can be obtained.

[Brief explanation of drawings]

1 and 3 are block diagrams showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional clock disconnection detection circuit. 1-n, 11-1 (n-1)...Timed circuit, 2
1-2(n-1)...Inversion circuit, 31-3n.
...Logic product circuit, 5,50...Selection circuit. Agent Patent Attorney Otodon Uchihara 1st time 2nd time

Claims (1)

[Claims] a plurality of first time circuits that are activated in response to input of any one of clock signals of a plurality of types of cycles, each having a different time limit; and one first time limit circuit having the longest time limit. at least one second timer circuit activated in response to a sending signal of the first timer circuit other than the timer circuit, and one second timer circuit having the longest timer period and the second timer circuit having the longest timer period. one said second timer circuit activated by the sender signal of the one said first timer circuit having said time limit time of length; and one sends an AND signal of both sender signals;
one first AND circuit, one first timer circuit having a time limit other than the longest, and one second timer circuit activated by the first timer circuit's sendout signal. at least one second AND circuit that outputs an AND signal with an inverted signal of the output signal; and a selection circuit that selects and outputs one output signal from the first and second AND circuits. A clock disconnection detection circuit comprising: