JPH02309841A - Modulator - Google Patents

Abstract

PURPOSE:To increase an IF frequency with no adjustment by making a sampling frequency of a digital signal to be 4 times the carrier frequency. CONSTITUTION:A data signal inputted to data input points 25, 26 is sampled respectively by sampling circuits 27, 28, passes through digital filters 29, 30 and carriers costheta, sintheta from a carrier generating circuit 33 are modulated into an IF band at multipliers 31, 32. Then the modulated waves are synthesized by an adder 34 and converted into an analog signal at a D/A converter 35. Then the signal passes through a DC cut-off filter 36 and the DC component is eliminated and send to the antenna. In this case, the relation of fs=4fc exists, where fs is the sampling clock frequency and fc is the carrier frequency. Since the interleave of sampling frequency is attained, the IF frequency is increased with no adjustment.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a digital modulator.

(Prior Art) Conventionally, analog signal processing has been used in a modulator that modulates a carrier wave with a baseband digital signal to obtain a modulated wave signal in the IF band.

FIG. 9 is a diagram showing the configuration of a quadrature modulator using analog signal processing.

In the figure, 1 is a data input point where an I channel data signal converted from a digital signal is input, and 2 is a data input point where a similarly converted Q channel data signal is input. be.

The data signals input to these data input points 1.2 are
In each multiplier 3.4, the in-phase component of the reference carrier wave from the carrier wave oscillator 5 and the orthogonal component of the base carrier wave via the 90° phase shifter 6 are modulated. Each modulated signal is then combined by an adder 9 after passing through an attenuator 7.8.

The modulated signal synthesized in this way is sent to the multiplier 10 with R
After modulating the RF frequency reference signal from the F frequency reference signal oscillator 11 , it passes through a bandpass filter 12 and is sent to the antenna 13 .

However, such a modulator based on analog signal processing has a disadvantage in that there are a large number of adjustment points and precision parts that must be used, as described below.

First, the amplitude of the in-phase component and the amplitude of the quadrature component input manually to the adder 9 must be balanced.
For example, the characteristics between multipliers 3 and 4 cannot be made completely equal considering manufacturing errors, and therefore it is necessary to adjust the balance between them using attenuators 7 and 8.

Second, unless the phase of the in-phase component and the phase of the quadrature component manually input to the adder 9 maintain a fairly accurate orthogonal relationship, quadrature phase leakage will occur and the deterioration of the 1'1151 wave will be extremely large. . For this reason, a high-quality 90'' phase shifter 6 is required, but such a phase shifter is very expensive and large in size, and is not suitable for the recent demands for miniaturization and cost reduction of modulators.

Third, the delay of the in-phase component between multiplier 3 and adder 9 and the delay of the quadrature component between multiplier 4 and adder 9 must be equal, but there must be attenuators 7 and 8 between them, respectively. are interposed, it is very difficult to adjust these delays equally.

Fourth, the manual impedance of both the in-phase component and the quadrature component of the digital input signal must be precisely matched, and this adjustment is forced at the time of circuit creation.

Fifth, the adjustments listed in the first to fourth items require attenuators and impedance matching circuits that consume large amounts of power, resulting in a modulator that requires large amounts of power.

As described above, modulators based on analog signal processing have various drawbacks.

Therefore, modulators using digital signal processing have been proposed.

FIG. 10 is a diagram showing the configuration of a modulator based on such digital signal processing.

In the figure, 14 is a data input point to which an l-channel data signal, which is a digital signal, is input;
is a data input point to which a similar Q-channel data signal is input.

Here, a constant value is input to the integrator 16 through the input point 17 so as to match the frequency of the carrier wave, and from this integral value COC0
8RO8,5INI? The OM 19 generates an in-phase data signal of the reference carrier wave and an orthogonal data signal of the reference carrier wave.

゛Then, the data signals input to the data input points 14 and 15 are respectively input to the COC08R in the multipliers 20 and 21.
Reference carrier in-phase data signal from O8, SINROM
The reference carrier orthogonal data signals from I 9 are modulated and combined by adder 22 .

The modulated signal synthesized in this way is converted into an analog signal by the D/A converter 23, passes through the low-pass filter 24, and after modulating the RF frequency reference signal from the RF frequency reference signal oscillator 11 in the multiplier 10. , passes through a bandpass filter 12 and is sent to an antenna 13.

Incidentally, such a modulator based on digital signal processing can overcome the drawbacks of the above-mentioned modulator based on analog signal processing, but has the drawback that the IF frequency cannot be increased.

That is, FIG. 11 is a diagram showing frequency changes in a modulator by such digital signal processing, in which the baseband signal (■ in FIG. 11) is modulated, and the IF signal output through the low-pass filter 24 is Let CO9 (2π Nt+φ) be (Fig. 11 ■), and let CO3 (2πf2t) be the RF carrier wave from the RF frequency reference signal oscillator 11 (Fig. 11 ■).

Then, the RF signal output from the multiplier 10 (Fig. 11 ■,
■) is C03(2yr (r2+fl)t+φ)+C0
3(2yr (f'2-fl)t+φ).

Therefore, when the IF frequency 1'l is low, in order to extract the desired signal (Fig. 11 ■) cos(2rr (1'2+f'l) + φ) from the RF signal output, a very steep bandpass filter is required. 12 (■ in Figure 11), which is often technically impossible.

By the way, in digital signal processing, in order to increase the IF frequency, it is necessary to increase the sampling speed and calculation speed.

However, in such a modulator, it is extremely difficult for the transversal filter for waveform shaping, which is placed before the data input point and consists of many multipliers, to perform high-speed calculations associated with the 1F frequency. Even if it is possible, the power consumption is very large and a large amount of heat is generated. Further, multipliers 20 and 21 also have a similar problem.

(Problems to be Solved by the Invention) As described above, a modulator based on analog signal processing has the disadvantage that there are a large number of adjustment points and precision parts that must be used.

Further, in the conventional modulator using digital signal processing, there is a problem that the IF frequency cannot be increased.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a modulator using digital signal processing that can increase the IF frequency without adjustment, and that can be reduced in price and size.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a modulator that modulates a carrier wave with a digital signal to obtain a modulated wave signal in an IF band, in which the sampling frequency of the digital signal is changed to the frequency of the carrier wave. frequency 4
It has been doubled.

A second invention, in the above-described invention, includes a digital/analog converter that converts a carrier wave modulated with the digital signal into an analog signal, and a DC component of the analog signal converted by the digital/analog converter. It is equipped with a DC cut filter.

The third invention modulates the carrier wave with a digital signal, and
In a modulator that obtains a band modulated wave signal, data related to a carrier wave modulated by the digital signal is once stored in a memory, and then the data is stored in the memory at a faster speed than the writing speed of the data to the memory. is read out, and the read data is used as a modulated wave signal in the IF band.

(Function) According to the present invention, in the I channel of the input digital signal, the carrier wave C is placed at the first sampling point.
If OS θ-1 is matched and multiplied, then at the next sampling point COS θ-〇, hereinafter cos θ-1
．． 0.1. They are made to correspond to O, -1, 0-, and are multiplied. At even-numbered sampling points, eO9θ−0
Since it is multiplied in correspondence with , no calculation is necessary, although sampling is performed at this point.

That is, the sampling rate in the modulator of the present invention can be half that of the conventional modulator.In other words, if the multiplication rate of the transversal filter at the front stage of the channel (1) is kept the same, sampling can be performed at twice the rate. In other words,
At the same multiplication speed, it is possible to double the IF frequency.

Also, at odd-numbered sampling points, the input digital signal has COS θ-1 or cos θ-1.
-1 is multiplied. This means that the digital signal can be passed through as is, or it can be inverted and passed through. Therefore, a multiplier for this purpose becomes unnecessary and can be replaced with a simple switching circuit.

The same applies to the Q channel.

In the second invention, as described above, when a digital modulated wave is converted into an analog signal, a DC component appears, but by providing a DC cut filter, this DC component can be removed.

In the third invention, after data related to a carrier wave modulated by a digital signal is once stored in a memory, the data stored in the memory is read out at a higher speed than the writing speed of the data to the memory, and the read data is By setting the modulated wave signal in the IF band to be the modulated wave signal in the IF band, there is an effect that the modulated wave signal in the IF band can be obtained at a frequency higher than the frequency related to the writing speed to the memory.

Here, if the digital modulated wave signal at the IF frequency written to the memory is cos <2 πrlt + θ ([)) and the reading speed of the memory is m times the writing speed, then the digital modulated wave signal at the IF frequency read from the memory The signal becomes cos (2mπl'lt+φ(1)).

Therefore, even if the IF frequency during digital signal processing is kept low and modulated, or even if the sampling rate is digitally modulated at a low speed, by writing to the memory and then reading it out at high speed, the IF frequency that is the output of the memory can be adjusted. It is possible to make it higher.

In addition, the digital modulation wave signal cos (2 m yr fit +φ (net)
) is multiplied by the carrier wave cos (2πr2t) in the RF frequency band, and cos (2π(f'2+l1lfl)t+φ(IIl
t)+cos(2π(“2-IIlrl)t+φ(it
)), which generates spurious waves in addition to the desired wave, but m
If it is large enough, it can be removed with a gentle bandpass filter.

(Example) Hereinafter, details of embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a modulator according to an embodiment of the present invention.

In the figure, 25 is a data input point to which an I-channel data signal, which is a digital signal, is input;
is a data input point to which a similar Q-channel data signal is input.

The data signals input to these data input points 25, 26 are each sampled by sampling circuits 27, 28, and after passing through digital filters 29, 30, multipliers 31, 32, carrier wave generating circuit 33
The carrier waves COS θ and sin θ are modulated into the IF band. Thereafter, the adder 34 synthesizes the D/A converter 3.
5 into an analog signal. Then, after passing through a DC cut filter 36 and having the DC component removed, it is sent to the antenna side.

Here, in the modulator of this embodiment, the relationship is f5=4f'c, where fs is the sampling clock frequency and fc is the carrier frequency. That is, if the wavelength of the sampling clock is l/rs and the wavelength of the carrier wave is l/rc, then 2.1
The relationship is /fs-1/4fc.

In the modulator of this embodiment, such a relationship makes it possible to "thin out" sampling.

This will be explained below based on FIG. 2.

- Focusing on the channel, the input data (Fig. 2 (a)) sampled by the sampling clock (Fig. 2 (b)) and passed through the digital filter 29 is converted into a carrier wave cos θ (Fig. 2 (C)) by the multiplier 31. ) is multiplied by

That is, the first sampling point (Fig. 2 (a)
) is correspondingly multiplied by eO8θ-1 (Fig. 2 (C) ■), and the second sampling point (Fig. 2 (a) ■)
is multiplied by cos θ-0 (Fig. 2 (c) ■), and the third and subsequent sampling points are sequentially COS
It is multiplied correspondingly by θ-1, 0, 1, -1.

Here, if we focus on the even-numbered sampling points, these multiplication results will always be 0 (Figure 2 (d)
).

Therefore, in the modulator of this embodiment, sampling is not performed at even-numbered sampling points, and the amount of calculation in the digital filter 29 is halved. Note that the same applies to the Q channel, and the amount of calculation in the digital filter 30 is halved.

The result obtained by the adder 34 in this way is shown in FIG.
It becomes as shown in e).

Next, other embodiments of the present invention will be described.

FIG. 3 is a block diagram showing the configuration of a modulator according to another embodiment of the present invention.

In the modulator shown in the figure as well, the relationship is fs-41'c, where fs is the sampling clock frequency and fc is the carrier frequency. That is, if the wavelength of the sampling clock is l/rs and the wavelength of the carrier wave is l/rc, then 1/
The relationship is f's-1/4rc.

The data signals input to the data input points 25 and 26 are respectively sampled by sampling circuits 27 and 28, passed through digital filters 29 and 30, and then input to the inversion switching circuit 37. If the input data is in two's complement representation, by adding "bi" to the LSB of the output from the inversion switching circuit, an inverted output with a sign opposite to that of the input signal can be obtained. The output is input to the D/A converter 35.

The inversion switching circuit 37 switches between the output from the digital filter 29.30, the output from the inverter 38.39 that inverts the output J from the digital filter 29.30, and the ground 40.41 in each of the I and Q channels. One of them is selected by switches 42 and 43. Then, one of the outputs from the switches 42 and 43 is selected by the switch 44 and output to the D/A converter 35.

Switching of the switches 42, 43, and 44 in the inversion switching circuit 37 is performed by the sampling circuit 4 by the switching control circuit 45.
This is done based on the sampling clock at 4.

Hereinafter, the operation of this embodiment will be explained based on FIG. 2 mentioned above.

When the pipe port is shown in Figure 2 (d), ■D/A as a channel.
The signals to be input to the converter 35 are as follows: input data as is, 10-person data inverted, 0, input data as is, and so on. Therefore, in response to this, the switching of the switch 42 is changed directly from the digital filter 29 → ground 40 - inversion of the digital filter 29 →
Ground 40 - Directly from digital filter 29 →
..., the same function as the carrier generation circuit 33 in the modulator shown in FIG. 1 can be realized by the inversion switching circuit 37. The same applies to the Q channel.

In addition, the signal shown in Fig. 2(e) (from both channels
/A signal to be input manually to the A converter 35) is switched to the switch 4.
This is realized by switching 4.

In this way, this embodiment not only has the effect of halving the amount of calculation in the digital filters 29 and 30 similar to the modulator shown in FIG. I can do it.

In the modulator shown in FIG. 1 or 3, as can be seen from FIG. 2(d), at points where it is clear from the beginning that the value is 0,
A digital signal processing circuit (not shown) disposed before 8 may be configured to output 0 without performing calculations in advance.

Next, a third embodiment of the present invention will be described.

FIG. 4 is a diagram showing the configuration of a modulator according to a third embodiment of the present invention.

In the figure, 14 is a data input point to which an I-channel data signal, which is a digital signal, is input;
is a data input point to which a similar Q-channel data signal is input.

Here, a constant value is input to the integrator 16 through the input point 17 so as to match the frequency of the carrier wave, and from this integral value COC0
3RO8 and SINROMI 9 generate an in-phase data signal of the reference carrier wave and an orthogonal data signal of the reference carrier wave.

The data signals inputted to data input points 14.15 are then inputted to multipliers 20.21 and
8, the reference carrier in-phase data signal from SINROMI
The signal is modulated by the orthogonal data signal of the base carrier wave from 9, and is combined by the adder 22.

The modulated signal synthesized in this way is temporarily stored in the memory 45, and then converted into an analog signal by the D/A converter 23, passed through the low-pass filter 24, and then the multiplier 1.
RFF from the RFF wave number reference signal oscillator 11 at 0
After modulating the wave number reference signal, it passes through a bandpass filter 12 and is sent to an antenna 13.

Note that 46 is a clock control device that controls the timing of writing and reading from the memory 45.

The modulator of this embodiment will be explained in more detail with reference to the diagram of frequency shift from the digital input signal to the RF multiplied signal shown in FIG.

A predetermined value is manually input from the manual point 17 to the integrator 16 so that the desired first IF frequency rl is obtained, and the COC05R
O8, 90° phase-shifted quadrature carrier generated by SINROMI 9 cos(2yr Nt), -8IN(2yr rlt)
get.

Then, each carrier wave is modulated by a multiplier 20.21 using in-phase data ((2) in FIG. 5) COSφ and orthogonal data ((2) in FIG. 5) SINφ.

Thereafter, both outputs are combined by an adder 22 to obtain a digital modulated wave signal of the first IF band (■ in FIG. 5) cos (2πHt++; 6 (t)).

At this time, the IFF wave number of the carrier wave is set to a relatively low value.

Thereafter, the digital modulated wave signal is temporarily stored in the memory 45, and the data stored in the memory 45 is read out at least faster than the input speed of the signal to the memory 45, and the digital modulated wave signal of the second IF band (see FIG. ■) Output.

Here, the reading speed of the memory 45 is the writing speed m
If the second I read from the memory 45 is
The digital modulated wave signal of FF wave number becomes cos(21Iπf'lt+φ(Ilt)).

Then, the digital modulated wave signal in the second IF band is converted to D/
Analogized by A converter 23, low pass filter 2
4, and multiplier 10 multiplies it by the RF frequency base signal carrier wave (Fig. ))
+cos(2yr (1'2-0111)+φ(ml)
).

Here, in addition to the desired wave, spurious waves (Fig. 5 ■) occur, but if m is sufficiently large, they can be cut out by the gentle bandpass filter 12 (Fig. 5 ■), and the desired transmitted wave (Fig. 5 ■) is generated. Figure ■) can be obtained.

FIG. 6 is a time chart showing writing and reading times and transmission times to the memory 45.

If the time for writing the digital modulated wave signal into the memory 45 (Fig. 6 (a) ■) is 1, then the time for reading the digital modulated wave signal (Fig. 6 (a) ■) is 1/m.
Therefore, the data is compressed to 1/m, and the transmission efficiency is increased.

Furthermore, if the writing and reading times are constant, the times at which the transmission waves are sent are at regular intervals (Fig. 6 (b) ■), and the transmission waves are sent at regular intervals (Fig. 6 (b) ■). This method is suitable for TDM because it can be made to correspond to the time shown in FIG. 6(b) (■).

Next, a fourth embodiment of the present invention will be described.

FIG. 7 is a diagram showing the configuration of a modulator according to a fourth embodiment of the present invention.

In the modulator shown in FIG. 4, the memory 45 in the modulator shown in FIG. (See figures (d) and (e))
This makes it possible to transmit continuous data (see (a) (2) and (c) (2) in FIG. 8). Note that four are switching control units that control switching of the switches 47 and 48.

[Effect of the invention] As explained above, according to the present invention, the I
It is possible to provide a modulator using digital signal processing that allows the F frequency to be increased, and which can be reduced in price and size.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a modulator according to an embodiment of the present invention, Fig. f42 is a diagram showing the flow of signal modulation in this embodiment, and Fig. 3 is another embodiment of the present invention. FIG. 4 is a diagram showing the configuration of a modulator according to the third embodiment of the present invention, and FIG. 5 is a diagram showing the configuration of a modulator according to the third embodiment of the present invention. FIG. 6 is a time chart showing the write time, read time and transmission time to the memory according to the third embodiment, and FIG. 7 is the modulation according to the fourth embodiment of the present invention. of the vessel (
8 is a time chart for explaining the fourth embodiment, FIG. 9 is a diagram showing the configuration of a quadrature modulator based on conventional analog signal processing, and FIG. 10 is a diagram showing the configuration of a conventional digital quadrature modulator. Diagram showing the configuration of a modulator by signal processing, No. 11
The figure is a diagram of frequency shift in the RF multiplied signal from the digital input signal related to the modulator shown in FIG. 10. 25.26...Teter manpower point, 27.28...S...
Combining circuit, 29.30... Digital filter, 31.32... Multiplier, 33... Carrier wave generation circuit, 34 Adder, 35... D/A converter, 36... DC cut filter . Applicant Toshiba Corporation Representative Patent Attorney Suyama Sa - 1chi, 〉) Jshi Q + Yanne ν
Figure 2

Claims (3)

[Claims] (1) A modulator that modulates a carrier wave with a digital signal to obtain a modulated wave signal in an IF band, characterized in that the sampling frequency of the digital signal is four times the frequency of the carrier wave. (2) A digital/analog converter that converts the carrier wave modulated by the digital signal into an analog signal, and a DC cut filter that removes the DC component of the analog signal converted by the digital/analog converter. The modulator according to claim 1, characterized in that: (3) In a modulator that modulates a carrier wave with a digital signal to obtain a modulated wave signal in the IF band, data related to the carrier wave modulated with the digital signal is once stored in a memory, and then the data is written to the memory. A modulator, characterized in that the data stored in the memory is read out at a higher speed than the speed, and the read data is used as a modulated wave signal in the IF band.