JPH02308500A - Electrically programmable and erasable nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve reliability by performing readout alternately with erasure and write repeatedly in an erase cycle and a write cycle with a clock signal, and completing an operation when data is set at an erase level or a write level. CONSTITUTION:The clock signal CLK is operated with the start of a rewrite cycle, and the erasure and the readout are performed alternately in the erase cycle, and the write and the readout are performed alternately in the write cycle with a control circuit 2. A system is comprised so that all bits in a byte performing rewrite can be set at '1's in the erase cycle, and when read out data changes to '1', a rewrite completion detection circuit 3 generates an erasure completion signal, then, the erase cycle is completed. In the next write cycle, the write is repeated, and when readout data changes from '1' to '0', all rewrite cycles are completed. Thereby, the reliability for the completion of the erasure and the write can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an electrically programmable and erasable nonvolatile semiconductor memory device, and more particularly to an electrically programmable and erasable nonvolatile semiconductor memory device that has a memory cell erase cycle and write cycle. Regarding storage devices.

[Conventional technology]

A conventional electrically programmable and erasable nonvolatile semiconductor memory device has a timer circuit for setting erasing and writing times.

The time TT1M set by this timer circuit is longer than the sum of the time T2R and TWR required to create a long pulse by frequency-dividing the oscillation circuit output and actually erase or write to the memory cell. It's meant to be long. T, engineering, while starting rewriting.

When the time elapsed, the rewriting was completed unconditionally without reading the memory cells and confirming their status.

[Problem to be solved by the invention]

In the conventional electrically programmable and erasable nonvolatile semiconductor memory device described above, the time T required for actual cell erasing and writing is
Since the erase/write time is set by a timer circuit independently of ER and TwB, there are the following drawbacks.

The time TTrM set by the timer circuit varies depending on the diffusion conditions and operating temperature of the semiconductor elements constituting the timer circuit. Furthermore, since T, □, and TWR similarly have these dependencies, a sufficient margin must be provided so that TrtM>(T□+'rw,) under any operating conditions. Furthermore, since the state of the cell is not checked at the end of rewriting, there is a drawback that if the erase and write performance of the cell deteriorates due to repeated rewriting, the reliability of rewriting completion will decrease.

Also, for example, if TT work tends to be short on the low temperature side and long on the high temperature side, whereas Tz*, T□ tends to be long on the low temperature side and short on the high temperature side, then T7rx> on the low temperature side
It is necessary to set TTfM so that (TER+TWR). When using this mainly in a high temperature environment, T
TLM>(T+:i+TwR), and since erasing and writing are performed for a long time compared to the cell's ability, extra stress is applied to the cell, which has the disadvantage of accelerating deterioration.

[Means to solve the problem]

The electrically programmable and erasable nonvolatile semiconductor memory device of the present invention includes an electrically programmable and erasable memory cell, and the memory cell is alternately erased and read during an erase cycle using a clock signal. , a control circuit that alternately repeats writing and reading during a write cycle after the end of erasure, and an erase end that notifies the control circuit of the end of erasure when the data read from the memory cell during the erase cycle reaches an erase level. and a rewrite end detection circuit that outputs a rewrite end signal when data read from the memory cell during the write cycle reaches a write data level.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, a memory cell array 1 in which electrically programmable and erasable memory cells 11 are arranged, and a memory cell array 1 are alternately erased and read during an erase cycle using a clock signal CLK, and the erase is completed. A gate circuit G serves as a control circuit 2 that alternately repeats writing and reading during a subsequent write cycle. -G, a sense amplifier 4, and a D flip-flop 6, the data from the data latch circuit 5 and the data from the memory cell array 1 are compared, and the data read from the memory cell array 1 during the erase cycle becomes the erase level. and a rewrite end detection circuit 3 which outputs an erase end signal to notify the control circuit 1 of the end of erasing when the write cycle occurs, and outputs a rewrite end signal when the data read from the memory cell array l reaches the write data level during the write cycle. It is configured to have

Next, the operation of this embodiment will be explained.

FIG. 2 is a waveform diagram of various signals for explaining the operation of this embodiment.

Here, vpp is a high voltage used for erasing and writing the memory cell 11, and the shaded area indicates a floating state.

At the start of the rewriting cycle, the four-way signal CLK operates, and the control circuit 2 controls the memory cell 11 at each period τ.
Voltages VS, VG applied to the source, gate, and drain of
, switch VD and erase ('rg) during erase cycle.
and reading (T8) are performed alternately, and during a write cycle, writing (Tw) and reading (TR) are performed alternately.

During the erase cycle, the expected value D1. is set to 111++ for all bits in the byte being rewritten, and while the read data DS is 0'', erasing is repeated, but when the memory cell 11 is erased, the output becomes 1. ;', the rewriting end detection circuit 3 generates an erase end signal and ends the erase cycle.

In the next write cycle, the data latched in the data latch circuit 5 is used as the expected value. now,
When DIO="1°" and DI="O", the DSO does not write after erasing.

DSL is "1" immediately after erasing is completed, but when writing is repeated and DSI changes to "0°', all successive data matches the expected value, a write end signal is generated, and the entire rewrite cycle is completed. .

FIG. 3 is a circuit diagram of a second embodiment of the present invention, and FIG. 4 is a waveform diagram of each signal.

In this embodiment, instead of the memory cell array 1, a dummy self having the same structure as the memory cell 11 in the memory cell array 1 is provided, and by performing erasing and writing to this dummy self and reading it, the completion of erasing and writing is detected. do.

As in the first embodiment, the dummy self performs erase 2 reading, writing, and reading at the period τ, detects when the sense amplifier 4 output DS changes from the write state "0" to the erase state "1", and erases it. end.

The end of writing is detected by detecting a change from '1'° to '0''.

This embodiment has the advantage that the control circuit is simplified because it does not require comparison with an expected value and the number of cells read during a rewrite cycle is small.

Further, since a normal memory cell performs a rewriting operation even while reading a dummy cell, rewriting takes twice as long as the dummy cell. Therefore, the stress applied to the cell is greater than that in the first embodiment, but on the other hand, this makes it possible to provide a margin for manufacturing variations in the dummy cells.

Additionally, since dummy cells and regular memory cells have the same dependence on manufacturing conditions and temperature, this technology is advantageous in terms of ease of setting margins and prevention of unnecessary stress on cells compared to conventional technology. .

〔Effect of the invention〕

As explained above, the present invention detects the write/erase state of the actual cell and terminates the erase/write, taking into consideration the margin with the actual cell performance, unlike the conventional example using a timer circuit. This is not necessary at all, and the effect is that the reliability of erasing and writing completion is extremely high.

Furthermore, since the time when erasing and writing to the cell actually ends coincides with the time when erasing and writing are completed as seen from the outside, no unnecessary stress is applied to the cell, which has the effect of lengthening the life of the cell.

Furthermore, when the erasing time and writing time are different, when setting the time using a timer circuit, pulses with two different pulse widths must be created, which complicates the circuit. However, in the present invention, there is no need to take this point into consideration. Not at all.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
FIG. 3 is a circuit diagram of the second embodiment of the present invention, and FIG. 4 is a waveform diagram of each signal in FIG. 2. 1... Memorial array, 2.2A... Control circuit, 3.3A... Rewriting completion detection circuit, 4.
... sense amplifier, 5 ... data latch circuit, 6 ... D flip-flop, 7 ...
...Dummy cell, 8...RSS flip flow rough, 11...Memory cell I Go~GIG...
...Gate circuit. Agent Patent Attorney Uchihara Oto r'""-7"7゛'"'= Door: 1 calculation 4 koku

Claims (1)

[Claims] A memory cell that is electrically programmable and erasable, and a clock signal that erases and erases the memory cell during an erase cycle.
a control circuit that alternately repeats reading, and performs writing and reading alternately during a write cycle after completion of erasure; and a control circuit that performs data read from the memory cell during the erase cycle when the data reaches an erase level. It is characterized by comprising a rewrite end detection circuit that outputs an erase end signal to notify a circuit of the end of erasure, and outputs a rewrite end signal when data read from the memory cell during the write cycle reaches a write data level. An electrically programmable and erasable nonvolatile semiconductor memory device.