JPH02308332A - Information processor - Google Patents

Abstract

PURPOSE:To use the locality of time and space of memory reference to quickly access the memory by providing a data unit with a stock means and providing a data cache with a transfer means. CONSTITUTION:A data unit 101 is provided with a stock means 101a where plural data are stocked, and a data cache 103 is provided with a transfer means 103a which simultaneously transfers data in a memory address N requested by the data unit 101 and data in a memory address N+1 to the data unit 101. Consequently, data having a high reference probability in the data cache 103 is preliminarily transferred to the data unit 101 and requested data is compared with data in the data unit 101, and memory access is unnecessary when they coincide with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that performs parallel processing of information.

[Conventional technology]

Conventionally, there has been an information processing apparatus of this type as shown in FIG. This second figure was created by Carl Dobbs+P.
Written by aul Reed and Tommy Ng:
Supercomputing Chip, VIS
r SVSTEMS DESIGN Vol, IX, N
o, 5. It is based on the configuration shown in May 1988, pp. 24-33, and in the figure, 201 is an integer unit that performs integer operations and logical operations, 202 is a floating point unit that performs floating point operations, and 203 is a data cache and register file. 204 is a register file that stores information necessary for the above operations; 205 is a data unit that performs data read or write processing;
is a scoreboard that detects and avoids register conflicts, 20
6 is an instruction fetch unit that fetches and decodes instructions and transfers data to each of the above units; 207 is an internal bus; 208 is an address bus that exchanges instruction addresses between the data unit 203 and the data cache 210; and 209 is a data This is a data bus for exchanging data between the unit 203 and the data cache 210.

Next, the operation will be explained. Instruction fetch unit 20
6 is pipelined into three stages: instruction fetch, decode, and transfer, and after completing the fetch in one clock, the instruction is passed to the decode stage. In the decoding stage, the instruction is partially decoded and a register request is issued to the scoreboard 205 in order to prefetch the operands necessary for the operation from the register file 204 to the functional unit corresponding to the instruction. Each register in register file 204 has a scoreboard bit that is set when the register is stalled and cleared when the data operation is complete. The scoreboard 205 receives the register request from the instruction fetch unit 206 and rotates the scoreboard bits eight times.
The instruction fetch unit 206 only when it is in the clear state.
sends a signal of availability to. Instruction fetch unit 20 receives an available signal from scoreboard 205
6 transfers the instruction to the corresponding functional unit and simultaneously fetches the instruction. Each functional unit also has several vibe line stages and executes instructions using prefetched operands.

The data unit 203 is also one functional unit, and 3
pipelined into two stages. stage 1
Now, the receiver calculates the memory address of the attached instruction,
Pass the calculation results to the next stage. In stage 2, the address bus 208 is driven based on the sent address. If the sent instruction is a store instruction, the data to be stored at this stage is fetched from the register file 204 and the address is placed on the address bus 208 and the data is placed on the data bus 209. In stage 3, the response of the data cache 210 is monitored.

In the case of a load instruction, the data bus 209 is read at this stage and data is taken in.

[Problem to be solved by the invention]

Since conventional information processing devices are configured as described above, the data unit must perform memory access for each individual load instruction, which requires a lot of processing time no matter how much the calculation performance improves. The problem was that processing performance did not improve as expected if there was a lot of data exchanged with the outside world.

This invention was made in order to solve the above-mentioned problems, and provides an information processing device that can perform high-speed memory access by utilizing the temporal and spatial locality of memory references. With the goal.

[Means to solve the problem]

The information processing device according to the present invention includes a data unit 101
Stocking means 101a for stocking a plurality of pieces of data in
is provided, and the data cache 103 has data unit 1.
Assuming that the memory address of the data requested from 01 is N, the transfer means 1 simultaneously transfers the requested data at address N and the data at address (N+1) to the data unit 101.
03a is provided.

[Effect]

The stock means 101a of the data unit 101 stocks a plurality of pieces of data. The transfer means 103a of the data cache 103 simultaneously transfers the data at address N and the data at address (N+1) requested from the data unit 101 to the data unit 101.

[Embodiments of the invention]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. Components corresponding to those shown in FIG. 2 are given the same reference numerals, and their explanations will be omitted.

In FIG. 1, 101 is a data unit having stock means 101a for stocking a plurality of data;
3, when the memory address of the data requested from the data unit 101 is N, the requested data at address N and the data at address (N+1) are simultaneously stored in the data unit 101.
This is a data cache having a transfer means 103a for transferring data to. Further, 102 is a data bus for exchanging data between the data cache 103 and the data unit 101.

Next, the operation will be explained. The data unit 101 is
Like the conventional device, it is divided into three pipeline stages, and when a memory access command is received, a memory address is calculated in the first stage. Let N be the memory address calculated in the first stage. If the accepted instruction is a store instruction, the instruction is passed to the second stage after the calculation similar to the conventional device is completed. If the accepted instruction is a load instruction, the calculated memory address N is compared with the address of the data stored in the stock means 101a in the data unit 101. If there is a match as a result of the comparison, data corresponding to the matched address is written to the register file 204 without performing memory access. If there is no match, the instruction is passed to the second stage to perform the memory access. In the second stage, address bus 208 and data bus 102 are driven,
The data cache 103 is informed of the memory address N of the data required to execute the instruction, and the instruction is passed to the third stage. The data cache 103, which has received the memory address N from the data unit 101, transfers the requested data at address N and data at address (N+1) to two data buses 10.
2 is simultaneously transferred to the data unit 101 by the transfer means 103a. In the third stage, out of the two data sent from the data cache 103, the data necessary for executing the instruction is written to the register file 204, and at the same time, the two data are sent to the data unit 103.
Replace the data within. The data stored here will be referenced at the time of the next load instruction.

In this way, data with a high reference probability is transferred in advance to the data unit 101 in the data cache 103, and the address of the requested data in the data unit ioi is compared with the address of the data in the data unit 101. If they match, there is no need to perform memory access, and only if they do not match, memory access is performed, so the overall time required for memory access can be reduced.

〔Effect of the invention〕

As described above, according to the present invention, the data unit is provided with a stock means for stocking a plurality of pieces of data, and the data cache simultaneously stores the data at address N and the data at address (N+1) requested from the data unit. For example, data with a high reference probability can be transferred to the data unit in advance in the data cache, and the requested data in the data unit can be compared with the data in the data unit. If both match, there is no need to perform memory access, and the overall number of memory accesses is reduced.Therefore, the time required for memory access can be shortened, and the data processing speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main part configuration of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a professional diagram showing the main part structure of a conventional information processing apparatus. 101...7'-ta:l-nit, 101a...Stock means, 103...Data cache, 103a
... Transfer means, 201 ... Integer unit, 202.
...Floating point unit, 204...Register file, 206...Instruction fetch unit.

Claims (1)

[Claims] Data is transferred between an integer unit that performs integer operations and logical operations, a floating point unit that performs floating point operations, a register file that stores information necessary for the above operations, and a data cache that stores data and this register file. In an information processing device, the information processing device includes a data unit that performs read and write processing, and an instruction fetch unit that pipelines each stage of instruction fetch, decoding, and data transfer to each of the above components. A stock means for storing a plurality of pieces of data is provided, and when the memory address of the data requested from the data unit is N, the data at the requested address N and the data at address (N+1) are simultaneously stored in the data cache. An information processing device comprising a transfer means for transferring data to the data unit.