JPH031232A - Information processor - Google Patents

Abstract

PURPOSE:To accelerate processing speed by fetching instructions with two instruction fetching units simultaneously at a processing part, and processing them in parallel or sequentially according to priority. CONSTITUTION:The processing part 103 fetches the instruction at an N-th address and an (N+1)th address transferred from an instruction cache 104 simultaneously with the instruction fetching units 101 and 102, and processes those instructions in parallel or sequentially. The instruction cache 104 transfers the instructions at the N-th address and the (N+1)th address to the processing part 103 simultaneously. Thereby, it is possible to obtain an information processor capable of efficiently fetching the instruction, and accelerating the processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that processes information in parallel.

[Conventional technology]

Conventionally, there has been a device of this type as shown in FIG. This second figure was created by Carl Dobbs, Paul
Written by Reed and Tommy Ng: Superc
Computing on Chip.

VLSI SYSTEMS DESIGN Vol.
IX, No, 5. May 1988. pp24-33
In the figure, 201 is an integer unit that performs integer operations, logical operations, etc., 202 is a floating point unit that performs floating point operations, etc., and 203 is a floating point unit that performs floating point operations.
204 is a data unit that performs data read or write processing between memory (instruction cache) and register file; 204 is a register file that stores information necessary for the above operations; 205 is a scoreboard that detects and avoids register conflicts; 206 is an instruction fetch unit that fetches and decodes instructions and transfers data to functional units; 207 is an internal bus; 208 is an address bus that exchanges memory addresses of instructions between the instruction fetch unit 206 and the instruction cache 210; This is a data bus for exchanging instructions between the instruction fetch unit 206 and the instruction cache 210.

Next, the operation will be explained. Instruction fetch unit 20
6 is pipelined into three stages: instruction fetch, decoding, and transfer, and the memory address of the next instruction to be executed is sent to the instruction cache 2 using the address bus 208.
The instruction cache 210 that has received the memory address passes the instruction corresponding to the memory address to the instruction fetch unit 206 using the data bus 209.

After the instruction fetch unit 206 completes the fetch in one clock, it passes the instruction to the decoding stage.

In the decoding stage, the instruction is partially decoded and a register request is issued to the scoreboard 205 in order to cause the functional unit corresponding to the instruction to pre-fetch the operands required for the operation from the register file 204. Register file 2
Each register in 04 has a scoreboard bit that is set when the register is stalled and cleared when the data operation is complete. After receiving the register request from the instruction fetch unit 206, the scoreboard 205
The bit is checked and only if it is in the clear state is it sent an available signal to the instruction fetch unit 206. It has an instruction fetch unit 206 pipeline stage that receives an available signal from the scoreboard 205 and executes the instruction using the pre-fetched operands.

[Problem to be solved by the invention]

Since the conventional 7-line table processing device is configured as described above, the instruction fetch unit can decode only one instruction in one crofter, so it decodes at most one instruction in one clock.
The problem was that only one calculation result could be obtained, and the processing speed could not be improved any further.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide an information processing device that can efficiently fetch instructions and improve processing speed.

[Means to solve the problem]

The information processing device according to the present invention includes two instruction fetch units 101 and 102 that fetch instructions simultaneously, and a processing unit 103 that performs processing in parallel or sequentially according to the priority between these instruction fetch units 101 and 102; The device is characterized by comprising an instruction cache 104 having a function of receiving the memory address N of the instruction to be executed by the processing unit 103 and simultaneously transferring the instruction at address N and the instruction at address (N+1) to the processing unit 103. It is.

[Effect]

The processing unit 103 includes instruction fetch units 101 and 102.
The instruction at address N and the instruction at address (N+1) transferred from the instruction cache 104 are fetched simultaneously, and these instructions are processed in parallel or sequentially according to their priorities. The instruction cache 104 stores the instruction at address N and (N+
1) Transfer the instructions at the address to the processing unit 103 at the same time.

[Embodiments of the invention]

FIG. 1 is a block diagram showing the main part configuration of an information processing apparatus according to the present invention. In the figure, 103 is two instruction fetch units 101 and 10 that fetch instructions simultaneously.
2 between these instruction fetch units 101, 10
This is a processing unit that performs processing in parallel or sequentially according to the priority between the two. The instruction fetch unit 101 always processes the instruction at address N (N=0.1...) regardless of whether the instruction address is even or odd, and the instruction fetch unit 102 always processes the instruction at address (N+1). process instructions. An instruction cache 104 has a function of receiving the memory address N of the instruction to be executed by the processing unit 103 and simultaneously transferring the instruction at address N and the instruction at address (N+1) to the processing unit 103.

105 is, for example, a 32-bit data bus through which the instruction cache 104 simultaneously transfers the instruction at address N and the instruction at address (N+1) requested by the processing unit 103. An address bus 208 is used by the processing unit 103 to specify an address in the instruction cache 104.

Next, the operation will be explained. The processing unit 103 determines that the memory address N of the next instruction to be executed is the instruction fetch unit 1.
01 or as determined by the instruction 102,
The memory address N is notified to the instruction cache 104 using the address bus 208. The instruction cache 104 receives the memory address N of the instruction, compares the memory addresses in the instruction cache 104, and if there is a match, the instruction at the N address and the instruction at the (N+1) address are simultaneously transferred to the two data buses 105. is used to transfer the data to the processing unit 103. If there is no matching memory address, the main memory (not shown) is accessed. The processing unit 103 sends the instruction at address N of the two instructions sent from the instruction cache 104 to the instruction fetch unit 101 at (N+
1) The instruction at the address is fetched by the instruction fetch unit 102, and the two instructions are executed in parallel or sequentially according to the priority between the instruction fetch units.

[Effects of the Invention] As described above, according to the present invention, the instruction at address N and the instruction at address (N+1) are simultaneously transferred in response to the memory address N requested by the processing unit in the instruction cache, and Since the two instruction fetch units are configured to fetch instructions simultaneously and process them in parallel or sequentially according to the priority, instructions can be efficiently fetched (fetched) regardless of whether the address of the instruction is an even number or an odd number. , Therefore, the effect of improving the processing speed can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part structure of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the main part structure of a conventional information processing apparatus.

Claims (1)

[Claims] In an information processing device that processes multiple instructions in parallel, there is provided a processing unit that has two instruction fetch units that fetch instructions simultaneously and performs processing in parallel or sequentially according to priorities between these instruction fetch units; Receives the memory address N of the instruction to be executed in the N
An information processing device comprising an instruction cache having a function of simultaneously transferring an instruction at an address and an instruction at an address (N+1) to a processing unit.