JPH02304936A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the breakdown strength of a MOS transistor by forming a source/drain diffusion layer in low concentration at the end section of a selective oxide film and shaping a source/drain diffusion layer in concentration higher than the source/drain diffusion layer by utilizing the end section of an oxidation-resistant film. CONSTITUTION:An oxide film 2 is formed onto a P-type silicon substrate 1 and a nitride film 3 onto the oxide film 2, the nitride film 3 is left only in a region, in which a gate is shaped, to form a nitride film pattern 3a, a resist pattern 4 is shaped around the pattern 3a, and an offset layer 5 is formed. The resist pattern 4 is removed, and an oxide film 6 is shaped onto the oxide film 2 through heat treatment while an offset diffusion layer 5a is formed simultaneously. A resist pattern 7 is shaped onto the oxide film 6, an N<+> forming pattern 6a is formed through a dry etching technique, and an impurity in concentration higher than the first diffusion layer 5a is diffused to form a second diffusion layer 8. Consequently, the second diffusion layer in high concentration as a source/drain diffusion layer is covered with the first diffusion layer in low concentration. Accordingly, the breakdown strength of a MOS transistor is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device that allows the drain layer of a MOS transistor having an offset structure used in a high voltage IC to be manufactured with precision. be.

(Prior art) Conventionally, an offset type MOS transistor was disclosed in Japanese Patent Application Laid-Open No.
There are those disclosed in Japanese Patent Application Laid-open No. 171165 and Japanese Patent Application Laid-Open No. 61-239667, which have a structure that has high voltage resistance, high signal chain properties, and is suitable for microfabrication.

Figures 3(a) to 3(d) are from the above-mentioned JP-A-61-1
"rMO3) transistor disclosed in Publication No. 71165"
FIG. 3 is a process cross-sectional view of a conventional semiconductor device manufacturing method corresponding to FIG.

A conventional method for manufacturing a semiconductor device will be explained with reference to FIGS. 3(a) to 3(a).

First, as shown in FIG. 3(a), a P-type semiconductor substrate 41
The source, gate, and drain forming regions are covered with an oxidation-resistant film 41.
This oxidation-resistant film 41a is patterned, and N-type impurity ions are implanted using this oxidation-resistant film 41a as a mask to form offset layers 42.42a.

Next, as shown in FIG. 3 (bl), selective oxidation is performed to form selective oxide films 43 and 43a.

At this time, the offset layer 42a formed under a part of the selective oxide film 43a becomes a drift region, and the rest of the offset layer 42 becomes a region that contributes to improving the breakdown voltage.

Next, as shown in FIG. 3(c), the offset 142
After forming a gate oxide film 44 and a gate electrode pattern 45 on the P-type semiconductor substrate 41 between them, ions of N-type impurity are implanted using the selective oxide film 43.43a as a mask.
The source/drain diffusion layer 46 is offset by the offset layers 42 and 42.
Form between a.

Next, as shown in 3rd rM(d), after forming the intermediate insulating film 47, a contact hole is formed in this intermediate insulating film 47, and a wiring metal pattern 48 is formed in this contact hole. A type MOS transistor is formed.

Note that FIG. 4 is a cross-sectional view of a conventional P-channel type MoS transistor, and in this FIG.
- Only the same reference numerals are given to the parts corresponding to those in FIG. 3(d).

(Problem to be Solved by the Invention) In the semiconductor device manufactured in this way, the breakdown voltage of the MOS transistor is determined at the bottom surface of the source/drain diffusion layer 46, and its value is determined by the concentration of the P-type semiconductor substrate 41. Depends on.

Therefore, there is a problem that the breakdown voltage cannot be increased at the same substrate concentration.

In addition, in order to increase the withstand voltage, the substrate concentration at the bottom of the drain,
Alternatively, if the concentration of the drain diffusion layer is changed, a step of forming a new diffusion layer is added, which makes the process unsatisfactory in terms of cost and yield.

This invention solves the problems of the above-mentioned prior art, such as the inability to increase the withstand voltage of a MOS transistor with the same substrate concentration, and the problem in terms of cost and yield in order to increase the withstand voltage. A method for manufacturing a semiconductor device is provided.

(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device in which a first diffusion layer is formed around a predetermined distance from an oxidation-resistant film that remains only in a portion that will become a gate via an oxide film. A step of forming the oxidation-resistant film on a semiconductor substrate, selectively oxidizing the portion from which this oxidation-resistant film has been removed, and removing the portion covering the first diffusion layer from the edge of the oxidation-resistant film to form a layer with a higher concentration than the first diffusion layer. This method introduces a step of diffusing impurities.

(Function) The present invention provides a semiconductor device manufacturing method in which a highly doped second diffusion layer serving as a source/drain diffusion layer is covered with a lightly doped first diffusion layer, thereby improving the withstand voltage of a MOS transistor. Therefore, the above-mentioned problem can be eliminated.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1(a) to Figure 1(
B) is a process sectional view of one embodiment.

First, as shown in Figure 1 (al), the resistivity is 1~2Ω・c
P-type silicon substrate 1 (first conductivity type semiconductor) of 100
Processing is carried out in an oxygen atmosphere for about 30 minutes at 0''C to form about 500 oxides wA2.

Next, a nitride film 3 having a thickness of tooλ to 20f)Oλ is formed as an oxidation-resistant film by a known CVD technique.

Next, as shown in FIG. 1b), by using known photolithography and etching techniques, the nitride film 3 is left only in the region where the gate will be formed, and the nitride film 3 in other parts is removed.
A nitride film pattern 3a is formed.

Next, the 1st I! As shown in I(c), a resist pattern 4 is formed around the nitride film pattern 3a using a known photolithography technique, and using the nitride film pattern 3a and the resist pattern 4 as a mask, a known ion implantation technique is used to form a resist pattern 4. The offset layer 5 is formed by implanting an N-type impurity (for example, phosphorus) of 10 to 10'' tons/cd into the region on the P-type silicon substrate 1 where the offset is to be formed.

Next, as shown in FIG. 1(d), after removing the resist pattern 4, it was heated at 1000°0400 in a steam atmosphere.
By heat treatment for about 1 minute, a selective oxide film with a thickness of 1.
Oxidize the oxide film 6 of about 5n! It is integrally formed on 2.

At this time, the end of the nitride film pattern 3a becomes a canopy as shown in the figure. That is, Bird's Beak 3b
form.

Moreover, at this time, the offset layer 5 shown in FIG. 1(c)
is diffused to a depth of 1 to 2−, and the offset diffusion N5a
is formed.

Next, as shown in FIG. 1(e), a source/drain layer forming resist pattern 7 is formed on the oxide film 6 at a certain distance from the nitride film pattern 3a using a known photolithography technique, and CF, SF4 Using the nitride film pattern 3a and the source/drain layer forming resist pattern 7 as a mask, the oxide film 6 is anisotropically etched using a dry etching technique using a method such as the like, to form a N' formation pattern 6a.

Next, as shown in FIG. 1(f), an N of 10" to 10" tons/e+j is deposited by a known ion implantation technique.
Implant mold impurities (e.g. arsenic) and heat at 1000°C3
A heat treatment is performed for about 0 minutes to form source/drain diffusion layers 8.

At this time, the junction depth of the source/drain diffusion layer 8 is 0.
5μ, the junction depth of the offset diffusion layer 5a is 1 to 2μ, and the source/drain diffusion layer 8 is completely formed within the offset diffusion layer 5a.

Next, the source/drain layer forming resist pattern 7 is removed, and the nitride film pattern 3a is removed, as shown in FIG. It is formed at the location where the nitride film pattern 3a was removed.

Next, as shown in FIG. 1 (5), after forming the intermediate insulating film 10, a contact hole is formed in the intermediate insulating film IO, and then Aj wiring 11 is formed by vapor deposition and patterning of a wiring metal such as AI. and offset type MO3)
A transistor is formed.

Here, the numerical conditions described in the above embodiments are merely examples, and can be changed depending on the design of the transistor.

Furthermore, if the constituent materials are selected so that the conductivity types of the channels are reversed, it can also be applied to a P-channel type MO3) transistor. FIG. 2 is a sectional view of this P-channel type MO3I-transistor, and the same parts as in FIG. 1 (5) are given the same reference numerals. Note that 12 is a gate electrode.

Furthermore, by forming a well layer having a conductivity type opposite to that of the semiconductor substrate in the semiconductor substrate, the present invention can also be applied to a complementary MOS transistor (cMO3).

(Effects of the Invention) As described in detail above, according to the present invention, a low concentration source/drain diffusion layer is formed at the edge of the selective oxide film, and the source/drain diffusion layer is formed using the edge of the oxidation-resistant film. Since the source/drain diffusion layer is formed with a higher concentration than the drain diffusion layer, when the same substrate concentration is used, the high concentration source/drain diffusion layer is all covered by the low concentration source/drain diffusion layer. As a result, the withstand voltage is improved. For example, when using a 10'"cll-" N-type substrate,
A breakdown voltage of approximately 20V is expected.

Further, since the offset length of the low concentration source/drain diffusion layer can be determined by the thickness of the thick oxide film, the offset length is not affected by the mask alignment accuracy of photolithography technology.

[Brief explanation of the drawing]

1(a) to 1(c) are process cross-sectional views of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a P-channel type M obtained by the method for manufacturing a semiconductor device of the present invention.
O3) A cross-sectional view of a transistor, FIGS. 3(a) to 3(d) are process cross-sectional views of a conventional semiconductor device manufacturing method, and FIG. 4 is a P channel obtained by a conventional semiconductor device manufacturing method. FIG. 2 is a cross-sectional view of a type MOS transistor. 1... P-type silicon substrate, 2, 6... oxide film, 3.
...Nitride film, 3a...Nitride film pattern, 5a...Low concentration source/drain diffusion layer, 8...High concentration source/drain diffusion layer, 9...Gate polysilicon pattern. FIG. 2 is a cross-sectional view of a P-channel MOS transistor according to the present invention 1.

Claims (1)

[Claims] (a) A step of sequentially forming an oxide film and an oxidation-resistant film on a first conductivity type diffusion layer formed on a first conductivity type semiconductor substrate or a second conductivity type semiconductor substrate; , (b) leaving the oxidation-resistant film only in the portion that will become the gate region, and (c) introducing a second conductivity type impurity around a certain distance of the remaining oxidation-resistant film to form the first a step of forming a diffusion layer; a step of selectively oxidizing the portion from which the oxidation-resistant film has been removed to form a selective oxide film; (f) removing a part of the oxidation-resistant film from the edge of the oxidation-resistant film in a certain range; A method for manufacturing a semiconductor device, comprising: a step of introducing a conductivity type impurity; and a method for manufacturing a semiconductor device.