JPH02304922A - Forming method of fine pattern - Google Patents

Abstract

PURPOSE:To prevent the generation of a crack in a first resist and the peeling of a second resist by silylating the first resist and forming the second resist onto the silylated layer. CONSTITUTION:First-layer wiring metals 3 are shaped onto the insulating film 2 of a semiconductor substrate 1 according to required pattern, and a second- layer wiring metal 5 is formed onto an irregular inter-layer insulating film 4 shaped onto the metals 3. A first resist 6 is formed onto the wiring metal 5, the whole surface of the substrate is exposed by ultraviolet rays, and the first resist 6 is silylated through heating for a proper time in an HMDS atmosphere and a silylated layer 7 is shaped. A second resist 8 is applied, and a pattern corresponding to a second layer wiring is formed through exposure and development. The second resist 8, the silylated layer 7 and the first resist 6 are etched successively. Accordingly, defective phenomena such as the cracks of the first resist 6, the peeling of the second resist 8, etc., can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a fine pattern using a multilayer resist.

[Conventional technology]

Conventionally, a three-layer resist method has been used to form fine patterns on a substrate with a stepped base to achieve patterning with high dimensional accuracy.

For example, FIG. 2 is a cross-sectional view showing one example.

That is, the first
After forming a layer wiring metal 13 and covering it with a glabella insulating film 14, a second layer wiring metal 15 which is a material to be etched is formed.
form. Then, a first resist 16 is applied on top of this to make the surface flat, and SOC (spin resist) is applied on top of this.
Coat 17 (on glass) to a thickness of about 1,000 coats and bake. Further, a second resist 18 is applied thereon, and conventional exposure and development are performed to form a pattern mask.

Then, using this second resist 18 as a mask, CF,
Reactive ion etching method (RIE) using gases such as
), and then using 5OG17 as a mask, the first resist 16 is etched by RIE with 0□.

Using the pattern thus obtained as a mask, the second N wiring metal 15 is etched to obtain a desired second layer wiring pattern.

According to this method, since the step formed on the semiconductor substrate is flattened by the first resist 16, the second resist 18 can be formed to have a uniform thickness. Regardless, a pattern with uniform dimensions can be obtained.

In addition, the second resist 18 is a thin 5O film with a thickness of about 100 mm.
Since this is a mask for etching G17, it can be made thinner and the resolution can be improved.

[Problem to be solved by the invention]

In the conventional disintegration method described above, in addition to the process becoming long, as shown in FIG.
17 is repelled, and a crack occurs in the first resist 16 when the 5OG 17 is fired.

Furthermore, the adhesion between the 30G17 and the second resist 18 deteriorates, and peeling tends to occur during firing.

If these cracks or peelings occur, it becomes impossible to etch the 5OG 17 or the first resist 16 into the desired pattern, and therefore, the problem arises that it becomes impossible to form the second layer wiring metal 15 into the desired fine pattern. .

An object of the present invention is to provide a method for forming a fine pattern that prevents cracks in the first resist and peeling of the second resist, and makes it possible to form a second layer wiring metal into a desired fine pattern. do.

[Means to solve the problem]

The method for forming a fine pattern of the present invention includes a step of forming a first resist on a material to be etched formed on a semiconductor substrate, and a step of silylating the surface of the first resist to form a silylated layer. A step of forming a second resist on the silylated layer, a step of forming the second resist into a desired pattern and etching the silylated layer using this as a mask, and a step of etching the etched silylated layer. The method includes a step of etching the first resist using a mask, and a step of etching the material to be etched using the etched first resist as a mask.

[Effect]

In this formation method, a first resist is silylated to form a silylated layer, and a second resist is formed on this silylated layer, thereby eliminating the need for the step of baking the soG. This prevents the occurrence of cracks in the second resist and peeling of the second resist, and enables good etching.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1(a), the first layer wiring metal 3 is formed in a desired pattern on the insulating film 2 on the surface of the semiconductor substrate 1. Further, a glabellar insulating film 4 is formed thereon, and a second layer wiring metal 5 constituting a second layer wiring is formed on this glabellar insulating film 4 having an uneven shape.

Next, as shown in FIG. 1(b), a first resist 6 is formed thereon. For this resist, Plasma Suff, a product manufactured by JSR Corporation, is used.

Next, as shown in Figure 1(c), the entire surface of the substrate is exposed to ultraviolet light and heated to 150°C for an appropriate time in an HMDS atmosphere to silylate from the surface to a depth of approximately 1000 nm. A silylated layer 7 is formed.

Next, as shown in FIG. 1(d), for example, Tokyo Ohka Chemical's P F P R800 is coated as the second resist 8, and exposed and developed by a normal method to form a pattern corresponding to the second layer wiring. Form.

Then, as shown in FIG. 1(e), the silylated layer 7 is etched by RIE using CFa using the second resist 8 as a mask.

Furthermore, as shown in FIG. 1Cf), using the silylated layer 7 as a mask, the first resist 6 is coated with non-silylated Rr (tJ=02).
Etching by E.

Using the thus obtained pattern as a mask, the second layer wiring metal 5, which is the material to be etched, is etched.

According to this formation method, it is possible to form the second layer wiring metal 5 into a desired fine pattern regardless of the surface irregularities of the first layer wiring metal 3 and the interlayer insulating film 4, similar to the conventional three-layer resist. becomes. Here, since the second resist 8 is formed after forming the silylated layer 7 on the surface of the first resist 6, the baking process when using SOG is unnecessary, and the number of processes can be reduced. At the same time, generation of cracks in the first resist 6 and peeling of the second resist 8 can be prevented, and the formation of fine patterns is promoted.

Note that an electron beam drawing resist is used as the second resist,
By performing patterning by EB exposure, it is possible to form fine patterns with high precision even using an EB resist with low dry etching resistance.

〔Effect of the invention〕

As explained above, in the present invention, a silylated layer is formed on the surface of a first resist to form a second resist, and the second resist, the silylated layer, and the first resist are sequentially etched to cover the surface. Since we are etching the etching material,
Similar to the conventional three-layer resist method, pattern formation with high dimensional accuracy is realized even on a substrate with steps. Moreover,
Since the process of applying and baking SoG is eliminated, defects such as cranking of the first resist and peeling of the second resist, which are caused by this process, can be prevented, and a stable fine pattern can be formed. .

[Brief explanation of drawings]

FIGS. 1(a) to 1(h) are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps, and FIG. 2 is a cross-sectional view for explaining a conventional manufacturing method and its problems. 1.11... Semiconductor substrate, 2.12... Insulating film, 3
．． 13... First layer wiring metal, 4, 14... Interlayer insulating film, 5, 15... Second layer wiring metal, 6.16... First resist, 7... Silylated layer , 8.18...Second resist, 17...5OC0 Fig. 1 Fig. 1

Claims (1)

[Claims] 1. A step of forming a first resist on a material to be etched formed on a semiconductor substrate, a step of silylating the surface of this first resist to form a silylated layer, and a step of forming a second resist on this silylated layer. forming a desired pattern with this second resist and etching the silylated layer using this as a mask; and etching the first resist using the etched silylated layer as a mask. A method for forming a fine pattern, comprising the steps of: etching; and etching the material to be etched using an etched first resist as a mask.