JPH02304797A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a data reading time at the time of chip select access by setting either one of output data from a differential amplifier circuit or an output buffer circuit to an intermediate level at least according to a chip select change detecting signal, a sense amplifier activating signal and a data equalize signal. CONSTITUTION:A chip select change detecting signal CTD is inputted at least to either one of a differential amplifier circuit 1 and a prebuffer output circuit 11 and a sense amplifier activating signal SE operates the differential amplifier circuit 1 even during the period of an L level. Simultaneously, the output data of the differential amplifier circuit 1 and an inverter circuit 2 are set to the intermediate level. Accordingly, even when the sense amplifier activating signal SE is generated later than a data equalize signal ATD, either on of the differential amplifier circuit 1 and an output buffer 12 at least can be avoided from an inactive state just after reading is started. Thus, an access time can be made speedy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that can speed up access time during chip select access.

[Conventional technology]

FIG. 4 shows a circuit configuration diagram of an output system of a conventional semiconductor memory device. In the figure, reference numeral 1 denotes a differential amplifier circuit that receives data A and W output from a memory cell array (not shown) divided into blocks. 2 is output data φ from the differential amplifier circuit 1.

It is an inverter circuit that inputs data φ.

The inverted data φ1 of is output to the data bus 5. Reference numeral 10 denotes an inverter circuit and an AND circuit which receive the chip select signal C and the block select signal BS, and output the sense amplifier activation signal SE to the differential amplifier circuit 1 and the gate of the N-channel MO3I transistor 4.

3.4 is data φ while the differential amplifier circuit 1 is operating.

and N-channel MO3 to bring φ1 to intermediate level.
) is a transistor. 6 and 7 are inverter circuits which input the data φl on the data bus 5, and invert the inverted data φ2 . φ3 is input to the gates of P-channel MO3) transistor 8 and N-channel MO3) transistor 9. 13 is output data D. This is a data output terminal for outputting UA. 11 is the above inverter circuit 2
．． 6゜7 and N-channel MO3) are pre-output buffers including transistors 3 and 4, and 12 is a P-channel MO3) transistor.
This is an output buffer including transistor 8 and N-channel MO3I transistor 9.

The operation of the conventional circuit configured as described above will be explained with reference to FIG. At the time of chip select access when the state of the chip select signal C changes and reading from the semiconductor memory device starts, the block select signal BS of the memory cell array having the memory cell having the information to be read goes to H level, and the chip select signal a goes to L level. When this happens, information A and X are output from the memory cell. At this time, sense amplifier activation signal SE changes to H level, differential amplifier circuit 1 is activated, and N-channel MOS transistor 4 is turned on. During chip select access, data equalize signal ATD changes from H level to L level after the start of reading, so a period in which both data equalize signal ATD and sense amplifier activation signal SE are at H level occurs.

During this period, the output data φ of the differential amplifier circuit 1.

is equalized to an intermediate level, and since the N-channel MOS transistor 3.4 is turned on, the output φ1 of the inverter circuit 2 also becomes an intermediate level.

When the data equalize signal ATD changes to L level, the data φ. The level starts to change from the intermediate level, and at the same time, N-channel MO3I-transistor 3 turns OFF, so
The level of data φ also begins to change from the intermediate level. Thereafter, data φ1 is input to two inverter circuits 6 and 7, and data φ2° and φ3 are output. This data φ2
．． P channel MOS transistor 8 depending on the level of φ3
and N-channel MO3) ON or OFF of transistor 9 is determined, and finally data D. LIT is data output terminal 1
3 is output.

[Problem to be solved by the invention]

It is also used to control the operation of circuits around memory cells. For this reason, the capacitance of the signal wiring for the chip select signal 6 increases, and the delay in the chip select signal C due to the capacitance becomes noticeable as the speed of semiconductor storage devices increases.
The rising edge of the sense amplifier activation signal SE, which is the logical product of the two signals, is delayed with respect to the falling edge of the data equalization signal ATD.

As a result, there is a problem in that a period in which no data is output from the differential amplifier circuit 1 occurs, resulting in a delay in output data.

FIG. 6 shows this state. When the sense amplifier activation signal SE becomes H level after the data equalize signal ATD becomes L level, the data equalize signal ATD
A period T occurs in which both the signal and the sense amplifier activation signal SE are at L level, and during this period, the data φ. , φ1 are no longer output, and the output data D. The time required to output LIT becomes longer.

The present invention has been made to solve the problems of the conventional devices as described above, and an object of the present invention is to provide a semiconductor memory device that can shorten data read time during chip select access.

[Means to solve the problem]

The circuit of the output system of the semiconductor memory device according to the present invention has a differential amplifier circuit and an output buffer circuit (both output data of one of them are transmitted to a chip select change detection signal CTD, a sense amplifier activation signal SE, and a data equalize signal AT).
It is configured so that D is set to an intermediate level.

[Operation] The semiconductor memory device according to the present invention inputs the chip select change detection signal CTD to at least one of the differential amplifier circuit and the pre-buffer output circuit, thereby maintaining the difference even during the period when the sense amplifier activation signal SE is at L level. Since the dynamic amplifier circuit is operated and the output data of the differential amplifier circuit and the inverter circuit 2 are set to an intermediate level at the same time, chip selection can be performed when the sense amplifier activation signal SE is delayed with respect to the data equalization signal ATD. We aim to speed up the access time when accessing.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

- FIG. 1 is a circuit diagram of an output system of a static semiconductor memory device according to an embodiment of the present invention. In this figure, the same reference numerals as in FIG. 4 indicate the same parts. 14 is an N-channel MOS transistor that is controlled by a chip select change detection signal CTD that senses that the chip select signal a changes from H level to L level, and is an N channel MOS transistor that is controlled by a sense amplifier activation signal SE. 4 are connected in parallel.

Further, FIG. 2 shows an example of the configuration of the differential amplifier circuit l shown in FIG. 1, in which reference numerals 15 and 16 are P-channel MOS transistors, and 17 to 21 are N-channel MOS transistors.

As shown in FIG. 2, the chip select change detection signal CTD is applied to the gate of an N-channel MOS transistor 21 connected in parallel to an N-channel MOS transistor 20 controlled by a sense amplifier activation signal SE. input.

Next, the operation of the above embodiment will be explained with reference to FIG. When the chip select signal a changes to L level and the block select signal BS of the memory cell array having memory cells with continuous information changes to H level, the static semiconductor memory device enters the read state and data A, λ are read from the memory cells. is input to the dynamic amplifier circuit 1. At the same time, the chip select change detection signal CTD shown in FIG. 3 becomes H level, turning on the N-channel MOS transistor 14 shown in FIG. Activate. At the time of chip select access, the data equalization signal ATD is at H level before data A and λ are input to the differential amplifier circuit 1, so the N-channel MO3) transistors 3 and 19 are already turned on, as shown in FIG. so that the data φ. , φ1 will be at an intermediate level. When data equalize signal ATD is at H level, if data A and N continue to be input to differential amplifier circuit 1, the data equalize signal changes to L level, and N channel MOS transistor 3°19 becomes 0FFL.
, immediately data φ. , φ1 start changing from an intermediate level. Here, the chip select change detection signal CTD changes to L level and the J channel MOS transistor 14.2
1 is turned off, but at the same time the sense amplifier activation signal SE
becomes H level, N-channel MO3) transistor 4,
20 is turned on, the differential amplifier circuit 1 and the inverter circuit 2 remain active, and data φ, which is the amplified signal of data A and H, is generated. , φ, is output.

Thereafter, data φ1 is input to two inverter circuits 6°7, and data φ2. φ3 is output.

This data φ2. Depending on the level of φ3, P channel M
OS) ON/OFF of transistor 8 and N channel MO3) transistor 9 is determined, and finally data DOt+
T is output to the data output terminal 13.

As shown in FIG. 6, there is a delay in the generation of the sense amplifier activation signal SE, and even if the sense amplifier activation signal goes to the L level while the data equalize signal ATD is at the H level, the data from the memory cell While A1 person is reading,
Since the chip select change detection signal CTD is input to the differential amplifier circuit 1 and the inverter circuit 2, the data φ3.
φ2 becomes an intermediate level, the delay of time T as shown in FIG. 6 is cut off, and data E is output to the data output terminal 13.

In this way, in the above embodiment, the output data of both the differential amplifier circuit and the output buffer circuit is set to an intermediate level by the chip select change detection signal CTD, the sense amplifier activation signal SE, and the data equalize signal ATD. Even if the sense amplifier activation signal SE is delayed with respect to the data equalize signal ATD, the access time during chip select access can be increased.

Note that in the above embodiment, the outputs of both the differential amplifier circuit and the output buffer circuit are set to an intermediate level, but only one of them may be used, and substantially the same effect as in the above embodiment can be obtained.

In the above embodiment, the circuit shown in FIG. 2 was used as the differential amplifier circuit l, but the differential amplifier circuit shown in FIGS. 7 and 8, or the circuit shown in FIGS. A circuit combining two or more stages of differential amplifier circuits may be used, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the semiconductor memory device according to the present invention, even if the sense amplifier activation signal occurs later than the data equalize signal, by generating the chip select change detection signal, the differential amplifier circuit and the output buffer Activates at least one of the differential amplifier circuit and output buffer (the output data of both the output buffers is temporarily set to an intermediate level and is output). This has the effect of preventing at least one of them from becoming inactive, thereby speeding up access time.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an output system of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is an example of a differential amplifier circuit included in the circuit of the output system of the semiconductor memory device shown in FIG. 1 above. FIG. 3 is a timing chart of each signal in FIG. 1 above. FIG. 4 is a circuit configuration diagram of the output system of a conventional semiconductor memory device, FIG. 5 is a timing chart when each signal in FIG. 4 is normal, and FIG. 6 is a data equalization signal ATD and sense amplifier activation. Signal S
FIGS. 7 and 8 are timing charts of each signal when a mismatch occurs in E, and show other embodiments of the differential amplifier circuit included in the output system circuit of the semiconductor memory device shown in FIG. 1 above. FIG. In the figure, 1 is a differential amplifier circuit, 2 and 6.7 are inverter circuits, 5 is a data bus, 3.4.8°9.14 and 17-21.24-29.34-38 are N-channel MO
S) transistor, 8.15°16.22.23 and 3
0 to 33 are P-channel MOS) transistors, 10 is an inverter circuit and an A N D circuit, 11 is a pre-output buffer, 12 is an output bumper, 13 is a data output terminal, and A
, λ is data output from a memory cell, S is a chip select signal, BS is a block select signal, ATD is a data equalization signal, CTD is a chip select change detection signal, SE is a sense amplifier activation signal, φ. is the data input to the pre-output bus, φ is the data input to the data bus, φ2. φ. is the data input to the output buffer, and DOLIT is the output data. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Chip select change detection signal that detects that the chip select signal that controls whether or not to activate the semiconductor memory device changes from high level to low level, data that equalizes complementary data output from the memory cell array The output data of at least one of the differential amplifier circuit that amplifies the complementary data and the buffer circuit that buffers the output of the differential amplifier circuit is brought to an intermediate level by using the equalize signal and the sense amplifier activation signal. A semiconductor memory device characterized by: