JPH02303185A - Manufacture of multilayer printed wiring board - Google Patents

Manufacture of multilayer printed wiring board

Info

Publication number
JPH02303185A
JPH02303185A JP12520389A JP12520389A JPH02303185A JP H02303185 A JPH02303185 A JP H02303185A JP 12520389 A JP12520389 A JP 12520389A JP 12520389 A JP12520389 A JP 12520389A JP H02303185 A JPH02303185 A JP H02303185A
Authority
JP
Japan
Prior art keywords
layer material
sheet
prepreg
wiring board
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12520389A
Other languages
Japanese (ja)
Inventor
Yoshinori Urakuchi
浦口 良範
Katsutoshi Sakai
坂井 克寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP12520389A priority Critical patent/JPH02303185A/en
Publication of JPH02303185A publication Critical patent/JPH02303185A/en
Pending legal-status Critical Current

Links

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To eliminate a defective exterior view of a multilayer printed-wiring board and to prolong a life of a molded plate by a method wherein, in a laminated body where prepregs are piled up on each surface and/or each rear surface of two or more inner-layer material, a caulking pin is arranged in a required position and an outer-layer material is arranged on an outermost layer, the molded plate is arranged in a position not coming into contact with the caulking pin and this assembly is laminated and molded. CONSTITUTION:As an inner-layer material, an electrical circuit is formed on a copper-foil face such as a one-sided copper-clad laminated sheet, a double-sided copper-clad laminated sheet or the like. As a prepreg, a woven cloth, a nonwoven cloth or a mat composed of an inorganic fiber such as glass, asbestos or the like, an organic synthetic fiber such as a polyester, a polyamide or the like or a natural fiber, a sheet of paper or a base material combining these is impregnated with a single substance, a denatured substance or a mixed substance of a phenolic resin, a cresol resin, an epoxy resin or the like; the prepreg is then dried. As an outer-layer material, the one-sided copper-clad laminated sheet, a copper foil or the like is used. Caulking pins are installed preferably at four corner parts of the inner- layer material and the prepreg. It is required to arrange and install a molded sheet so as not to come into contact with the caulking pins; the sheet is installed at the inside of the positions of the caulking pins.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子機器、電気機器、コンビニ−ター、通信機
器等に用りられる多層印刷配線板の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a multilayer printed wiring board used in electronic equipment, electric equipment, convenience stores, communication equipment, etc.

〔従来の技術〕[Conventional technology]

従来の多層印刷配線板、例えば6ra印刷配線板は第1
図に示すように回路1を有する内層材2゜プリプレグ3
の所要位置にカシメ°ビン4を配して位置合せを行ない
最外層に外層材6を配設してから金属製成形プレート6
に挾んで積層成形して得られるが、カシメピン4が成形
プレート6に接触する部分の成形プレート6表面に傷、
打痕を生じ次回積層成形時に多層印刷配線板表面に傷、
打痕が転写され、製品に外観不良を与える問題があった
Conventional multilayer printed wiring boards, such as 6RA printed wiring boards, are first
Inner layer material 2゜prepreg 3 with circuit 1 as shown in the figure
The caulking pin 4 is placed at the required position for alignment, the outer layer material 6 is placed on the outermost layer, and then the metal forming plate 6 is placed.
Although it is obtained by lamination molding by sandwiching it between the two, there are scratches on the surface of the molding plate 6 at the part where the caulking pin 4 contacts the molding plate 6.
This will cause dents and scratches on the surface of the multilayer printed wiring board during the next lamination molding.
There was a problem in that the dents were transferred, giving the product a poor appearance.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の技術で述べたように従来の積層成形方法では多層
印刷配線板に外観不良が多発するのは避けられなりこと
であった。本発明は従来の技術における上述の問題点に
鑑みてなされたもので、その目的とするところは、多層
印刷配線板の外観不良をなくシ、成形プレート寿命を延
長させることのできる多層印刷配線板の製造方法を提供
することにある。
As described in the section on the prior art, in the conventional lamination molding method, it was inevitable that the multilayer printed wiring board would have frequent appearance defects. The present invention has been made in view of the above-mentioned problems in the prior art, and its purpose is to provide a multilayer printed wiring board that can eliminate the appearance defects of the multilayer printed wiring board and extend the life of the molded plate. The purpose of this invention is to provide a method for manufacturing the same.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は2枚以上の内層材の各上面及び又は下面にプリ
プレグを重ね、所要位置にカシメピンを配し最外層に外
層材を配設した積層体において、カシメピンに接触しな
い位置に成形プレートを配設して積層成形することを特
徴とする多層印刷配線板の製造方法のため、上記目的を
達成することができたもので、以下本発明の詳細な説明
する。
The present invention is a laminate in which prepregs are stacked on the upper and/or lower surfaces of two or more inner layer materials, swiveling pins are arranged at required positions, and an outer layer material is arranged on the outermost layer, in which a molded plate is arranged at a position that does not contact the swiveling pins. The above object can be achieved because of the method for producing a multilayer printed wiring board, which is characterized in that the multilayer printed wiring board is laminated and formed.The present invention will be described in detail below.

本発明に用込る内層材としては片面銅張積層板、両面鋼
張積層板等の銅箔面に電気回路を形成したもので、プリ
プレグとしてはフェノール樹脂、クレゾール樹脂、エポ
キシ樹脂、不飽和ポリエステル樹脂、ポリイミド樹脂、
ポリブタジェン樹脂、ポリフェニレンオキサイド樹脂、
弗化樹脂、ポリブチレンテレフタレート樹脂、ポリエチ
レンテレフタレート樹脂、ポリフェニレンサルファイF
樹脂等の単独、変性物、混合物をガラス、アスベスト等
の無機繊維やポリエステル、ポリアミド、ポリビニルア
ルコール、ポリアクリル等の有機合成繊維や木綿等の天
然繊維からなる織布、不織布、マット或は紙又はこれら
の組合せ基材に含浸、乾燥してなるものである。外層材
としては片面銅張積層板、銅箔等を用することができる
。カシメピン位置は好ましくは内層材、プリプレグの四
隅部に設けることが望ましい、成形プレートはカシメピ
ンに接触しないように配設することが必要で、そのため
カシメピン位置より内側になるように成形プレートサイ
ズを小さくしたり、或はカシメピン位置に切欠部を設け
た成形プレート形状にすることができる。かくすること
によりカシメピンと成形プレートとの接触部の傷、打痕
発生を防止することができるものである。積層成形手段
としては多段プレス法、プレス法、マルチロール法、ダ
ブルベルト法、連続無圧成形法等の任意積層成形手段を
用いることができる。
Inner layer materials used in the present invention include single-sided copper-clad laminates, double-sided steel-clad laminates, etc., in which an electric circuit is formed on the copper foil surface, and prepregs include phenolic resin, cresol resin, epoxy resin, and unsaturated polyester. resin, polyimide resin,
Polybutadiene resin, polyphenylene oxide resin,
Fluorinated resin, polybutylene terephthalate resin, polyethylene terephthalate resin, polyphenylene sulfide F
Woven fabrics, non-woven fabrics, mats, paper or It is obtained by impregnating and drying these combination base materials. As the outer layer material, a single-sided copper-clad laminate, copper foil, etc. can be used. The caulking pin position should preferably be provided at the four corners of the inner layer material or prepreg.The molding plate must be placed so that it does not touch the caulking pin, so the size of the molding plate should be reduced so that it is inside the caulking pin position. Alternatively, it can be formed into a molded plate shape with a notch provided at the caulking pin position. By doing so, it is possible to prevent scratches and dents from occurring at the contact portion between the caulking pin and the molded plate. As the lamination molding method, any lamination molding method such as a multistage press method, a press method, a multi-roll method, a double belt method, a continuous pressureless molding method, etc. can be used.

以下本発明の一実施例を図示実施例にもとづいて説明す
る。
An embodiment of the present invention will be described below based on an illustrated embodiment.

実施例 第2図は本発明の一実施例を示す簡略断面図である。第
2図に示すように回路1を有する厚さ0゜3Mのエポキ
シ樹脂ガラス布基材内層材2.21と該内層材2.2/
間に介在せしめた厚さQ、 111fflのエポキシ樹
脂ガラス布基材プリプレグ3を重ね、更に内層材2.2
1の外側にも厚さ0.1flのエポキシ樹脂ガラス布基
材プリプレグ3を配し所要位置をカシメピン4で位置合
せしてから最外層に厚さ0.035mの銅箔5を配設し
た積層体のカシメピッ4位置より内側になるように厚さ
3flのステンレ虞鋼製成形プレート6で挾み成形圧力
4 ’ k/d 5165℃で90分間積層成形して6
層印刷配線板を得た。
Embodiment FIG. 2 is a simplified sectional view showing an embodiment of the present invention. As shown in FIG. 2, an epoxy resin glass cloth base inner layer material 2.21 having a circuit 1 and a thickness of 0°3M and the inner layer material 2.2/
The epoxy resin glass cloth base material prepreg 3 with a thickness Q of 111 ffl is layered in between, and the inner layer material 2.2 is layered.
An epoxy resin glass cloth base material prepreg 3 with a thickness of 0.1 fl is placed on the outside of the 1, and the required positions are aligned with caulking pins 4, and then a copper foil 5 with a thickness of 0.035 m is placed on the outermost layer. Lamination molding was carried out for 90 minutes at 5165°C at 4' k/d and 4' k/d by sandwiching between 3 fl thick stainless steel forming plates 6 so that the parts were inside the crimping pin 4 position of the body.
A layer printed wiring board was obtained.

比較例 実施例の成形プレート6をカシメピン位置より外側にな
るように大型プレート1−用すた以外は実施例と同様に
処理して6層印刷配線板を得た。
Comparative Example A 6-layer printed wiring board was obtained by processing the molded plate 6 of the example in the same manner as in the example except for the large plate 1 so that the molded plate 6 was placed outside the caulking pin position.

実施例及び比較例の6層印刷配線板の外観不良及び成形
プレート寿命は第1表のようである。
Table 1 shows the appearance defects and molded plate life of the 6-layer printed wiring boards of Examples and Comparative Examples.

〔発明の効果〕〔Effect of the invention〕

本発明は上述した如く構成されている。・特許請求の範
囲に記載した構成を有する多層印刷配線板の製造方法に
おいては外観不良を低下させ、成形プレート寿命を延長
させる効果がある。
The present invention is constructed as described above. - The method for manufacturing a multilayer printed wiring board having the configuration described in the claims has the effect of reducing appearance defects and extending the life of the molded plate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来方法により材料を積層した場合の簡略断面
図、第2図は本発明の一実施例による材料を積層した場
合の簡略断面図である。 1は内層回路、2は内層材、3はプリプレグ、4はカシ
メピン% 5は外層材、6は成形プレートである。
FIG. 1 is a simplified sectional view when materials are laminated by a conventional method, and FIG. 2 is a simplified sectional view when materials are laminated according to an embodiment of the present invention. 1 is an inner layer circuit, 2 is an inner layer material, 3 is a prepreg, 4 is a caulking pin%, 5 is an outer layer material, and 6 is a molded plate.

Claims (1)

【特許請求の範囲】[Claims] (1)2枚以上の内層材の各上面及び又は下面にプリプ
レグを重ね、所要位置にカシメピンを配し最外層に外層
材を配設した積層体において、カシメピンに接触しない
位置に成形プレートを配設して積層成形することを特徴
とする多層印刷配線板の製造方法。
(1) In a laminate in which prepregs are stacked on the upper and/or lower surfaces of two or more inner layer materials, swiveling pins are placed at required positions, and the outer layer material is placed on the outermost layer, a molded plate is placed at a position that does not contact the swiveling pins. 1. A method for manufacturing a multilayer printed wiring board, characterized in that the multilayer printed wiring board is laminated and formed.
JP12520389A 1989-05-18 1989-05-18 Manufacture of multilayer printed wiring board Pending JPH02303185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12520389A JPH02303185A (en) 1989-05-18 1989-05-18 Manufacture of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12520389A JPH02303185A (en) 1989-05-18 1989-05-18 Manufacture of multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH02303185A true JPH02303185A (en) 1990-12-17

Family

ID=14904458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12520389A Pending JPH02303185A (en) 1989-05-18 1989-05-18 Manufacture of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH02303185A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103787665A (en) * 2012-10-30 2014-05-14 王治虎 Linking agent, organic ceramic material, organic ceramic circuit board and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103787665A (en) * 2012-10-30 2014-05-14 王治虎 Linking agent, organic ceramic material, organic ceramic circuit board and preparation method thereof

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