JPH0230254A - Multiplex transmitter-receiver in high level data link control procedure - Google Patents

Abstract

PURPOSE:To attain high speed transmission by executing the processing in the unit of one bit in the processing timing synchronously with the 1-bit unit for each channel. CONSTITUTION:Upon the receipt of an 8-bit serial data from a reception signal line RXD, a demultiplexer DEMUX branches the data to channels CHO, CHI and the data is sent to reception circuits RSP0, RSP1 respectively. The reception circuits RSP0, RSP1 convert the incoming data into an 8-bit parallel (1 word) data while applying flag detection and abort error check in the unit of one bit and send the result to a reception processing circuit RPR. The processing circuit RPR according to a timing circuit TIM reads out status information from a save memory RLM in the processing for each channel (processing in the unit of words) to make the preceding processing consecutive.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) This invention relates to high-level data link control procedures (H
H that performs multiple processing in the transmitter/receiver using DLC)
Regarding DLC transmission/reception method.

(Prior Art) The transmission unit frame in HDLC has the structure shown in FIG. ing. To explain with reference to FIG. 2, all data transmission and reception is performed using an 8-bit flag sequence (start flag: F
) and ends with an 8-bit flag sequence (end flag 2F). Between the start flag and the end flag, there is an information section of arbitrary length bits (data to be sent and received) and a 16-bit frame check sequence used to check whether the received frame is normal or not. (FCS) is included. If the data has the same pattern as the start flag, there is a risk that the receiving side may mistake this data for a flag sequence, so as a rule to avoid this, the data following the start flag is the frame before the end flag. Inspection sequence, 2. (FCS), when a "1" bit occurs five times in a row, a "0" bit is inserted next. Therefore, in order to reconstruct the original data on the receiving side, additional “0°° inserted into
It is necessary to remove the bit.

As a data transmission process, data can be constructed in units of 1 bit or in units of 1 word consisting of several bits (e.g. 8 bits), but in the former case, the various processes required for transmission and reception are relatively simple. However, in order to transmit and receive one bit of data, it is necessary to complete such processing within one bit of transmission time, and this poses a problem in that the data transmission speed is limited.

On the other hand, with the latter, data bits for transmission and reception can be stored in a buffer and processed in units of one word, so the various processing required for transmission and reception is directly limited by the data transmission speed. However, the data transfer process also includes processes that take a relatively long time, such as data transfer area recognition process.

Normally, in data transmission, time synchronization of transmission and reception can be achieved in units of one bit. However, when transmitting and receiving data using HDLC, the sending side inserts the II OII bit and the receiving side deletes 0 bits (O deletion), so the receiving side simply synchronizes in units of 8 bits. It is not possible.

As a conventional HDLC transmitter/receiver using HDLC, the third
There was something shown in the figure. In FIG. 3, RXD is a receiving signal line, which leads data to the receiving circuit 1.

The receiving circuit 1 has a processing function described below for received data, and includes a controller (CPU) that performs t1 control of transmitting and receiving the processed data via the data bus DB.
2. Memory for storing sent and received data (DMDI 3
and is connected to the transmitting circuit 4. The transmitting circuit 4 has a function corresponding to the reverse processing of the receiving circuit 1 in order to send data to the transmitting signal line TXD.

Next, the receiving operation by the receiving circuit 1 will be explained.

When data transmission via the reception signal line RXD is carried out in bit series, data is taken in one bit at a time from the reception signal line RXD, and it is constantly monitored whether or not a start flag is detected. When the start flag is detected, it is determined whether or not to delete 0 bit by bit for each bit of data detected thereafter, and if deletion is necessary, the deletion is executed and the result of deletion is When the data has a fixed bit length of one word, it is transferred to the memory 3.

In this case, the calculation of the frame check sequence is performed bit by bit if the processing of the device is bit serial, and is performed word by word if the processing is parallel. Also, whether or not "1°" is continuous for 7 or more bits is checked by parallel processing in units of 1 bit.The above-mentioned operation is repeated thereafter.

If 0 is not inserted in the data between the start flag and the end flag, the data is determined to be a multiple of 8 bits, so it is necessary to check the fractional bits.

When the end flag is detected, the fractional bits are checked, and when all the checks are normal, the controller 2 is notified that one normal frame has been received.

The above describes the case of one channel, but multiple channels,
For example, to explain the case of two channels with reference to Figure 4, CJ (0 indicates channel 0 data (1 bit), C old indicates channel 1 data (1 bit), and T indicates that 1 bit is transmitted. Indicates the time.

FIG. 5 is a block diagram of a conventional I (DLC) transmitter/receiver that transmits data of multiplexed channels in this way. In FIG. Various processes necessary for transmission and reception are performed for each bit of data transmitted on the signal line TXD.TIM is a circuit that indicates which channel data is currently being processed; RLMT is a save memory that saves data from the receiving circuit 1 using an address from the circuit TIM, and RLMT is a save memory that saves data from the receiving circuit 1 using an address from the circuit TIM.Controller (CPU) 2
and memory (DMDI 3) are identical to those described with reference to FIG.

Next, the reception operation of the HDLC transmitter/receiver shown in FIG. 5 will be explained. The HDLC signal input to the receiving circuit 1 via the receiving signal line RXD completes the flag detection, data serial/parallel conversion, frame check sequence calculation, 0 deletion, and fractional bit checking all within time T. do. In this way, various processes including writing to the memory 3 are performed within the time T.
Must be completed within.

The address from the circuit TIM to the memory SLM for saving is usually the same as the channel. In this case, the circuit TIM advances the count every time T, and the reception signal line RXD
When the count is equal to the number of multiplexed channels, the count returns to zero. In other words, the circuit TIM
The count is repeated as 0,1°0.1...

In the receiving circuit 1, processing of the received bits is completed within time T, but in order to process one frame of data, multiple bits must be processed continuously, so the processing of one bit is Once completed, the information needed to process the bits of its own channel in the next cycle must be retained in memory 3 until the next cycle, i.e. the processing within time T requires the use of such evacuation memory. R.L.
It also includes the process of saving information to M and the process of reading it.

The transmission operation is a reverse process of the reception operation explained above, and since it is clear from the above explanation, the explanation thereof will be omitted.

(Problem to be Solved by the Invention) Conventional multiplex transmitting and receiving devices must complete all processes related to transmission and reception within the time of one bit, so these processes limit the maximum speed of transmission and reception. There was a problem with eyelashes.

SUMMARY OF THE INVENTION An object of the present invention is to provide an fDLc transmitting/receiving device that can easily increase the speed of transmission without limiting various processes associated with transmission and reception by the time of one bit.

(Means for Solving the Problems) A multiplex transmitting/receiving device of the present invention transmits data in a high-level data link control procedure,
a transmission processing circuit that processes data to be transmitted in units of a predetermined number of bits according to the high-level data link control procedure; and a transmission processing circuit that transmits each bit of the data outputted from the transmission circuit in units of bits. Each line is equipped with multiple transmitter circuits that perform processing for the
A plurality of receiving circuits each perform processing for receiving bits received via each of the lines, and a predetermined number of bits outputted from each receiving circuit are processed for receiving as a unit and the data is replayed. It is equipped with a reception processing circuit to be constructed.

(Function) According to the multiplex transmitting/receiving device configured as described above, each of the transmitting circuits and receiving circuits that exchange data with the line processes bits forming the data for each line. On the other hand, each of the transmission processing circuits and reception processing circuits process the data in units of predetermined bits in response to data exchange with the controller, thereby enabling data transmission by HDLC at a high bit rate.
And do it efficiently.

(Embodiment) FIG. 1 shows an HDL using HDLC according to an embodiment of the present invention.
FIG. 2 is a block diagram of a C transmitting/receiving device. In FIG. 1, parts that are the same as those described above as the prior art are designated by the same reference numerals, and the description thereof shall refer to the above description.

The transmission processing circuit SPR has a function of reading out transmission data stored in the memory 3 and transferring it to the transmission circuits 5SPO and 5SPI, and a function of transferring transmission state information to the transmission circuits 5SPO and SSP+.

The transmission circuits 5spo and ssp are transmission processing circuits SPR.
It has the function of adding a flag, calculating a frame check sequence, and inserting 0 to the transmission data received from the SPR in 1-bit units according to instructions from the SPR, and further converting the data into serial data and transmitting the data to the multiplexer MUX.

MUX is a multiplexer MUX that multiplexes bits from the transmitting circuits 5SPO and ssp and sends them to the transmitting signal line TXD.

DEMUX is a demultiplexer that extracts channel O and channel 1 bits from the multiplexed signal on the reception signal line RXD, and the extracted bits are sent to the corresponding reception circuit RSP,
and RSP.

The receiving circuits R5P and RSP are the receiving processing circuit RPR.
It has the functions of detecting flags, calculating frame check sequences, deleting 0s, checking fractional bits, and serial-parallel conversion of data in units of bits, and is connected to the reception processing circuit RPH.

The reception processing circuit RPR includes the reception circuits R5Po and RSP.
It has functions to control the transfer of received data input from the memory 3 to the memory 3, and to process data errors detected by the reception circuit RSP, and the memory 3 and the controller via the data bus DB. Connected to 2.

TIMQ includes receiving circuits RSPO and RSP, and transmitting circuit 5SPo so that multiplexer MUX and demultiplexer EMUX switch channels 0 and 1 for each bit in synchronization with the bit series data shown in FIG.
and ssp to notify which one to select and connect.

TIM l is the reception processing circuit RPR and the transmission processing circuit SP
For R, the receiving circuit R3P and RSP are connected in units of 1 word.
It notifies which of the outputs of the r, transmitter circuits SSP and ssp is to be selected, and also assigns addresses for reading/writing the save data to the save memories SLM and RLM in correspondence with that channel. It has the function of supplying

Next, the reception operation of such a configuration will be explained.

When the demultiplexer DEMUX receives bit serial data as shown in FIG. 4 from the reception signal line RXD, it branches this data into channels CHO and CHI according to the timing circuit TIMO, and sends the data to the corresponding transmission circuits RSP o and CHI, respectively. Send to RSP. On the contrary,
The receiving circuits R3P and RSP detect flags and perform abort/abort operations on each bit of input data.
While performing an error check, it is converted into 8-bit parallel data (1 word) and sent to the reception processing circuit RPR. The processing circuit RPR performs the following processing on the data of that channel according to the timing circuit TIM_r.

In other words, in processing for each channel (processing in units of 1 word),
When the channel is switched, first, the state information saved after the previous processing of the own channel is read from the saving memory RLM, and the previous processing is substantially continued.

Next, the reception processing circuit RPR includes the reception circuits R3P and R
Checks whether processing request events such as flag detection, calculation of abort/error frame check sequence, octet error, or transfer request due to completion of parallel data in units of one word have occurred based on the output of SP. If it has occurred, the processing request event that has occurred is processed. Therefore, the reception processing circuit RPR processes the processing request event that occurs in the reception circuits R5P and RSP while managing the reception state.

However, in the non-receiving state, the reception processing circuit RPR responds only to the processing request event of flag detection, and ignores all other processing request events because they are meaningless. Reception processing circuit R
When a flag is detected in the non-receiving state, the PR enters the receiving state, and when a flag is detected during the receiving state, the reception is completed, and after the reception is completed, the PR enters the non-receiving state. Further, the reception processing circuit RPR enters a non-receiving state and checks whether an FCS check and octet error processing request event has occurred. As a result, the reception processing circuit RPR determines normal reception when none of the processing request events occurs, and starts error processing when either or both of the processing request events occur.

In addition, when a transfer request event occurs in the reception state, the reception processing circuit RPR controls the reception circuits R3PO and RPR.
The data constructed from the output of SP+ in units of one word is transferred to the memory 3. However, when an abort occurs in the reception state, the reception processing circuit RPR is
Executes error handling and enters non-receiving state.

The transmission operation is almost the same as the above-mentioned reception operation, but has a reverse operation sequence. In other words, transmission processing is performed in units of 1 bit,
The transmission processing request event that occurs in this process is processed by the transmission processing circuit SPH.

Note that when the number of multiplexed channels is n, the timing circuit TIM, in the format shown in FIG.
-... (: Hn, (: IO, C old...) is controlled so that the timing is repeated. Receiving circuit rtspo
~RSP,, transmitting circuits ssp, ~SSP,, there are a total of n+1 transmitting circuits facing each channel, and from the own channel (for example, channel CHO) to the own channel (channel C) of the next cycle.
HD) must be within the number of bits per word of the own channel. In other words, the processing time for the own channel by the reception processing circuit RPR and the transmission processing circuit SPR must occur at least once within the number of bits in one word unit of an l channel.

Receiving circuits R5Po and RSP in Fig. 1, , transmitting circuit s
sp.

and ssp, the interface can have a simple configuration, and the reception processing circuit RPR and the transmission processing circuit S
The PH multiplexing method is also simple.

However, since this multiplexing method unconditionally allocates the same processing time to all channels, the processing time allocated to channels where no processing request event actually occurs is wasted.

FIG. 6 is a block diagram of another embodiment in which an interface is configured to condense lines in order to eliminate such wasted processing time. In this case, each transmitting circuit R3PO to R3Pn
The processing request events that occurred are included in the order of occurrence, and the contents of the processing request event and information on its own channel number are included in the processing request event queue as one received processing request event. Each processing request event included in a processing event queue is processed into that queue. Also, the address for the save memory 3 is:
This is the own channel number in the processing event.

The operation of the transmission sequence will be explained in a similar manner. In this case, the reception processing circuit RPR and the transmission processing circuit SPR can perform their processing without wasting time.

In the above description, it is assumed that the frame check sequence calculation is serial processing and is included in the processing in units of 1 bit, but when the frame check sequence calculation is processed in parallel, it is processed in units of 1 word. Also multiplexer M
UX and demultiplexer DEMUX are unnecessary when input/output data is directly connected to a line.

(Effects of the Invention) As described above in detail, the present invention executes processing in units of one pit with processing timing synchronized in units of bits for each channel, so high-speed processing is possible.
Furthermore, it is possible to efficiently perform multiplex processing for transmitting and receiving HDLC frames at high bit rates.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an HDLC transmitting/receiving device showing an embodiment of the present invention, FIG. 2 is a format diagram showing the structure of an fDLC frame, FIG. 3 is a block diagram of a conventional HDLC transmitting/receiving device, and FIG.
5 is a block diagram of a conventional multi-channel HDLC receiver, and FIG. 6 is a block diagram of an HDLC transmitter/receiver according to another embodiment of the present invention. be. RSP,, RSP, ---receiving circuit, 5spo, ss
p,...transmission circuit, RPR...reception processing circuit, SPR...transmission processing circuit, CPU...controller.

Claims (2)

[Claims] (1) In a multiplex transmission/reception system that transmits data using a high-level data link control procedure, a transmission process that performs processing for transmitting data to be transmitted in units of a predetermined number of bits according to the high-level data link control procedure. a plurality of transmitting circuits each processing each bit of the data outputted from the transmitting circuit for transmission in bit units; and a plurality of transmitting circuits provided for each line receiving data according to a high-level data link control procedure. a plurality of receiving circuits that perform reception processing on the bits received through each of the lines; and a plurality of reception circuits that perform reception processing on the bits received through each of the respective lines; and 1. A multiplex transmitter/receiver in a high-level data link control procedure, comprising: a reception processing circuit that reconstructs the data link; and a controller that controls transmission and reception according to requests from the transmission processing circuit and the reception processing circuit. (2) The controller is characterized in that the controller registers processing requests for transmission and reception generated from each transmission processing circuit and reception processing circuit in an event queue, and advances the processing requests according to the registration in the event queue. The high level data according to claim 1.
Multiple transmitter/receiver in link control procedure.