JPH02302047A - Charge transfer device - Google Patents

Abstract

PURPOSE:To suppress a bad influence by a carrier generated by heat coming from a driver in a charge transfer device on which the driver has been mounted by a method wherein a contact region with a semiconductor substrate is formed between a first well region and a second well region. CONSTITUTION:A buried channel region 4 used to transfer an electric charge as a charge transfer part is formed in a first p-type well region 2; an n-MOS transistor 6 used as a driver is formed in a second p-type well region 3. A contact region 18 composed of an n-type high-concentration impurity diffusion region is formed in a region between the first p-type well region 2 and the second p-type well region 13 which have been separated; a high-level voltage is applied via an aluminum wiring layer 19. As a result, when the transistor 6 is operated, heat is generated. Even when holes are generated by the heat, the generated holes do not affect the first p-type well region 2 by crossing a region of a semiconductor substrate 1 which has been biased surely by the contact region. Consequently, a dark current is prevented; an electric charge without disorder is transferred.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer device in which a charge transfer section and a driver for the transfer are formed on the same substrate, particularly for CMO.
The present invention relates to a charge transfer device such as a COD imager manufactured by the S process.

(1) Summary of the Invention The present invention provides a charge transfer device in which a charge transfer section and a driver for charge transfer are formed on the same substrate, which are of a conductivity type opposite to that of a semiconductor substrate. By arranging the L-L regions for the transfer section at a distance and using the area between them as a contact region, and by devising the arrangement of the transistors in the driver, the transfer to the charge transfer section of the driver can be improved. This reduces the negative effects and also reduces the chip size.

[Prior Art] Charge transfer devices such as CCDs are usually manufactured using semiconductor substrates. This charge transfer device has a well region, a channel stopper region 9j, etc. formed on the semiconductor substrate,
Transfer electrodes and the like are formed on the substrate surface. In particular, in a solid-state imaging device having a light receiving section, regions such as a light receiving section and a buried channel layer are formed in a p-type semiconductor substrate or a p-type well region, and signal charges are read out.

In order to transfer charge to -I, a driver is required to supply a drive pulse to the transfer electrode of the charge transfer section. This driver was a separate chip in conventional charge transfer devices. However, with advances in semiconductor manufacturing technology, chips equipped with drivers are now being developed.

[Problem to be solved by the invention]

However, when a charge transfer section and a driver are formed on the same chip, holes are generated due to the heat generated by the driver. When holes generated by this driver enter, for example, a P-type well region surrounding a charge transfer channel, the holes disturb signal charges and adversely affect signals from the imaging section.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a charge transfer device equipped with a driver that suppresses the adverse effects of carriers generated by heat from the driver.

[Means for Solving the Problems] In order to achieve the above object, the charge transfer device of the present invention is a charge transfer device in which a charge transfer section and a driver for charge transfer are formed on the same substrate. Assumed. The charge transfer section may have a structure including a light receiving section adjacent to each other. the first conductivity type in which the charge transfer portion is formed;
and a second well region of a second conductivity type in which a transistor of a first conductivity type channel constituting the driver is formed are formed spaced apart from each other on a semiconductor substrate of a first conductivity type. For example, on an n-type semiconductor substrate, two p-type well regions are formed spaced apart from each other, a charge transfer portion is formed in the first well region, and an nM semiconductor is formed to constitute a driver.

An S transistor is formed in the second well region.

A second conductivity type channel transistor constituting a driver may be formed in the first conductivity type semiconductor substrate between the first and second well regions. A contact region with the semiconductor substrate is formed between the first well region and the second well region.

(Function) When a well region with a transistor that constitutes a driver and a well region that constitutes a charge transfer section are formed in succession, carriers generated in a portion of the driver directly enter the charge transfer section as dark current. Therefore, in the charge transfer device of the present invention, these well regions are formed separately and separated from each other.For example, the first conductivity type is an n type, and the well regions are separated from each other. If the second conductivity type is p-type, an nMO3) transistor serving as a driver is formed in the p-type second well region. Even if a hole is generated in the p-type second well region, the p-type second well region
Since the first well region is separated from the first well region and surrounded by the n-type region, the holes do not reach the first p-type well region, thereby preventing any adverse effects. Furthermore, in the charge transfer device of the present invention, the contact region with the semiconductor substrate is formed in a spaced apart region. Therefore, by biasing the portion of the semiconductor substrate between the two well cavities, it is possible to achieve sufficient junction isolation, particularly between the semiconductor substrate and the well head by applying a reverse bias.

(Example〕 Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment In this embodiment, two IPW well regions are formed on an n-type semiconductor substrate, and the driver has a CMO3 configuration.
This is an example of a CD.

A schematic cross-sectional structure of the main part is shown in FIG.

A first p-type well region 2 and a second p-type well region 3 are formed in an n-type semiconductor substrate 1, each having a predetermined depth. These first p-type well region 2 and second p-type well region 3 are formed separated by a distance M11.

A buried channel region 4 serving as a charge transfer section for transferring charges is formed in the first p-type well region 2 . A transfer electrode 5 is formed on this buried channel region 4 via a gate insulating film (not shown). Furthermore, the charge transfer section may have a structure in which a light receiving section is formed adjacent to the buried channel region 4 via a transfer gate so as to form a solid-state imaging device. In the first p-type well region 2 having this charge transfer portion, an extraction region 12 for biasing is formed. This extraction area 12
is made up of a p-type high concentration impurity region, and a low level voltage is applied by the aluminum wiring layer 13.

In the second p-type well region 3, an nMO3 transistor 6 used as a driver is formed.

This nMO3) range has a source region 7 and a train region 8 made of N-type high concentration impurity regions separated from each other, and a gate electrode 9 is formed on the region between the source region 7 and the train region 8. Source region 7 is connected to ground voltage GND
is supplied, and the drain region 8 is connected to the transfer electrode 5. Further, an input signal Φin is supplied to the gate electrode 9. In the second ρ-type well region 3 in which such an nMOS transistor 6 is formed, an extraction region 10 for applying a bias is formed. This extraction region 10 is made of a p-type high concentration impurity region, and a voltage at a lower level than that of the aluminum wiring layer 11 is applied to the extraction region 1.
0 to the second p-type well region 3.

A pMOS transistor 14 constituting a driver is formed on the surface of the n-type semiconductor substrate 1 outside the second p-type well region 3 . This p, Mps transistor 1
4 has a source region 15 and a drain region 16 made of p-type high concentration impurity regions separated from each other, and a gate electrode i17 is formed on the region between the source region 15 and the drain region 16. The source region 15 has a power supply voltage V,. is supplied,
The drain region 16 is connected to the transfer electrode 14. A human power signal Φin is supplied to the gate voltage +Eta17. This pMOS transistor 14 is the above-mentioned nMOS
constitutes an inverter in combination with transistor 6;
As a driver? drives the transfer electrodes 5 of both transfer sections.

An n-type semiconductor substrate 1 faces the substrate surface in a region between the first p-type well region 2 and the second p-type well region 3 which are spaced apart from each other. On the surface of this n-type semiconductor substrate 10, there is a contact h made of an n-type high concentration impurity diffusion region.
A riM region 18 is formed.

A high level voltage is applied to this contact region 18 via an aluminum wiring layer 19. Therefore, the pn junction between the semiconductor substrate l and the p-type well region 2.3 is reverse biased, and pn junction isolation is performed in the region adjacent to the contact region 18.

FIG. 2 is a schematic plan view of the CCD of this embodiment. A substantially rectangular first p-type well region 22 is formed in the center of the substantially rectangular chip 21 .

In this first p-type well region 22? ! A buried channel area for transporting cargo, etc. is formed. A contact region 23 for biasing the semiconductor substrate is formed around the p-type well region 22 so as to surround the well region 22 . And, outside this contact area 23,
An inverter 24.24 as a driver is provided. Specifically, this inverter 24.24 is
M.

This corresponds to a CMOS inverter composed of the S transistor 6 and the PMOS transistor 14. The output of the inverters 24, 24 is supplied to a transfer electrode formed in the p-type well region 22, and drives the transfer electrode.

In the CCD of this embodiment having such a configuration, the second p-type well region 3 having the nMOS transistor 6 constituting the driver is separate from the first p-type well region 2 having the charge transfer section. It is said to be well. For this reason, nMO
3. Even if heat is generated due to the operation of the transistor 6 and holes are generated by the heat, the semiconductor substrate 61 is biased by the contact region 23.
The generated holes do not affect the first ρ-type well region 2 even beyond the region. Therefore, dark current is prevented and charges are transferred without signal disturbance.

Second Embodiment In this embodiment, two p-type well regions are formed apart from each other, and the contact pH region to the substrate and the pMO transistor constituting the driver are located in the region between the well 3 region. This is an example of the formation of

Its schematic cross-sectional structure is shown in FIG. Similarly to the first embodiment, a first p-type well region 32 and a second p-type well region 32 each have a predetermined depth for an n-type semiconductor = Hil.
A mold well region 33 is formed. The first p-type well region 32 and the second p-type well region 33 are separated by a distance of 1.
They are formed with a spacing of 2. This distance i2 is the distance between the pMO3 transistor 44 and the contact region 4, as described later.
8 is the area where it is formed.

In the first p-type well region 32, a buried channel region 34 serving as a charge transfer section for transferring charges is formed. A transfer electrode 35 driven by a driver is formed on this buried channel region 34 through a gate insulating film (not shown). Further, the charge transfer section may have a structure in which a light receiving section is formed adjacent to the buried channel region 34 via a transfer gate. In the first p-type well region 32 having this charge transfer portion, an extraction region 42 for biasing is formed. This lead-out region 42 is made of a p-type high concentration impurity region, and a low level voltage similar to that applied to the aluminum wiring layer 43 is applied thereto.

This first p-type well region 32 and a distance wound! ! In the second p-type well region 33, which is spaced apart by 2, an nMO3) transistor 36 constituting a driver is formed. This nMO3) transistor 36 has a source region 37 and a drain region 38 which are n-type high concentration impurity regions, and a gate electrode is placed on the channel region between the source region 37 and the drain region 38 via a gate insulating film. 39 is formed. The source region 37 is applied with the ground voltage GND, and the drain region 3 is connected to the transfer electrode 35 to drive the transfer electrode 35. Furthermore, the gate electrode 39 is supplied with an input signal Φin. On the surface of this second p-type well region 33, an extraction region 40 made of a p-type high concentration impurity region is formed. This extraction region 40 is biased to a low level via an aluminum wiring layer 41.

The surface of the n-type semiconductor substrate 31 faces the region between the first p-type well region 32 and the second p-type well region 33 . Then, on the surface of the n-type semiconductor substrate 31, a pMOS transistor 44L constituting a driver! : A contact region 48 for biasing semiconductor 1[31 is formed. The positional relationship between these contact regions 48 and the pMOS transistor 44 is such that the contact region 48 is pM
The relationship is such that it is placed between the OS transistor 44 and the first p-type well region 32.

The pMOS+ transistor 44 has a source region 45 and a drain region 46 made of p-type high'arX impurity regions. The source region 45 is at the power supply voltage ■. 'h<, the drain region 46 is connected to the drain region 38 of the nMO3h transistor 36 and also to the transfer electrode 35, and the pMOS transistor 44 and the nMOS transistor 36 connect the transfer electrode 35. to drive. A gate electrode 47 is formed on the region between the source region 45 and the drain region 46 with a gate insulating film interposed therebetween. This gate electrode 47 is supplied with an input signal Φin.

The contact pH region 48 is a region for biasing the semiconductor substrate 31, and is composed of an n-type high concentration impurity region. This contact pH region 48 is formed to surround the first p-type well region 32 in a plane. And this contact area.

A voltage at a higher level than that of the aluminum wiring layer 49 is applied to the aluminum wiring layer 48 .

The CCD of this embodiment having such a structure has a first p-type well region 32 and a second p-type well region 33 formed separately, as well as a contact region 48, as in the first embodiment. Since the well region and the substrate are effectively separated by the bias applied through
This prevents it from affecting the inside. Therefore, signal charges etc. can be maintained well. In addition, especially in this embodiment, the ρMO3 transistor 44 constituting the driver
and pM in the nMO3 transistor 36, which requires a channel of the opposite conductivity type as the substrate.

The S transistor 44 has a contact region 48.
It is formed in a region between two well regions 32 and 33. Therefore, biasing of the channel forming region (or biasing of the well) of the pMO3 transistor 44 can be performed using the contact region 48, and in this way, the contact region 48 can be used for biasing the pMOS transistor 44 and n
By using it also for taking out the semiconductor substrate 31 of the mold,
Area for the pMO3I transistor 44 can be saved. Therefore, the theoretical yield can be improved without reducing the chip size or increasing the chip size.

[Effects of the Invention] The charge transfer device of the present invention has a first structure in which a charge transfer section is formed.
A well region and a second well region in which a transistor constituting a driver is formed are formed separately and separated from each other, and a contact region is formed in a region between these well regions.

Therefore, carriers such as holes generated by the heat of the driver are prevented from entering the first well region, dark current, etc. are prevented, and reliable charge transfer is realized. Further, in the charge transfer device of the present invention, by providing a transistor having a channel of a conductivity type opposite to that of the substrate on the contact region side, it is possible to reduce the chip size.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of an example of the charge transfer device of the present invention, FIG. 2 is a schematic plan view of the example, and FIG. 3 is a schematic diagram of another example of the charge transfer device of the present invention. FIG. 1.31...Semiconductor substrate 2.32...First p-type well region 3.33...
Second p-type well region 4.34...buried channel region 6.36...nMOS transistor 14.44...pMO5h transistor 18.48...
・Contact area patent applicant Akira Koike, Sony Corporation representative patent attorney (and 2 others) Figure 2

Claims (2)

[Claims] (1) In a charge transfer device in which a charge transfer section and a driver for charge transfer are formed on the same substrate, a first well region of a second conductivity type in which the charge transfer section is formed and the driver are configured. A second well region of a second conductivity type in which a transistor of a first conductivity type channel is formed is formed on a semiconductor substrate of a first conductivity type, spaced apart from each other, and the first well region and the second well region are separated from each other. A charge transfer device characterized in that a contact region with the semiconductor substrate is formed between the regions. (2) The first well region between the first well region and the second well region.
2. The charge transfer device according to claim 1, wherein a second conductivity type channel transistor constituting the driver is formed on a conductivity type semiconductor substrate.