JPH02301214A - Comparator - Google Patents

Abstract

PURPOSE:To prevent malfunction in a comparator at the post stage by applying a voltage being a division of a power supply voltage to an output terminal of the 1st stage of a 1st comparator and limiting an input voltage of the 2nd stage of a 2nd comparator so as to be a voltage within the normal operating range. CONSTITUTION:A power voltage Vcc connects to an output terminal A via resistors R3, R4 and a Zener diode 14 connects between the resistors R3, R4. In this case, the Zener voltage of the Zener diode 14 is selected in advance so as to be below the upper limit of the normal operating voltage of a 2nd comparator 12. Thus, when the level of the output terminal A reaches a maximum voltage, that is, when a transistor(TR) of the 1st comparator 11 is not driven, the voltage at the output terminal A is a Zener voltage of the Zener diode 14. Thus, a voltage below the normal operating upper limit value is inputted to an inverting input terminal of the 2nd comparator 12 and the comparator is operated normally. Thus, the comparator of the post-stage is normally operated and an accurate output waveform is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a comparator circuit having two stages of comparators, and particularly to a circuit configuration that can effectively prevent malfunctions of comparators in the subsequent stages.

(Prior Art) Optical communication is being widely used in various communication fields including local area networks (LANs) due to its excellent feature of not receiving electromagnetic induction in transmission paths.

By the way, in each receiving section of such an optical communication system, it is necessary to demodulate the optical signal and understand its data content, so it is necessary to install an optical receiving circuit that photoelectrically converts the optical signal and discriminates its logical level content. Required.

The present applicant has proposed a method which is mainly used for this type of application, and which enables discrimination of the logic level content of the input signal without being affected by the offset voltage of the input signal, and maintains a normal duty ratio of the discriminated output signal. A patent application has been filed for an optical receiving circuit that can perform
issue).

This invention includes a first comparator and a second comparator downstream of the first comparator.
This is a comparator circuit as shown in FIG. 7, which has two stages of comparators.
The logic level content of the received signal (input signal) is discriminated regardless of its offset voltage, and this first
The second comparator reverses the input mode of the signal corresponding to the input signal and the voltage (signal) corresponding to the threshold voltage, and the duty ratio of the discriminated logic signal is determined by the level comparison by the second comparator. I am trying to automatically correct any deviations.

[Means to solve the problem]

Although the intended purpose can certainly be achieved with the above configuration, as shown in FIG.
The second comparator has a -temporal voltage V. 0 power supply.

That is, the transistor 1' of the first comparator 1 in the first stage
Since the collector voltage of the transistor 1' is also V, when the comparison output of the first comparator 1 in which the transistor 1' is not driven becomes logic "1" level, the voltage value of the comparison output is the collector voltage v0. The pressure will rise to nearly 0.

On the other hand, the second comparator 2 in the second stage is also driven by the power supply voltage V 1 .

In the case of C, the input voltage at which the second comparator 2 operates normally is:
Although it depends on the characteristics of the second comparator 2, it is approximately 8 of the power supply voltage V.
It is up to a voltage value of about 0%.

C Therefore, the above-mentioned C has been boosted to near the power supply voltage V. The comparison output of the first comparator 1 (logic "1" level signal)
is input to the input terminal of the second comparator 2, the second
A malfunction may occur in the comparator 2, resulting in an inconvenience such as an inability to obtain an accurate output.

That is, FIG. 6(C) shows a time chart of a desirable output waveform of comparator 2, but if a malfunction occurs in comparator 2, the phase will shift as shown in FIG. 6(a). In addition, as shown in FIG. 6(b), the signal may be distorted at the rising edge of the signal.

The present invention has been made in view of these circumstances, and it is an object of the present invention to provide a comparator circuit that does not cause malfunctions in the subsequent comparators.

[Means and effects for solving the problem] Therefore, in the present invention, a voltage obtained by dividing the power supply voltage is applied to the output terminal of the first comparator in the first stage, and the voltage is applied to the output terminal of the first comparator in the second stage. The voltage input to the input terminal of the device is limited to a voltage value within the normal operating range.

Further, in this invention, the power supply voltage applied to the second stage comparator is boosted, so that the input voltage output from the first comparator in the first stage falls within the normal operating range of the second comparator. Therefore, we are trying to raise the voltage value at the upper limit of the normal operating range.

〔Example〕

Embodiments of the comparator circuit according to the present invention will be described below with reference to the drawings.

Note that in the following embodiments, an optical receiving circuit is assumed that has a main configuration of a first comparator 11 at the front stage and a second comparator 12 at the rear stage. A photodiode that receives an optical signal transmitted through a fiber and converts it into an electrical signal, an amplifier that amplifies this converted electrical signal as required, and this amplified signal (received signal)
is integrated, and the integrated signal is sent to the first comparator 11.
The integrator circuit and the first
Since the positive feedback circuit that applies the output of the comparator to the non-inverting input terminal (child terminal) is not directly related to the gist of the present invention, its explanation will be omitted.

That is, in the embodiment circuit shown in FIG. 1, numeral 11 receives the integrally processed signal of the received signal into the inverting input terminal (one terminal), and also sends the positive feedback signal of the positive feedback circuit to the non-inverting input terminal (child terminal). A first comparator 13 receives and compares the levels of these signals; 13 is a voltage dividing circuit that divides the power supply voltage V by resistors R1 and R2; 12 inverts the comparison output of the first comparator 11; This is a second comparator that receives the divided voltage from the voltage dividing circuit 13 at its input terminal and its non-inverting input terminal to compare the levels of these signals, and the comparison output of this second comparator 12 is The signal is applied as a differential demodulation output from the optical receiving circuit assumed in this embodiment to a data processing circuit (not shown) in the subsequent stage. The first and second comparators 11 and 12 each have a constant voltage V
. It is operated with a power supply voltage of 0.

The first comparator 11 has the same function as the comparator 1 in FIG.
"Level, logic" A transistor (not shown) is switched on and off according to the 1 degree level signal, and logic "
Outputs a signal indicating 0° level and logic "1° level."

In the circuit of the embodiment, the power supply voltage V applied to the output terminal of the first comparator 11 is limited to a predetermined voltage range by the diode C14, and the power supply voltage V applied to the output terminal of the first comparator 11 is limited to a predetermined voltage range.
2 is working properly.

Now, in order for the second comparator 12 to operate normally, the voltage value of the signal input to its inverting input terminal needs to be below a predetermined voltage value (normal operating voltage upper limit). This normal operating voltage upper limit value V1n is the voltage value V of the power supply voltage. 0
Although it depends on the characteristics of the second comparator 12, it is approximately 80% of the voltage value V2.

C Therefore, it is necessary that the maximum voltage value of the output terminal A of the first comparator 11 be less than or equal to the normal operating voltage upper limit value vio.

Therefore, in this embodiment, the power supply voltage (collector voltage) ■ is connected to the output terminal A via the resistors R3 and R4C as shown in 15 in FIG.
A Tuna diode 14 is connected between 3 and R4 (reverse voltage applied).

In this case, the Tsuzuna diode 14 has a Tsuzuna voltage V of the Tsuzuna diode 14 as follows: V ≦V <V (1) z
In cc shall be selected in advance.

Therefore, when the output terminal A becomes the maximum voltage value, that is, when the comparison output of the first comparator 11 whose transistor is not driven becomes a logic "1" level, the voltage value of the output terminal A becomes the above value. The current voltage value of the diode 14 becomes V.

Therefore, the relationship of the above equation (1) is established, and even if this voltage value {circle around (2)} is input to the inverting input terminal of the second comparator 12, the second comparator 12 will operate normally.

Further, even if the circuit is configured as shown in FIG. 2 using the Tsuzuna diode 14, the same effect as the embodiment circuit shown in FIG. 1 can be achieved.

That is, as shown at 16 in the figure, the power supply voltage VCC is connected to the output terminal B of the first comparator 11 via the resistor R5, and the Tsusna diode 14 is connected to the input terminal C of the second comparator 12 ( (reverse voltage applied). On the other hand, terminal B
, C is connected with a resistor R6.

In this case as well, the maximum voltage value of the output terminal B becomes the tuner voltage V of the tuner diode 14, and the above equation (1) holds true, so that the second comparator 14 operates normally.

Note that it is also possible to omit the arrangement of the resistor R6 in the figure.

Moreover, the same effect as the embodiments shown in FIGS. 1 and 2 can be achieved by using only a resistor without using a Tsuyuna diode.

That is, as shown at 17 in FIG. 3, the power supply voltage (collector voltage) is connected to the output terminal of the first C comparator 11 via the resistor R7, and one end of the resistor R8 is connected to the output terminal. , with the other end grounded,
A voltage dividing circuit is constructed to divide the power supply voltage V by C by resistors R7+R8, and the divided voltage is applied to the output terminal.

In this case, as mentioned above, in order for the second comparator 12 to operate normally, it is necessary to make the maximum voltage value at the output terminal, that is, the above-mentioned divided voltage V, below the above-mentioned normal operation type UT voltage upper limit value vi1. There is (the following equation (2)).

V ≦V <V (2)
OUT In cc Here, the divided voltage V is clearly OUT V = (R8/(R7+R8)l ・”ee
UT (3) Therefore, by selecting the resistors R7 and R8 so that the above equations (2) and (3) are satisfied, the second comparator 12
will operate normally.

Also, as shown at 18 in FIG. 4, the power supply voltage V. 0 is connected to the output terminal E of the first comparator 11 via a resistor R9, and a resistor R11 is connected to the input terminal F of the second comparator 12.
Connect one end and ground the other end. On the other hand, terminal B
, C is connected with a resistor R1o. In this way, the power supply voltage V
. . When the voltage is divided by the resistors R9゜R and R, the divided voltage value of the input terminal to tt F is V -fR/ (R9+R1o+R11) l
”Vo.

By selecting R9, R, and R such that OUT 11 (4) satisfies the above equation (2), normal operation of the second comparator 12 is achieved.

Now, in the embodiment described above, the power supply voltage V. 0 is divided by a Tsuyuna diode or a resistor so that it is equal to or less than the normal operating voltage vi□ of the second comparator 12, and is applied to the output terminal of the first comparator 11. The power supply voltage V applied to the second comparator 12 is such that the voltage input to the terminal is within the normal operating range.

A similar effect can be achieved by boosting the upper limit voltage of the normal operating range by boosting the voltage.

That is, as shown at 19 in FIG.
A booster circuit 20C (consisting mainly of a DC/DC converter, for example) is provided between 2 and the power supply voltage V2, and this booster circuit 20 boosts the power supply voltage V2 to a predetermined voltage value V2.
A boosted voltage V 1 of up is applied to the second comparator 12 .

The normal operation voltage upper limit value "in" of the second comparator 12 is uniquely determined by the boosted voltage V.

On the other hand, the maximum voltage value of the output terminal G of the first comparator 11 is V
(logical “1” level), but the condition for the second C comparator 12 to operate normally is ■ ≦”in
...(5)C.

By boosting the power supply voltage V to the boosted voltage V so that the above equation (5) holds true, the second ratio ee
The Op comparator 12 will operate normally.

That is, in the conventional circuit configuration as shown in FIG. 7, the second comparator 12 as shown in FIGS.
In some cases, it was not possible to obtain a normal output waveform, but by using the circuit configuration of the example, the same figure (C)
The original ideal output waveform shown in can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the comparator at the latter stage of the two-stage comparator circuit always operates normally, so that an accurate output waveform can be obtained.

Therefore, when such a two-stage comparator circuit is applied to an optical receiving circuit for optical communication, the reliability of demodulated data of an optical signal can be greatly improved.

[Brief explanation of drawings]

1 to 5 are circuit diagrams showing embodiments of a comparator circuit according to the present invention, and FIGS. 6(a) and 6(b) are time charts illustrating output waveforms of a conventional comparator circuit. Same figure (
c) is a time chart illustrating the output waveforms of the embodiment circuits of FIGS. 1 to 5, and FIG. 7 is a circuit diagram illustrating a conventional comparator circuit. 11...first comparator, 12...second comparator, 1
4...N diode, 20...Boost circuit, R8
゜R1...Resistance. Figure 3 Figure 5 Figure 6 Figure 7

Claims (2)

[Claims] (1) a first comparator that compares the levels of input signals;
a second comparator which inputs the comparison output of the first comparator to one input terminal thereof and performs a level comparison with a predetermined reference signal; and a predetermined voltage for operating the first and second comparators. A comparator circuit having a power source, the power source being connected to the output terminal of the first comparator so that the maximum value of the comparison output of the first comparator becomes the predetermined voltage, The power supply voltage connected to the output terminal is divided so that the maximum value of the input voltage of the one input terminal of the second comparator is within a range in which the second comparator normally operates. A comparator circuit characterized in that the divided voltage is applied to the output terminal. (2) a first comparator that compares the levels of input signals;
a second comparator which inputs the comparison output of the first comparator to one input terminal thereof and performs a level comparison with a predetermined reference signal; and a predetermined voltage for operating the first and second comparators. A comparator circuit having a power source, the power source being connected to the output terminal of the first comparator so that the maximum value of the comparison output of the first comparator becomes the predetermined voltage, A booster circuit for boosting the power supply voltage applied to the second comparator is provided between the second comparator and the power supply, and the one of the second comparators is A comparator circuit, wherein the second comparator operates normally when the predetermined voltage is input to an input terminal of the comparator circuit.