JPH02301208A - Gain adjustment circuit - Google Patents

Gain adjustment circuit

Info

Publication number
JPH02301208A
JPH02301208A JP12125789A JP12125789A JPH02301208A JP H02301208 A JPH02301208 A JP H02301208A JP 12125789 A JP12125789 A JP 12125789A JP 12125789 A JP12125789 A JP 12125789A JP H02301208 A JPH02301208 A JP H02301208A
Authority
JP
Japan
Prior art keywords
resistor
operational amplifier
inverting input
input terminal
ladder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12125789A
Other languages
Japanese (ja)
Inventor
Yasuhiro Ishizaki
石崎 泰寛
Hiroshi Yamazaki
博史 山崎
Shinya Yokodate
伸也 横舘
Kazunushi Saegusa
三枝 一主
Koji Kaneko
幸司 金子
Tatsuhiko Mizushima
達彦 水島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12125789A priority Critical patent/JPH02301208A/en
Publication of JPH02301208A publication Critical patent/JPH02301208A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To adjust the gain with a feedback resistor of an operational amplifier only by connecting two output current paths of a 2R ladder resistor to each inverting input terminal of 1st and 2nd operational amplifiers connected in series. CONSTITUTION:Each output current path of a 2R ladder resistor 3 connects to each inverting input terminal of two operational amplifiers 2, 8 connected in series. Since the two output current path currents in the complementary relation from a 2R ladder 3 are subject to voltage conversion to the inverting input terminal by a 1st feedback resistor 4, the inverting input terminal is an imaginary grounding point. Thus, the sum between the input voltage and a voltage across the 1st feedback resistor 4 connecting to the inverting input terminal of the 1st operational amplifier 2 is equal to the sum between the output voltage and a voltage across a 2nd feedback resistor 5 connecting to the inverting input terminal of the 2nd operational amplifier 8. Thus, the factor in the 2R ladder resistor is cancelled and the gain adjustment is attained with the feedback resistor only.

Description

【発明の詳細な説明】 [産業上の利用分野〕 本発明は、利得調整回路、特にアナログ信号振幅とデジ
タルデータの乗算、あるいはデジタル−アナログ変換等
のために用いられる利得調整回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gain adjustment circuit, and particularly to a gain adjustment circuit used for multiplication of analog signal amplitude and digital data, digital-to-analog conversion, and the like.

[従来の技術] 第2図は、特開昭63−102506号公報に示されて
いる従来のデジタル利得制御回路で、信号K (1)?
、t2Rラダー抵抗器(3) と帰還増幅器を形成して
いる第1の演算増幅器(2)の反転入力端子に第1の抵
抗器(4)を介して接続されている。演算増幅器(2)
の出力は、抵抗器(5)を介して加算用の第2の演算増
幅器(8)の反転入力端子に加えられる。2Rラダー抵
抗器(3)は乗算用電流源を作り出すための装置である
。第1の演算増幅器(2)の帰還用の第1の抵抗器(4
)は電流−電圧変換動作をする。信号源(1)の電圧を
第2の演算増幅器(8)の帰還抵抗器(7)で電流加算
させるための帰還抵抗器(6)は信号源(1)と第2の
演算増幅器(8)の反転入力端子との間に接続されてい
る。信号源(1)の電圧と演算増幅器(2)の出力電圧
を加算している帰還抵抗器(7)は回路の安定度を得る
ための位相補正用コンデンサ(9)と並列接続されてい
る。
[Prior Art] FIG. 2 shows a conventional digital gain control circuit shown in Japanese Patent Application Laid-Open No. 63-102506, in which the signal K(1)?
, t2R ladder resistor (3), and is connected via a first resistor (4) to the inverting input terminal of a first operational amplifier (2) forming a feedback amplifier. Operational amplifier (2)
The output of is applied via a resistor (5) to the inverting input terminal of a second operational amplifier (8) for summing. The 2R ladder resistor (3) is a device for creating a multiplication current source. The first resistor (4) for feedback of the first operational amplifier (2)
) performs current-voltage conversion operation. A feedback resistor (6) for adding current to the voltage of the signal source (1) by the feedback resistor (7) of the second operational amplifier (8) is connected to the signal source (1) and the second operational amplifier (8). is connected between the inverting input terminal of A feedback resistor (7) which adds the voltage of the signal source (1) and the output voltage of the operational amplifier (2) is connected in parallel with a phase correction capacitor (9) for obtaining stability of the circuit.

帰還増幅器(2)の帰還抵抗となっている2Rラダー抵
抗器(3)に流れる電流は、第1の演算増幅器(2)の
反転入力端子が仮想接地となっているため、2Rラダー
抵抗器(3)は半導体スイッチ(10)の切換え状態に
かかわらずGND電位(Ov)になっており、等価的に
2Rラダー抵抗器(3)が同一点へ接続されている場合
と同じである。従って、第1の演算増幅器(2)の出力
電圧をeoとすると、2R抵抗器の結合点からGND側
を見た等価抵抗値はRとなるので、コントロール点D7
での2R抵抗器(3)に流れる電流は(eo/2R)と
なり、D6、D5、 ・・・  、Doに流れる電流は
それぞれ1/2となる。従って、Dkでの2R抵抗器(
3)に流れる電流はIt −(eo /R)(1/2)
”−にとなる。故に、説明を簡単にするためにDkでの
2R抵抗器(3)のみが第1の演算抵抗器(2)の反転
入力端子へ接続された場合を考え、信号源電圧をVIN
、各抵抗器(4)、(5)、(6)、(7)の抵抗値を
それぞれR4、R5、R6、R7、とすると、(VIN
  O)−R4Itより eo =  (2) 8−k (R/R4)VINとな
る。但し、半導体スイッチ(10)が2R抵抗器(3)
に流れる電流すべてをGND側へ流す状態(D o〜D
7=0)では第1の演算増幅器(2)は負帰還増幅器を
形成されず、開ループ状態となるので、 eo =  AOVIN (AO;  第1の演算増幅
器(2)の開ループ利得) となる。一方、信号源電圧VINは帰還抵抗器(6)を
介して第2の演算増幅器(8)の反転入力へ印加される
から、その出力は Vout =−[(Ry /R6) (2)”  (R/R4)(R7/R5)] VINと
なる。さらに任意のコントロールデータでは、(R/R
4)(Rt /R5) =(Rt /Rs )、IXV
、N となる。R5−R,−Rとし、さらにR4−Rとした場
合、 X (R7/R) VIN となる。そして、D0〜D7−1、θ〜0の場合は、 Vout = (2’  1)  (R7/R) VI
N。
Since the inverting input terminal of the first operational amplifier (2) is virtually grounded, the current flowing through the 2R ladder resistor (3), which is the feedback resistance of the feedback amplifier (2), is 3) is at the GND potential (Ov) regardless of the switching state of the semiconductor switch (10), which is equivalently the same as when the 2R ladder resistor (3) is connected to the same point. Therefore, if the output voltage of the first operational amplifier (2) is eo, the equivalent resistance value seen from the connection point of the 2R resistor to the GND side is R, so the control point D7
The current flowing through the 2R resistor (3) is (eo/2R), and the current flowing through D6, D5, . . . , Do is 1/2. Therefore, the 2R resistor at Dk (
3) The current flowing in It − (eo /R) (1/2)
Therefore, to simplify the explanation, consider the case where only the 2R resistor (3) at Dk is connected to the inverting input terminal of the first operational resistor (2), and the signal source voltage VIN
, the resistance values of the resistors (4), (5), (6), and (7) are R4, R5, R6, and R7, respectively, then (VIN
From O)-R4It, eo = (2) 8-k (R/R4)VIN. However, the semiconductor switch (10) is a 2R resistor (3)
A state in which all the current flowing in the
7 = 0), the first operational amplifier (2) does not form a negative feedback amplifier and is in an open loop state, so eo = AOVIN (AO; open loop gain of the first operational amplifier (2)). . On the other hand, since the signal source voltage VIN is applied to the inverting input of the second operational amplifier (8) via the feedback resistor (6), its output is Vout = -[(Ry /R6) (2)'' ( R/R4) (R7/R5)] VIN.Furthermore, in any control data, (R/R
4) (Rt /R5) = (Rt /Rs), IXV
, N. When R5-R, -R and further R4-R are set, it becomes X (R7/R) VIN. And in the case of D0~D7-1, θ~0, Vout = (2' 1) (R7/R) VI
N.

また、Do −D? −1〜1の場合は、Vout −
[28(2’−1)] VINとなる。
Also, Do-D? -1 to 1, Vout -
[28(2'-1)] becomes VIN.

[発明が解決しようとする課題] 従来の利得調整回路は、以上のように構成されていたの
で、 X (RR7/R4R5)  R7/R61・VINか
ら理解できるように、利得パラメータRR7/R4R,
に2Rラダー抵抗器の抵抗値Rが含まれている。
[Problems to be Solved by the Invention] Since the conventional gain adjustment circuit was configured as described above, the gain parameters RR7/R4R,
includes the resistance value R of the 2R ladder resistor.

このR値は、半導体スイッチのオン抵抗値とラダー抵抗
器の抵抗値からなっているので、半導体スイッチのオン
抵抗値のバラツキや非線形性、温度特性などを改善し、
一定のものに選別する必要があり、また、2Rラダー抵
抗器の抵抗器に高性能のものを使用しなければならない
等の問題があった。
This R value is made up of the on-resistance value of the semiconductor switch and the resistance value of the ladder resistor, so it improves the variation in the on-resistance value, nonlinearity, temperature characteristics, etc. of the semiconductor switch.
There were problems such as the need to select a certain number of resistors, and the need to use high-performance resistors for the 2R ladder resistor.

この発明は、かかる問題点を解決することを課題として
なされたもので、演算増幅器の帰還抵抗器のみで利得調
整を可能にすると共に、安価な半導体スイッチと安価な
2Rラダー抵抗器とで構成できるデジタル式利得調整回
路を得ることを目的とするものである。
This invention was made with the aim of solving these problems, and allows gain adjustment using only the feedback resistor of an operational amplifier, and can be configured with an inexpensive semiconductor switch and an inexpensive 2R ladder resistor. The purpose is to obtain a digital gain adjustment circuit.

[課題を解決するための手段] この発明に係る利得調整回路は、2Rラダー抵抗器の各
出力電流路を、2つの直接接続された演算増幅器のそれ
ぞれの反転入力端子に接続することを特徴とする。
[Means for Solving the Problems] A gain adjustment circuit according to the present invention is characterized in that each output current path of a 2R ladder resistor is connected to each inverting input terminal of two directly connected operational amplifiers. do.

[作用] この発明による利得調整回路によれば、2Rラダーから
の相補的(合計が一定)関係にある2つの出力電流路電
流が、第1の帰還抵抗器により反転入力端子へ電圧変換
されているため、反転入力端子は仮想接地になり、入力
電圧と第1の演算増幅器の反転入力端子へ接続された第
1の帰還抵抗器両端電圧の合計と、出力電圧と第2の演
算増幅器の反転入力端子へ接続されている第2の帰還抵
抗器の両端電圧の合計が同一となる。そのため、2Rラ
ダー抵抗器の要素は相殺され、帰還用の抵抗器のみで利
得調整が可能となる。
[Function] According to the gain adjustment circuit according to the present invention, two output current path currents from the 2R ladder that are complementary (the sum is constant) are voltage-converted to the inverting input terminal by the first feedback resistor. Therefore, the inverting input terminal becomes virtual ground, and the sum of the input voltage and the voltage across the first feedback resistor connected to the inverting input terminal of the first operational amplifier, and the output voltage and the inverting voltage of the second operational amplifier. The sum of the voltages across the second feedback resistor connected to the input terminal becomes the same. Therefore, the elements of the 2R ladder resistor are canceled out, and the gain can be adjusted using only the feedback resistor.

[実施例] 次に、第1図に示す一実施例に基づいてこの発明をさら
に詳細に説明する。
[Example] Next, the present invention will be described in more detail based on an example shown in FIG.

第1図において、信号[(1)には、第1の抵抗器(4
)を介して2Rラダー抵抗器(3)の一方の出力電流路
と第1の演算増幅器(2)の反転入力端子とが接続され
て、負帰還増幅器が形成されている。
In FIG. 1, the signal [(1) is connected to the first resistor (4
), one output current path of the 2R ladder resistor (3) and the inverting input terminal of the first operational amplifier (2) are connected to form a negative feedback amplifier.

2Rラダー抵抗器(3)は、デジタル制御データにより
出力点が半導体スイッチ(10)によって切換えられる
もので、その第2の出力電流路は、第2の演算増幅器(
8)の反転入力端子に接続されている。この第2の演算
増幅器(8)は、第2の抵抗器(5)を介して第1の演
算増幅器(2)と直列に接続され、両抵抗器(4)と(
5)はそれぞれ、2Rラダー抵抗器(3)の電流を電圧
に変換する。
The output point of the 2R ladder resistor (3) is switched by a semiconductor switch (10) according to digital control data, and its second output current path is connected to the second operational amplifier (
8) is connected to the inverting input terminal. This second operational amplifier (8) is connected in series with the first operational amplifier (2) via a second resistor (5), and both resistors (4) and (
5) respectively convert the current of the 2R ladder resistor (3) into voltage.

ここで、第2の演算増幅器(8)は、2Rラダー抵抗器
(3)と第2の抵抗器(5)と共に負帰還増幅器を形成
している。また、(9)は回路の安定度を得るための位
相補正用コンデンサである。
Here, the second operational amplifier (8) forms a negative feedback amplifier together with the 2R ladder resistor (3) and the second resistor (5). Further, (9) is a phase correction capacitor for obtaining stability of the circuit.

2Rラダー抵抗器(3)の2R抵抗器は第1の演算増幅
器(2)と第2の演算増幅器(8)の仮想接地となって
いる反転入力端子へ接続されているため、第1の演算増
幅器(2)の出力電圧をeI ”” ” OUT 、第
2の演算増幅器(8)の出力電圧をe、)とすると、従
来回路の説明と同様、2R抵抗器は半導体スイッチ(1
0)の状態にかかわらず同電位(Ov)に接続されてい
るから、2R抵抗器に流れる電流は各点D7〜D0でそ
れぞれ(eo/R)(1/2)、 −、(eo/R)(
1/2)’となり、Dkでの2R抵抗器のみが第1の演
算増幅器(2)の反転入力端子に接続された場合の出力
電圧e0は、VIN−−R4■、より、 eo ”   (R/R4)  (2)’−’ VIN
となり、任意の制御データでは、 X、V、N となり、同様に、 eol”  R611″ ””   R5[1(1/ 2)  8−’  コ  
(eo/R)より、 e o ””   (R/ Rs ) [1/ (1−(1/2)’−k)]  eo+となり
、任意の制御データでは、 X (R/ Rs ) e or となる。従って、eol””VOuTとVINとの関係
は両式より、 X (R/Rs ) eol となるから、 lo  (L)orす、Z+−・・十υ7Z’ノX  
(R5/R4)  VIN Do +I)、  2+・・・+D727X  (R5
/R4)  VIN となる。
Since the 2R resistor of the 2R ladder resistor (3) is connected to the inverting input terminal which is the virtual ground of the first operational amplifier (2) and the second operational amplifier (8), the first operational Assuming that the output voltage of the amplifier (2) is eI ``'' OUT and the output voltage of the second operational amplifier (8) is e, ), the 2R resistor is connected to the semiconductor switch (1
0), the current flowing through the 2R resistor is (eo/R) (1/2), -, (eo/R) at each point D7 to D0, respectively. )(
1/2)', and the output voltage e0 when only the 2R resistor at Dk is connected to the inverting input terminal of the first operational amplifier (2) is VIN−-R4■, so eo ” (R /R4) (2)'-' VIN
So, for arbitrary control data, it becomes
(eo/R), e o "" (R/ Rs ) [1/ (1-(1/2)'-k)] eo+, and with arbitrary control data, X (R/ Rs) e or Become. Therefore, from both equations, the relationship between eol""VOut and VIN becomes X (R/Rs) eol, so lo (L)orsu, Z+-... 1υ7Z'ノX
(R5/R4) VIN Do +I), 2+...+D727X (R5
/R4) VIN.

従って、Do=D7−1.0〜0の場合、eo+= (
2’  1)(R5/R4)VIN″: 28 (Rs
 /R4)VIN また、D0〜D7−1〜1の場合、 eo+−(1/ (281))  (R5/R4)VI
N”=  1/2”  (R5/R4)VIN2R抵抗
器の反転入力への接続を逆にすると、X (R5/R4
) VIN となり、各データでは、 D0〜D7−θ〜0の場合、 eo+W (1/ (2”   1) l  (Rs 
/Ra ) VIND0〜D7−0.1〜1の場合、 eo+−2’  (Rs /R4) VIN従って、こ
の発明による利得調整回路によれば、いずれの極性にお
いても、2Rラダー抵抗器(3)の抵抗値Rが含まれず
、外付けの第1の抵抗器R4(4)と第2の抵抗器R6
(5)のみで、利得調整抵抗を形成できる。
Therefore, if Do=D7-1.0~0, eo+= (
2' 1) (R5/R4)VIN'': 28 (Rs
/R4)VIN Also, in the case of D0~D7-1~1, eo+-(1/ (281)) (R5/R4)VI
N”= 1/2” (R5/R4) Reversing the connection of the VIN2R resistor to the inverting input results in X (R5/R4
) VIN, and in each data, for D0~D7-θ~0, eo+W (1/ (2” 1) l (Rs
/Ra) VIND0~D7-0.1~1, eo+-2' (Rs/R4) VIN Therefore, according to the gain adjustment circuit according to the present invention, in either polarity, the 2R ladder resistor (3) does not include the resistance value R of the external first resistor R4 (4) and second resistor R6.
A gain adjustment resistor can be formed using only (5).

このように本発明によれば、第1の演算増幅器(2)の
出力電圧eoIすなわち回路の出力V。LITには2R
ラダー抵抗器(3)の抵抗値因子を含まず、第1の抵抗
器(4)と第2の抵抗器(5)のみが利得パラメータと
なるので、この両抵抗のみで利得調整が可能となり、半
導体スイッチや2Rラダー抵抗器(3)を高価なものと
する必要がなくなる。
Thus, according to the invention, the output voltage eoI of the first operational amplifier (2), ie the output V of the circuit. 2R for LIT
Since the resistance value factor of the ladder resistor (3) is not included and only the first resistor (4) and the second resistor (5) are the gain parameters, gain adjustment is possible with only these two resistors. There is no need to make expensive semiconductor switches and 2R ladder resistors (3).

なお、上記の実施例においては、デジタル式の利得調整
回路について説明したが、信号源電圧を直流電圧とした
デジタル−アナログ変換回路に適用することもできる。
In the above embodiment, a digital gain adjustment circuit has been described, but the present invention can also be applied to a digital-to-analog conversion circuit using a DC voltage as the signal source voltage.

[発明の効果] この発明は以上説明したとおり、第1の抵抗器と第2の
抵抗器との外付けの2本の抵抗器のみで利得調整が可能
となり、高精度の半導体スイッチや抵抗器を用意する必
要がなくなり、安価に回路を形成でき、また精度の高い
利得調整ができる効果がある。
[Effects of the Invention] As explained above, the present invention enables gain adjustment using only two external resistors, the first resistor and the second resistor, and is suitable for use in high-precision semiconductor switches and resistors. There is no need to prepare a circuit, the circuit can be formed at low cost, and the gain can be adjusted with high precision.

【図面の簡単な説明】 第1図はこの発明の一実施例による利得調整回路の回路
図、第2図は従来の利得調整回路の回路図である。 図において、(1)は信号源、(2)は第1の演算増幅
器、(3)は2Rラダー抵抗器、(4)は第1の抵抗器
、(5)は第2の抵抗器、(6)は帰還抵抗器、(7)
は帰還抵抗器、(8)は第2の演算増幅器、(9)は位
相補正用コンデンサ、(10)は半導体スイッチである
。 なお、図中、同一符号は、同一または相当部分を示す。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a gain adjustment circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional gain adjustment circuit. In the figure, (1) is the signal source, (2) is the first operational amplifier, (3) is the 2R ladder resistor, (4) is the first resistor, (5) is the second resistor, ( 6) is the feedback resistor, (7)
is a feedback resistor, (8) is a second operational amplifier, (9) is a phase correction capacitor, and (10) is a semiconductor switch. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】  入力電流路に接続され順次抵抗値が2Rとなる経路に
分岐する複数の抵抗と、この順次分岐された経路を2つ
の出力電流路のいずれかに接続する複数の半導体スイッ
チとを含み、半導体スイッチへ入力される信号に応じて
入力電流路から2つの出力電流路へ至る抵抗値の比が変
更される2Rラダー抵抗器と、 仮想接地となっている反転入力端子が第1の抵抗器を介
し、信号源に接続され、出力端子が信号出力端に接続さ
れた第1の演算増幅器と、 仮想接地となっている反転入力端子が第2の抵抗器を介
し、第1の演算増幅器の出力端子に接続された第2の演
算増幅器とを有し、 上記2Rラダー抵抗器の入力電流路を第2の演算増幅器
の出力端子に接続し、上記2Rラダー抵抗器の2つの出
力電流路を第1の演算増幅器の反転入力端子と第2の演
算増幅器の反転入力端子とにそれぞれ接続することを特
徴とする利得調整回路。
[Claims] A plurality of resistors connected to an input current path and sequentially branching into paths having a resistance value of 2R, and a plurality of semiconductor switches connecting the sequentially branched paths to either of two output current paths. a 2R ladder resistor whose resistance value ratio from the input current path to the two output current paths is changed according to the signal input to the semiconductor switch; and an inverting input terminal serving as a virtual ground. A first operational amplifier is connected to a signal source through a second resistor, and has an output terminal connected to a signal output terminal, and an inverting input terminal, which is a virtual ground, is connected to a first operational amplifier through a second resistor. and a second operational amplifier connected to the output terminal of the operational amplifier, the input current path of the 2R ladder resistor is connected to the output terminal of the second operational amplifier, and the input current path of the 2R ladder resistor is connected to the output terminal of the second operational amplifier. A gain adjustment circuit characterized in that an output current path is connected to an inverting input terminal of a first operational amplifier and an inverting input terminal of a second operational amplifier, respectively.
JP12125789A 1989-05-15 1989-05-15 Gain adjustment circuit Pending JPH02301208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12125789A JPH02301208A (en) 1989-05-15 1989-05-15 Gain adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12125789A JPH02301208A (en) 1989-05-15 1989-05-15 Gain adjustment circuit

Publications (1)

Publication Number Publication Date
JPH02301208A true JPH02301208A (en) 1990-12-13

Family

ID=14806779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12125789A Pending JPH02301208A (en) 1989-05-15 1989-05-15 Gain adjustment circuit

Country Status (1)

Country Link
JP (1) JPH02301208A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06303060A (en) * 1993-04-15 1994-10-28 Mitsubishi Electric Corp Gain control amplifier circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06303060A (en) * 1993-04-15 1994-10-28 Mitsubishi Electric Corp Gain control amplifier circuit

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