JPH0230115B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory circuits. In particular, dynamic random access memory (Random
The present invention relates to a memory interface circuit between a dynamic logic memory cell group and a static logic data input/output circuit in a RAM that has both the mass capacity of an access memory (RAM) and the high speed of a static RAM.

For convenience, a memory circuit using an N-channel MOSFET will be described below, but the same is essentially true for a memory circuit using a P-channel MOS FET.

When RAM has a memory capacity of 16K bits or more,
In order to avoid pin-necking of integrated circuits and an increase in chip size, a two-clock multi-address system is employed, as is well known. That is,
There are two clocks: RAS (Row Address Strobe) and (Column Address Strobe). The former controls the refresh operation of the one-transistor memory cell array, and the latter contributes to controlling the data input/output operations of reading and writing. do. The operation of the RAM will be explained below using the drawings.

The timing waveform of the read cycle is shown in FIG. Two clocks are activated in sequence, row address strobe followed by column address strobe. Using the former as a reference, the row address information is inputted taking into account the setup time and hold interval, and the latter is used as a reference, and the column address information is time-divisionally input from the same pin.Then, after passing through the internal operation of the memory circuit, valid data is output. appear.

Access time is an indicator of RAM performance, and if the queue delay time _tRCD is large, the time it takes for valid data to appear in the output, that is, the access time, will also be long. The shorter the access time, that is, the faster the access time, the higher the performance of the RAM. The higher the speed, the stricter the clock timing constraints become. For example, queue delay time
t A situation arises in _{the RCD} in which row address information and column address information must be switched.

When configuring a memory system using this type of RAM, you often run into the problem of how to keep the skew of multiple address information to a minimum. In a system with a large address skew, it is necessary to increase the queue delay time _tRCD , but conversely, this slows down the access time, resulting in a decrease in the performance of the memory system.

For this reason, there is an operation mode called page mode that allows faster access. In page mode, as shown in Figure 2, the row address strobe
Column address strobe with RAS low
By toggling CAS and randomly supplying only column address information, the first
This is a well-known operation mode in which multiple memory cells on a word line selected by RAS/cycle can be accessed at high speed. However, in this page mode, an access time of around 150 nanoseconds can be obtained at most, so systems that operate faster than this, such as video data processing systems that require an access time of around 50 nanoseconds, cannot be used. The speed is insufficient.

For this reason, a proposal has been made to change the page mode operation of only the column address strobe from dynamic to static in order to obtain faster operation. This proposal, as shown in Figure 3,
A register for temporarily storing read data is installed between the sense amplifier in the column address related circuit (shaded area) and the input/output data bus D, and this register is selected at high speed in response to column address information. A static circuit is introduced.

The basic configuration of the proposed column address related circuit is shown in FIG. Since the basic internal operations of the one-transistor type dynamic memory and static memory are well known, a detailed explanation will be omitted. After selecting multiple memory cells (both not shown) by the word line and amplifying the read data from the multiple memory cells by the sense amplifiers SA0, SA1, etc., each digit potential is set to the power supply level and the ground level, respectively, in accordance with the stored content. becomes. Between this digit line
If the signals of DL0 and 0, DL1 and 1, etc. are temporarily saved in the register blocks RG0, RG1, etc. by the data holding signal RGL,
Since the digit line of the dynamic logic system and the register blocks RG0, RG1, etc. of the static logic system are insulated, the read control signal is decoded by a static decoder (not shown).
If you access in response to REY0, REY1...
Access operations can be performed faster than in conventional page mode.

However, in a memory cell array using such open digit type sense amplifiers SA0, SA1..., the sense amplifiers SA0, SA1... are arranged in high density to match the pitch of the digit lines, and the register blocks RG0, RG1... . . must be added, resulting in stricter restrictions on circuit layout, which leads to an increase in chip size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit that alleviates constraints that occur during circuit layout and that aims to simplify the circuit configuration.

The circuit of the present invention provides at least one memory cell in which N memory cells are accessed in parallel via N digit lines in response to activation of one of a plurality of word lines.
a dynamic memory cell group, a sense amplifier corresponding to the digit line inserted and connected to the digit line to amplify read data from the memory cell group, and a sense amplifier for holding the output of the sense amplifier. a static type resistor corresponding to the sense amplifier; a resist gate corresponding to the sense amplifier connected between the far end of the digit line connected to one output of the sense amplifier and an input of the register corresponding to the sense amplifier; , a static read gate corresponding to the register that selects and outputs one of the outputs of the N registers input in response to activation of the one word line in response to an address signal; The present invention is characterized in that the resist gate is closed after the sense amplifier output is held in the register.

Next, the present invention will be explained in detail with reference to the drawings.

A basic configuration of an embodiment of the present invention is shown in FIG. 5, and an example of a circuit for the basic configuration is shown in FIG. 6.

Referring to FIGS. 5 and 6, in this embodiment, the paired digit lines DL0 and 0, DL1 and 1
Open digit type sense amplifiers SA0, SA1... inserted and connected between..., static type register blocks RG10, RG11..., and static type read gates G01 and G02 forming resist gates G00, G10... , G11 and G12... Only memory cells ME00 and ME01 of the dynamic memory cell group are shown, and other memory cells are omitted along with a large number of word lines.

In FIG. 6, when word line WL0 and di-word line DYR are activated, memory cell ME
The read data from 00 and ME01 is amplified by the sense amplifiers SA10 and SA11 with the amplified signal SE, and then the digit line pairs DL0,0 and DL1 and 1 are set to the power supply level and the ground level in response to the stored contents. information will appear. Note that digit lines DL0, DL1... are dummy word lines DYR.
A precharge signal that is activated just before the activation of
Reference cell RS0 activated in response to DR,
It is precharged to a potential slightly higher than ground potential via RS1.

The digit line pair DL0,0 and DL1,
If the information of DL1 is transmitted from either digit line,
As the data holding signal RGL rises, it is transmitted to register blocks RG10 and RG11. After that, register activation signal RGE rises and register blocks RG10 and RG11 are activated.

The memory cells ME00 and ME11 and their stored contents are amplified by sense amplifiers SA10 and SA11, respectively, and for example, when the digit line DL0 is at a power supply potential (hereinafter referred to as high level), the digit line
When DL0 is at ground potential (hereinafter referred to as low level), contact _N1 of register block RG10 and
_N2 has been charged to a high level in advance, but the charge at the contact _N1 is extracted through the resist gate G00 and the transistor _Q3 , and the contact _N1 becomes a high level and the contact _N2 becomes a low level, and the resistor block RG10 The information inside is determined to be 0''.

Also, when digit line DL0 is at low level and digit line 0 is at high level, the capacitance of contact _N1 is made larger than the capacitance of contact _N2 to create an unbalanced capacitance, and contact _N1 is at low level,
Contact _N2 becomes high level and the register block
The information in RG10 is determined to be "1".

After the information in the register blocks RG10, RG11, . . . is determined, the data holding signal RGL falls, and the digit lines DL0, DL1, . . . are isolated from the register blocks RG10, RG11, . Then, in response to the external address input information, the read control signal REY0 rises, and the read data buses DO and
The potentials of transistors Q ₄ , Q ₁ , Q ₃ and read gate G01 and transistors Q ₅ , Q ₂ , Q ₃ are respectively
The value determined by the ratio of the read gate G02 is determined. The difference potential becomes several 100 mV, and the differential amplifier added to the read data bus DO immediately operates at high speed.

The operation waveform diagram in the above read mode is shown in
As shown in the figure.

In this way, in order to save the sense amplifier information to the static type register blocks RG10, RG11, etc., it is only necessary to take it in from either one of the digit line pair, so the open digit type sense amplifiers SA10, SA11, etc. can be used. If
Since the resist blocks RG10, RG11, . . . are laid out at one end of the digit line, it is possible to prevent the chip size from increasing, which is extremely effective.

Another embodiment of the basic configuration of the present invention shown in FIG. 5 is shown in FIG.

In this embodiment, register blocks RG10, RG
11... information in register block RG10,
Instead of reading from the nodes N ₁ and N ₂ of RG11, the read control signals REY0 and REY1 are read from the node N ₂ .
Since the data is transmitted to the read data bus DO in response to . . . , the area occupied by the read data bus can be reduced to half that of the embodiment shown in FIG. 6. Moreover, the signal appearing on the read data bus is set to a reference voltage (a level intermediate between the physical "1" and "0" appearing on the read bus).
It is read out at high speed by a differential amplifier that amplifies the potential difference with V _Ref .

As described above, according to the present invention, in a RAM that has both the features of a dynamic MOS RAM with large capacity and a static MOS RAM with high speed, even if an interface circuit is added to realize this, the chip Layout can be done easily without affecting the layout,
Moreover, it is possible to realize RAM that can be accessed faster than before.

[Brief explanation of drawings]

Figures 1 and 2 show conventional dynamic RAM.
3 is a block diagram of a conventional RAM, FIG. 4 is a conventional memory circuit, FIGS. 5 and 6 are one embodiment of the present invention, and FIG. 7 is another embodiment of the present invention. Examples and FIG. 8 show operating waveforms for these embodiments, respectively. SA0, SA1, SA10, SA11...Sense amplifier, RG0, RG1, RG10, RG11...Register block, DL0,0, DL1,1...
...digit line, D _IN ...data input terminal, D _OUT
...Data output terminal, D, ...Input/output data bus, DI, ...Write data bus, DO, ...
Read data bus, RGL...data holding signal,
RGE...Register activation signal, WEY0, WEY
1...Write control signal, REY0, REY1...Read control signal, ME00, ME01...Memory cell,
RS0, RS1...Reference cell, DR...Precharge signal, SE...Amplified signal, WL0...Word line, DYR...Dummy word line, G00, G
10...Resist gate, G01, G02, G1
1, G12...Reading gate, Q ₁ , Q ₂ , Q ₃ , Q ₄ ,
Q ₅ ...transistor, N ₁ , N ₂ ...node.

Claims (1)

[Claims] 1 At least one dynamic memory cell group in which N memory cells are accessed in parallel via N digit lines in response to activation of one of a plurality of word lines; a sense amplifier corresponding to the digit line inserted and connected to the digit line to amplify read data; a static register corresponding to the sense amplifier for holding the output of the sense amplifier;
a resist gate corresponding to the sense amplifier connected between the far end of the digit line connected to one output of the sense amplifier and an input of the register corresponding to the sense amplifier; a static read gate corresponding to the register, which selects and outputs one of the outputs of the N registers input in response to activation in response to an address signal; A memory circuit characterized in that the resist gate is closed after being held.