JPH06101226B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular, it is intended to speed up continuous data reading and writing operations.

[Background of the Invention]

Conventional semiconductor memory devices are discussed, for example, in the article entitled "256 Kbit MOS Dynamic RAM with 100 ns Access Time" by Nikkei Electronics, October 24, 1983, p175-194, Nakano et al. In the nibble mode operation shown here, as is well known, 4-bit data is read in parallel from a memory cell array, the data is held in four read data latch circuits, and the data of the latch circuits are sequentially output by a nibble shift register. To do.

FIG. 4 shows a time chart of the read operation. Continuous reading of 4-bit data is performed by repeating the column address strobe signal ▲ ▼, but the second and subsequent outputs are only operations for selecting four latch circuits by the nibble address internally generated. Compared with the conventional page mode, the nibble cycle tie tNe is reduced to about 1/2. Similarly, FIG. 5 shows a time chart of the write operation.

However, in this method, all the circuits are composed of dynamic circuits, so even after the data is fetched from the memory array to the read data latch circuit, the column address strobe signal ▲ ▼ is cycled for continuous output. It is necessary to keep the row address strobe signal ▲ ▼ active, which has the drawback of increasing the cycle time tRc.

[Object of the Invention] An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to output data from the latch circuit to the outside (when reading (or writing) data continuously like a nibble mode. Another object of the present invention is to provide a semiconductor memory element capable of performing (input of data to the latch circuit from the outside) and initialization processing for the next latch operation in parallel.

[Summary of the Invention] In order to achieve the above object, a memory cell array capable of simultaneously reading a plurality of bits designated by a row address, and a static type that latches read data read from the memory cell array at regular intervals A semiconductor memory for reading data existing in the DRAM and latching the data in the register during activation of the RAS signal, sequentially reading the latched data, and outputting the data to the outside. In the element, a selection unit that selects a position from which data is first read from the register and sequentially outputs the data by shifting the read position from the selected position is provided, and a latch operation from the memory cell array to the register is performed. After the end, deactivate the RAS signal and
The latched data is output to the outside according to the signal from the selecting means.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a dynamic semiconductor memory device which is an embodiment of the present invention. The memory cell array 1 composed of a dynamic circuit is divided into four blocks, and each block M0 ... M3 has an input / output common data line pair I00 / ▲.
▼,… I03 / ▲ ▼ are connected. This input / output common data line pair I00 / ▲ ▼,… I03 / ▲ ▼
Applied to read data latch circuits RDL0, ..., RDL3 each composed of a static circuit, the output signal line pair is output data line pair D0B / ▲ via a selection MOS transistor pair Q0a / Q0b, ... Q3a / Q3b. Connected to ▼. Output data line pair D0B / ▲ ▼ consists of a static circuit 3
It is input to the data output circuit 6 having a state function and outputs the read data output signal Dout. Next, the write data signal Din is applied to the data input buffer 2, and its output, the input data line pair DiB / ▲ ▼, is connected to the input terminals of the write data latch circuits WDL0, ..., WDL3.
The outputs of the write data latch circuits WDL0 ... WDL3 are the input / output common data line pairs I00 / ▲ ▼, ..., I03 / ▲ ▼
, And write data to the blocks M0, ..., M3 of the memory cell array 1.

Each of the read data latch circuits RDL0, ... RDL3 and the write data latch circuits WDL0, ... WDL3, that is, 2-bit address signals Ai, Aj for selecting an arbitrary leading bit from 4 bits are applied to the address buffer 3. The output signals a0 and a1 are applied to the selection signal output circuit 4 composed of a static circuit.

The selection signal output circuit 4 first outputs address signals a0 and a1.
The result of decoding is that any one of the four selection signals SEL0, ..., SEL3 is activated, and then the shift clock signal SC is applied, one by one is activated in order based on the first activated selection signal. Turn into. The selection signals SEL0, ..., SEL3 are connected to the gate electrodes of the selection MOS transistor pair Q0a / Q0b, ..., Q3a / Q3b and the write data latch circuits EDL0 ,. An input / output enable signal ▲ ▼ for controlling continuous reading and writing of data is applied to the control circuit 5 composed of a static circuit. This control circuit 5 shifts the shift clock signal SC to the selection signal output circuit 4,
It outputs a gate signal OE to the data output circuit 6 and a data latch signal DL for controlling the data input buffer 2 during a write operation.

FIG. 2 is a time chart of the read operation of this embodiment. Since the operation of the MOS dynamic memory is a technique well known to those skilled in the art, the description of the basic detailed operation is omitted.
By activating the row address strobe signal RAS and the column address strobe signal CAS, a total of 4 bits of data of 1 bit each from each block M0, ..., M3 of the memory cell array 1 are simultaneously read, and the input / output common data line pair I00 / ▲
Read data latch circuits RDL0, ..., RDL3 are loaded via ▼, ..., I03 / ▲ ▼. At this time T1
Then the data read from the memory cell array 1 is completed,
Since the read data is held in the read data latch circuits RDL0, ..., RDL3 composed of static circuits, the row address strobe signal RAS and the column address strobe signal CAS are allowed to shift to the inactive state. It is possible to initialize the internal circuit composed of the dynamic circuit for the read or write operation of the.

On the other hand, continuous output of read data to the outside is performed by continuous repetition of the input / output enable signal IOE. The first activation of the input / output enable signal IOE activates the selection signal designated by the address signals Ai, Aj, for example, SEL1 to activate the MOS transistors Q1a / Q1b.
Is turned on, and the data held in the read data latch circuit RDL1 is applied to the data output buffer 6 through the output data line pair D0B / ▲ ▼. At the same time, the gate signal OE output from the control circuit 5 is activated and the read data signal Dout is output. Next, input / output enable signal ▲
At the rising edge at which ▼ shifts to the inactive state, the shift clock SC signal is output and the selection signal output circuit 4 becomes 1
Are shifted one by one, and SEL2 is activated instead of the selection signal SEL1 by the subsequent second activation of ▲ ▼, and the data of the read data latch circuit RDL2 is read data signal Do.
It is output as ut. Similarly, the data of the read data latch circuit RDL3 is output by the third activation of the input / output enable signal ▲ ▼, and the data of the read data latch circuit RDL0 is output as the read data signal Dout by the fourth activation. .

As described above, since the selection signal output circuit 4, the control circuit 5, and the data output circuit 6 are composed of static circuits,
Even after the row address strobe signal RAS shifts to the inactive state, continuous output of read data can be controlled.

Further, since the read data latch circuits RDL0, ..., RDL3 are composed of static circuits, in the read operation subsequent to the read operation, until the data is taken in by the read data latch circuits RDL0 ,. Since the data is held, as shown in FIG. 2, it is possible to output the read data of the operation and the next operation, that is, activate the row address strobe signal RAS in parallel.

FIG. 3 is a time chart of the write operation of this embodiment. In this embodiment, the write data latch circuits WDL0, ...,
Since WDL3 is composed of a dynamic circuit, write data latch circuit WDL0, ..., WDL for write data signal Din
Capture to 3 is limited to the period when the row address strobe signal RAS is activated, but regardless of the activation of the column address strobe signal CAS, the input / output enable signal is activated at the same time as the activation of the row address strobe signal RAS. It is possible to capture data continuously by IOE.

In the above embodiments, the case where continuous data output and data input are 4 bits is shown, but the present invention is not limited to this. Further, even if the data can be continuously input / output up to 4 bits or 8 bits, the operation can be ended with an arbitrary number of bits less than the maximum number of bits such as 1 bit or 2 bits. Needless to say. Further, in this embodiment, a normal 1-bit configuration, for example,
Although the structure of 256 K words × 1 bit is shown, a structure of a plurality of bits can be realized in the same manner. Furthermore, since the input / output enable signal IOE is added in this embodiment, for example, in the conventional 256K word × 1 bit configuration, all the pins of the 16-pin package are used, and the number of pins is insufficient. Although there is a problem, this can be easily solved by sharing the data input / output pin.

Also, instead of the I / O enable signal, the column address strobe signal CAS system circuit is configured by a static circuit, so that the function of the I / O enable signal for the column address strobe signal CAS when the row address strobe signal RAS is inactive It is also possible to prevent an increase in the number of pins by providing the.

〔The invention's effect〕

 According to the present invention, the following effects can be obtained.

1. Since the process of starting the next operation from the output of read data and initialization for the next operation can be performed in parallel, the cycle time of the read operation can be shortened.

2. The write data can be taken in at the same time when the write operation starts, so the cycle time of the write operation can be shortened.

Looking at an actual example, in a dynamic semiconductor memory device of 256 Kb, for example, a normal read or write cycle time is generally about 260 nS,
When reading or writing continuous 4 bits in nibble mode, the cycle time increases to about 500 nS. However, according to the present invention, even in the case of continuous 4-bit reading or writing, the cycle time does not increase and it can be executed in about 260 nS.

[Brief description of drawings]

FIG. 1 is a block diagram of a dynamic semiconductor memory device showing an embodiment of the present invention, FIG. 2 is a time chart of the read operation of the embodiment of FIG. 1, and FIG. 3 is a time chart of the write operation. FIG. 4 is a time chart of the read operation of the conventional semiconductor memory element, and FIG. 5 is a time chart of the write operation of the same. 1 ... Memory cell array 2 ... Data input buffer 3 ... Address buffer 4 ... Selection signal output circuit 5 ... Control circuit 6 ... Data output circuit RDL0 ... RDL3 ... Read data latch circuit WDL0 ... WDL3 ... Write data latch circuit SEL0 ... SEL3 ... Select signal IOE ... Input / output enable signal SC ... Shift clock signal

Claims (1)

[Claims] 1. A memory cell array composed of a dynamic circuit capable of simultaneously reading a plurality of bits designated by a row address, and a register for latching read data read from the memory cell array at regular intervals. In a semiconductor memory device for reading the data existing in the memory cell array and latching the data in the register while the RAS signal is activated, sequentially reading the latched data and outputting the data to the outside, A static type circuit is used, and a position is selected from the register to read data first, and a static type selection circuit that sequentially shifts the read position from the selected position and outputs the data is provided. When the RAS signal is deactivated after the end of the latch operation from the memory cell array to the register Together
A semiconductor memory device, wherein the latched data is output to the outside by the selection circuit.