JPH02297970A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve data-retaining properties by making thinner a gate insulating film between a floating gate and a control gate and a gate insulating film at a charge-accumulating part of MNOS type constituting EPROMs when constituting and IC with an EPROM and a MNOS type EPROM. CONSTITUTION:An involatile EPROM consists of a FETQEM where a control gate is provided on a floating gate through a gate insulating film. Also, an EEPROM consists of a FETQFM where a floating gate is provided on a tunnel insulating film and a MISFETQFS for selecting memory for driving it. Further, an EPROM consists of a FETQMM where a gate electrode is provided on a gate insulating film with a charge-accumulating part and a MISFETQMS for selecting memory cell for driving it. Thus, when constituting as in the above, a first gate insulating film 101 is formed by allowing a substrate 1 to be subjected to thermal oxidation and a second gate insulating film 104 consists of a mixed film where SiO2, Si3N4, and SiO2 are laminated in sequence from the lower layer.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device equipped with two or more types of nonvolatile memories. .

[Prior art]

Conventionally, there are two types of semiconductor integrated circuit devices with built-in microcomputers: EPROM and MNO8 type EEPROM.
2. Description of the Related Art Semiconductor integrated circuit devices equipped with various types of nonvolatile memory are known.

In the above-mentioned conventional technology, EPROM is used as a large-capacity ROM that can be rewritten many times, and MNO8 is used as a ROM that can be rewritten many times and has a small capacity.
A type EEPROM is used.

The EPROM includes a memory cell composed of a field effect transistor for storing information.

The field effect transistor includes a first gate insulating film,
It is equipped with a floating gate, a second gate gate, a control gate, etc. The first gate insulating film is provided on the main surface of the substrate. The first gate insulating film is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate. The floating gate is provided on the first gate insulating film. The floating gate is composed of, for example, a deposited polycrystalline silicon film. Impurities are implanted into the polycrystalline silicon film for purposes such as reducing resistance.

The control gate is provided on the floating gate with the second gate insulating film interposed therebetween. The second gate insulating film is made of, for example, a silicon oxide film. The silicon oxide film constituting the second gate insulation III is formed, for example, by thermally oxidizing the polycrystalline silicon film constituting the bloating gate.

The MNOS type EEPROM includes a memory cell composed of an information storage field effect transistor and a memory cell selection MISFET for driving the field effect transistor.

The field effect transistor includes a gate insulating film having a charge storage portion, a gate electrode, and the like.

The gate insulating film is composed of a laminated film in which a silicon oxide film and a silicon nitride film are sequentially laminated from the bottom layer on the main surface side of the substrate. The M N 0.9 type EEPROM retains data by trapping electrons in a trap level near the interface between the silicon oxide film and the silicon nitride film that constitute the gate insulating film.

Regarding this type of technology, for example,
It is described in Publication No. 87.

[Problem to be solved by the invention]

However, as a result of studying the above-mentioned prior art, the inventor found the following problems.

First, various film properties such as electrical insulation of a silicon oxide film formed by thermally oxidizing a polycrystalline silicon film are determined by the film quality of the polycrystalline silicon film, the concentration of impurities such as P in the polycrystalline silicon film, and the heat It largely depends on oxidation conditions, etc.

Therefore, in the semiconductor integrated circuit device described above, EP
The film characteristics of the second gate insulating film between the floating gate and the control gate of the ROM depend on the quality of the polycrystalline silicon film constituting the floating gate, the concentration of impurities such as P in the polycrystalline silicon film, thermal oxidation conditions, etc. Therefore, the film characteristics of the second gate insulating film deteriorate.

However, in order to increase the degree of integration of semiconductor integrated circuit devices, it is necessary to reduce the thickness of the gate insulating film, but as described above, the quality of the gate insulating film is poor; There was a problem in that it was not possible to make the insulating film thinner.

Furthermore, in the aforementioned MNO8 type EEPROM, electrons (information) trapped near the interface between the silicon oxide film and the silicon nitride film that constitute the gate insulating film are trapped due to defects such as pinholes in the silicon nitride film. There was a problem that leakage occurred to the gate electrode side, the amount of charge storage decreased, and the data retention characteristics of the MNO3 type EEPROM deteriorated.

Furthermore, the gate insulating film on the main surface of the substrate of the EPROM described above or the gate insulating film between the floating gate and the control gate, and the gate insulating film of the MNOS type EEPROM are formed in separate manufacturing processes. The problem was that there were too many.

The object of the present invention is to provide EEP RO,M and MNO8 type EEP.
In a semiconductor integrated circuit device equipped with a ROM, the EP
A gate insulating film between a floating gate and a control gate of a ROM memory cell and the MNOS type EE
It is an object of the present invention to provide a technique capable of thinning a gate insulating film having a charge storage part of a memory cell of a PROM.

Another object of the present invention is to provide a technique that enables high integration in the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of improving the data retention characteristics of the semiconductor integrated circuit device, EPROM, and MNOS type EEPROM.

Another object of the present invention is to use the EPROM and MNO8 type EE.
An object of the present invention is to provide a technique that can simplify the process in a semiconductor integrated circuit device equipped with a PROM.

Another object of the present invention is to provide an EPROM and a FLOTOX type E.
In a semiconductor integrated circuit device comprising an EPROM, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, and a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM;
An object of the present invention is to provide a technique that allows each tunnel insulating film of a memory cell of a LOTOX type EEPROM to be made thinner.

Another object of the present invention is to provide a technique capable of simplifying the process in a semiconductor integrated circuit device equipped with the EPROM and FLOTOX type EEPROM.

Another object of the present invention is to provide an EPROM and MNO8 type EEPR.
In a semiconductor integrated circuit device having an OM and a FLOTOX type EEPROM, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, a gate insulating film having a charge storage part of a memory cell of the MNOS type EEPROM; membrane, and the FLOT
An object of the present invention is to provide a technique that allows each tunnel insulating film of a memory cell of an OX type EEPROM to be thinned.

Another object of the present invention is to use the EPROM and MNO8 type E.
An object of the present invention is to provide a technology that can simplify the process in a semiconductor integrated circuit device equipped with an EP ROM and a FLOTOX type EEPROM.

Another object of the present invention is to
O8 type EEPROM or FLOTOX type EEPR□
An object of the present invention is to provide a technique that can simplify the process in a semiconductor integrated circuit device equipped with M.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) An EPROM in which a memory cell is composed of a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a field effect type in which a gate electrode is provided on a gate insulating film having a charge storage section. In a semiconductor integrated circuit device equipped with an EEPROM whose memory cells are transistors, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, and a gate insulating film having a charge storage part of a memory cell of the EEPROM. is composed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate.

(2) An EPROM in which a memory cell is configured with a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a memory cell is configured in a field effect transistor in which a floating gate is provided in a tunnel insulating film. In a semiconductor integrated circuit device comprising an EEPROM, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM and a tunnel insulating film of a memory cell of the EEPROM are placed on the main surface side of the substrate. It is composed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer.

(3) An EPROM in which a memory cell is formed by a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a field effect type in which a gate electrode is provided on a gate insulating film having a charge storage section. EEPRO that configures memory cells with transistors
M and E, which constitutes a memory cell with a field effect transistor with a floating gate on a tunnel insulating film.
In a semiconductor integrated circuit device equipped with an E P ROM,
a gate insulating film between the floating gate and the control gate of the memory cell of the EPROM;
a gate insulating film having a charge storage part of an OM memory cell;
The tunnel insulating film of the memory cell of the EEPROM is formed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate.

(4) An EPROM in which a memory cell is formed by a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a field effect type in which a gate electrode is provided on a gate insulating film having a charge storage part. EEPROM, whose memory cells are composed of transistors,
In a semiconductor integrated circuit device including a MISFET with a gate electrode provided on a gate insulating film, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, and a gate having a charge storage part of the memory cell of the EEPROM. an insulating film and the MISFE
1. A semiconductor integrated circuit device characterized in that the gate insulating film of T is composed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate.

(5) An EPROM in which a memory cell is configured with a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a memory cell is configured in a field effect transistor in which a floating gate is provided in a tunnel insulating film. In a semiconductor integrated circuit device comprising an EEPROM and a MISFET having a gate electrode provided on a gate insulating film, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, and a tunnel of a memory cell of the EEPROM. A semiconductor integrated circuit device characterized in that an insulating film and a gate insulating film of the MISFET are formed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate.

(6) An EPROM in which a memory cell is composed of a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a field effect type in which a gate electrode is provided on a gate insulating film having a charge storage part. EEPROM, whose memory cells are composed of transistors,
EEPRO consists of a memory cell consisting of a field effect transistor with a floating gate on a tunnel insulating film.
M and MISFE with a gate electrode provided on the gate insulating film
In the semiconductor integrated circuit device including the EPRO
a gate insulating film between the floating gate and the control gate of the EEPROM memory cell; a gate insulating film having a charge storage section of the EEPROM memory cell;
A tunnel insulating film of a memory cell of an EPROM, and the M
The gate insulating film of the ISFET is composed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate.

[Effect]

According to the above-mentioned means (1) to (6), even if defects such as pinholes occur in each insulating film constituting the composite film,
Defects such as pinholes in each insulating film are covered by other insulating films, and the defects are substantially eliminated, so that the film quality of the composite film is improved. As a result, the gate insulating film between the bloating gate and the control gate of the memory cell of the EPROM, the gate insulating film having the charge storage part of the memory cell of the MNoS type EEPROM, and the gate insulating film having the charge storage part of the memory cell of the FLOTOX type EEPROM are
Each of the memory cells and tunnel insulating films of the ROM can be made thinner.

According to the above-mentioned means (1), the gate insulating film between the floating gate and the control gate of the memory cell of the EPROM and the gate insulating film having the charge storage part of the memory cell of the EEPROM are each made of the same material. Since it can be formed in a process, the process can be simplified.

Further, according to the above-mentioned means (2), the gate insulating film between the floating gate and the control gate of the memory cell of the EPROM and the tunnel insulating film of the memory cell of the EEPROM can be formed in the same process. , the process can be simplified.

Further, according to the above-mentioned means (3), a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, a gate insulating film having a charge storage part of a memory cell of the EEPROM, a memory cell of the EEPROM Since each of the tunnel insulating films between the write semiconductor region and the floating gate can be formed in the same process, the process can be simplified.

Also, according to the above-mentioned means (4) to (6).

A gate insulating film of the MISFET, a gate insulating film between the floating gate and the control gate of the memory cell of the EPROM, a gate insulating film having a charge storage part of the memory cell of the MNOS type EEPROM, or a memory cell of the FLOTOX type EEPROM. Since each of the tunnel insulating films can be formed in the same process, the process can be simplified.

In addition, the above-mentioned means (1), (3), (4), and (6)
According to , since a silicon oxide film is interposed between the silicon nitride film on the main surface side of the substrate and the gate electrode, electrons trapped in the trap level near the interface between the silicon oxide film and the silicon nitride film However, leakage to the gate electrode due to defects such as pinholes in the silicon nitride film is reduced, and a decrease in the amount of stored charge is suppressed.

Thereby, the data retention characteristics of the MNO8 type EEPROM can be improved.

In addition, the above-mentioned means (1), (3), (4), and (6)
According to, gate disconnection between the floating gate and control gate of an EPROM memory cell, l1liW
A. Since each of the gate insulating films having the charge storage part of the memory cell of the MNO3 type EEPROM can be made thinner, it is possible to reduce the thickness of the gate insulating film having the charge storage part of the memory cell of the MNO3 type EEPROM.
High integration can be achieved in a semiconductor integrated circuit device equipped with a ROM.

[Embodiment of the Invention] An embodiment of the present invention will be specifically described below with reference to the drawings.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example I] A semiconductor integrated circuit device according to Example I of the present invention will be described with reference to FIGS. 1A and 1B (cross-sectional views of main parts showing a schematic configuration of the semiconductor integrated circuit device according to Example I). Note that FIG. 1A and FIG. 1B show the same semiconductor substrate of a semiconductor integrated circuit device.

The semiconductor integrated circuit device is made up of a p'' type semiconductor substrate 1. The p-type semiconductor substrate 1 is made of, for example, single crystal silicon. , hereinafter referred to as the main surface.

! ! As shown in FIG. 11IA and FIG. 1B, the semiconductor integrated circuit device of Example I has a memory cell as a nonvolatile memory using a field effect transistor Q0 in which a control gate is provided on a floating gate with a gate insulating film interposed therebetween. (hereinafter referred to as EPROM)
, a field effect transistor Q0 having a floating gate on a tunnel insulating film, and a memory cell selection M for driving the field effect transistor Q F II.
EEPROM whose memory cells are composed of ISFETQ□
(hereinafter referred to as FLOTOX type EEPRoM), a field effect transistor Q1.1. and a memory cell selection MISF for driving the field effect transistor Q.
It is equipped with an EEPROM (hereinafter referred to as MNOS type EEPROM), etc., which constitutes a memory cell with ETQ, . Further, the semiconductor integrated circuit device includes an MIS having a gate electrode provided on a gate insulating film as a peripheral circuit.
FETQni, Qn2. It is equipped with Qρx, QP*, etc.

Each element is insulated by an isolation region mainly composed of a p'' type semiconductor substrate 1, an inter-element isolation insulating film Woo, and a P-type channel stopper region 4. The inter-element isolation insulating film 100 is The P-type channel stopper region 4 is formed of a silicon oxide film formed by selectively oxidizing the main surface of the substrate. is provided on the main surface of the

The EPROM includes a field effect transistor Q for storing information, as shown on the left side of FIG. 1A. It is equipped with a memory cell consisting of.

The field effect transistor Q. is a p-type well region 3 provided on the main surface of the p-type semiconductor substrate 1 in a region defined by the inter-element isolation insulating film 100.
is provided on the main surface of the

The field effect transistor Q. is the first gate insulating film 101. It includes a floating gate 21, a second gate insulating film 104, a control gate 28, a pair of n-type semiconductor regions 6 and a pair of n-type semiconductor regions 9 forming a source region and a drain region, and the like.

The first gate insulating film 101 is provided on the main surface of the substrate. The first gate insulating film 101 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate.

The floating gate 21 is provided on the first gate insulating film 101. The floating gate 21 is a first conductive film subjected to predetermined patterning. The first conductive film is formed by, for example, CVD.
This is a polycrystalline silicon film deposited by a method. Also, the first
An n-type impurity, such as P, is implanted into the polycrystalline silicon film constituting the conductive film for the purpose of reducing resistance.

The control gate 28 is provided on the floating gate 21 with the second gate insulating film 104 interposed therebetween.

h1 The second gate insulating film 104 is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate. The silicon oxide film A is 1
For example, it is formed by thermally oxidizing a polycrystalline silicon film that constitutes the floating gate. The silicon nitride film is deposited by, for example, a CVD method.

The silicon oxide film B is formed, for example, by thermally oxidizing the silicon nitride film.

The control gate 28 is formed by subjecting a second conductive film to a predetermined pattern. The second conductive film, like the first conductive film, is made of, for example, a polycrystalline silicon film deposited by the CVD method, into which an n-type impurity such as P is implanted. Alternatively, the second conductive film is
For example, on the polycrystalline silicon film, W, T i ,
It is composed of a two-layer film provided with a metal film such as Mo. Alternatively, the second conductive film may be, for example, W Si on the polycrystalline silicon film.

It is composed of a two-layer film provided with a metal silicide film such as TiSi, MoSi2, etc.

Further, the floating gate 21. An insulating film 106 is provided on the outer peripheral surface of each of the second gate insulating film 104 and the control gate 28 .

The insulating film 106 is made of, for example, a silicon oxide film formed by thermal oxidation.

Furthermore, sidewall spacers 107 are provided on the sidewalls of the insulating film 10B. The sidewall spacer 107 is made of, for example, a deposited silicon oxide film.

A pair of n-type semiconductor regions 6 forming the source region and the drain region are formed by, for example, I
to I x 10"Catoms/cm"]
It is formed by implanting it by ion implantation. Therefore, the n-type semiconductor region 6 is provided in self-alignment with the control gate 28.

A pair of Go-type semiconductor regions 9 forming the source region and the drain region are mainly formed by the sidewall spacer 107.
and using the insulating film 106 as a mask, 1, for example, I
It is formed by implanting As by ion implantation in an amount of about 0" to I x 10" [atoms/c+++]. Therefore, the pair of n-type semiconductor regions 9
With the side wall spacer 107 interposed,
It is provided in self-alignment with respect to the control gate 28.

In this way, by configuring the source region and the drain region with the pair of n-type semiconductor regions 6 and the pair of d-type semiconductor regions 9, the source region and the drain region are LDD (
It has an extremely open drain structure.

An insulating film 108 is formed on one of the pair of Go-type semiconductor regions 9.
The first layer wiring 40 is inserted through the connection hole 50 provided in the
is connected.

The insulating film 108 insulates each element and the first layer wiring 40. The insulating film 108 is, for example, p,
s G (phosio silicate glass) film or BPSG (boron phosio silicate glass) I
It is composed of a single layer film. Or, the insulating film 10
8 is, for example, 2 in which a BPSG film is provided on a PSA film.
It is composed of layers. Alternatively, the insulating film 108 is composed of, for example, a two-layer film in which a BPSG film is provided on a deposited silicon oxide film.

The first layer wiring 40 is made of, for example, an aluminum film. Alternatively, the wiring 40 is made of, for example, an aluminum film in which one of Si, Cu, Pd, etc. is added to the aluminum film. Alternatively, the wiring 40 may be formed by, for example, 1. Si,C
It is composed of an aluminum film doped with a combination of two or more of U, Pd, etc. Or, the wiring 40 is
For example, it is composed of a two-layer film in which an aluminum film is provided on WSi, TiSi, MoSi, TiN, or the like. Alternatively, the wiring 40 may be made of, for example, WSi, TiSi.
,,MoSi2. It is composed of a two-layer film including an aluminum film containing additives on TiN or the like. Alternatively, the wiring 40 is formed of, for example, a two-layer film in which MoSi2 or the like is provided on an aluminum film. Or the wiring 40
For example, MoS is deposited on an aluminum film containing additives.
It is composed of a 2N film provided with i, etc. Alternatively, the wiring 40 may be, for example, WSi2. TiSi2. MoSi,
It is composed of a three-layer film in which an aluminum film is provided on , TiN, etc., and a MoSi, etc. is further provided on this aluminum film. Alternatively, the wiring 40 may be, for example, wlsi,
.

It is composed of a three-layer film in which an aluminum film containing additives is provided on TiSi, MoSi, TiN, etc., and MoSi, etc. is further provided on this aluminum film.

Further, an insulating film 109 is provided on the insulating film 108 and the first layer wiring 40. The insulating film 10
Reference numeral 9 insulates between the wiring 40 in the first layer and the wiring 41 in the second layer. The insulating film 109 is, for example, a silicon oxide film deposited by a plasma CVD method, a spin-on film, or a silicon oxide film deposited by a plasma CVD method.
It is composed of a glass film or a silicon oxide film deposited by plasma CVD method.

Although not shown, the wiring 41 and the insulation! 1
A final passivation film is provided on top of 109.

The final passivation film is composed of, for example, a deposited silicon nitride film or a spin-on-glass film.

In this way, the gate insulating film 1 between the floating gate 21 and the control gate 28 of the field effect transistor Q E , , l constituting the memory cell of the EPROM is
04 is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate. Even if a defect occurs, the defect such as a pinhole in each insulating film is covered by another insulating film, and the defect is substantially eliminated, so that the film quality of the gate insulating film 104 is improved.

As a result, the floating gate 21 of the field effect transistor Q- constituting the memory cell of the EPROM
The gate insulating film 104 between the control gate 28 and the control gate 28 can be made thinner.

Further, the impurity concentration of the pair of n-type semiconductor regions 6 forming the source region and drain region is the same as the impurity concentration of the pair of n-type semiconductor regions (7) forming the source region and drain region of the n-channel MISFET forming the peripheral circuit. higher than the concentration. This is achieved by increasing the impurity concentration of the pair of n-type semiconductor regions 6. This is to strengthen the electric field in the vicinity of the drain of the memory cell, to make it easier to generate hot I-carriers, and to make it easier to write data into the field effect transistor Q a s constituting the memory cell of the EPROM.

Furthermore, by providing the insulating film 10B, the EPROM
The data retention characteristics of the field effect transistor Q0 constituting the memory cell can be improved.

As shown in the center of FIG. 1A, the FLOTOX type EEPROM includes an information storage field effect transistor QW, 4, and a memory cell selection MISFET Q□ for driving the field effect transistor Q2.4. It is equipped with memory cells configured as follows.

The field effect transistor Q□ and the memory cell selection MISFET Q are provided on the main surface of the p-type semiconductor substrate 1 in a region defined by the inter-element isolation insulating film 100. It is provided on the main surface of the mold well region 3.

The memory cell selection MISFETQ includes a gate insulating film 101, a gate electrode 23, a pair of n-type semiconductor regions 5 forming a source region and a drain region, and the like.

The gate insulation m1ox is provided on the main surface of the substrate. The gate insulating film 101 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate.

The gate electrode 23 is provided on the gate insulating film 101. The gate electrode 23 is formed by subjecting the first conductive film to a predetermined pattern.

Further, the insulating film 10 is formed on the outer peripheral surface of the gate electrode 23.
6 is provided. By providing the insulating film 106, the dielectric strength voltage at the end of the gate electrode 23 can be improved.

Further, the side wall spacer 107 is provided on the side wall of the insulating film 106.

A pair of n-type semiconductor regions 5 forming the source region and the drain region are formed using an n-type impurity, for example, A, mainly using the gate electrode 23 and an insulating film (102) not shown as a mask.
It is formed by implanting s by, for example, ion implantation. Therefore, the pair of n-type semiconductor regions 5 are provided in self-alignment with respect to the gate electrode 23.

The insulating film (102) is formed during the process and does not exist when completed.
is provided on the gate insulating film 23.

The insulating film (102) is composed of, for example, a deposited silicon nitride film.

One side of the n-type semiconductor region 5 (the field-effect transistor Q PH side) is connected to the field-effect transistor Q□
It is integrated with one of a pair of n-type semiconductor regions 5 (semiconductor region for writing) constituting a source region and a drain region. Further, a first layer wiring 40 is connected to the other side of the n-type semiconductor region 5 through a connection hole 50 provided in the insulating film 108. A second layer wiring 41 is connected to the wiring 40 through a connection hole 51 provided in the insulating film 109.

The second layer wiring 41 has the same configuration as the first layer wiring 40.

The field effect transistor Q□ includes a first gate insulating film 101, a control gate 22, a second gate insulating film 104, a floating gate 29, a pair of n-type semiconductor regions 5 forming a source region and a drain region, etc. We are prepared.

The first gate insulating film 101 is provided on the main surface of the substrate. The first gate insulator [[101] is composed of, for example, a silicon oxide film formed by thermally oxidizing the substrate.

The control gate 22 is provided on the first gate insulating film 101. The control gate 22 is formed by subjecting the first conductive film to a predetermined pattern. Further, the control gate 22 is divided into two parts.

The floating gate 29 is connected to one of the divided control gates 22 (the memory cell selection MI
The second gate insulating film 10 is formed on the 5FET Q□ side).
The second gate insulating film 104 is provided on the main surface of the P-type well region 3 with the second gate insulating film 104 interposed therebetween, and one of the n-type semiconductor regions 5 (the memory cell The second gate insulating film 104 is provided on the selection MISFETQ side (write semiconductor region) with the second gate insulating film 104 interposed therebetween. The control gate 29 is formed by subjecting the second conductive film to a predetermined pattern.

The second gate insulating film 104 is provided between the control gate 22 and the floating gate 29, and between the floating gate 29 and the p-type well region 3, and 22 and one of the n-type semiconductor regions 5 (semiconductor region for writing). The second gate insulator 11!1104 is a field effect transistor Q forming a memory cell of the EPROM. It has the same structure as the second gate insulating film 104, and is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate. The bloating gate 2
The second gate insulator [104] interposed between the n-type semiconductor region 9 and one of the n-type semiconductor regions 5 (semiconductor region for writing) is used as a tunnel insulating film.

Further, the insulating film 106 is provided on the outer peripheral surface of each of the control gate 22, the floating gate 29, and the first gate insulating film 101.

Further, the side wall spacer 107 is provided on the side wall of the insulating film 106.

The pair of n-type semiconductor regions 5 forming the source region and the drain region mainly include the control gate 22, a mask provided between the control gate 22, the gate electrode 23 of the memory cell selection MISFET Q□,
Using the insulating film (102) (not shown) as a mask for impurity implantation, n-type impurities such as As are implanted by ion implantation. Therefore, the pair of n-type semiconductor regions 5 are connected to the control gate 2.
2 and the gate electrode 23 in a self-aligned manner.

In this way, the second gate insulating film 104 (tunnel insulating film) interposed between one of the pair of n-type semiconductor regions 5 (semiconductor region for writing) and the floating gate 29 is formed on the main surface side of the substrate. Since it is composed of a composite film in which silicon oxide film A, silicon nitride film, and silicon oxide film B are laminated sequentially from the bottom layer, even if a defect such as a pinhole occurs in each insulating film constituting the gate insulation film 11111104, each insulation film will remain intact. Defects such as pinholes in the film are covered by another insulating film, and the defects are substantially eliminated, so that the film quality of the gate insulating film 104 is improved. As a result, one of the pair of n-type semiconductor regions 5 (semiconductor region for writing) of the field effect transistor Q□ constituting the memory cell of the FLOTOX type EEPROM.
The tunnel insulating film 104 between the floating gate 29 and the floating gate 29 can be made thinner.

Further, the second gate insulating film 104 and the tunnel insulating film 104 are used as a field effect transistor Q constituting the memory cell of the EPROM. By having the same structure as the second gate insulating film 104, the gate insulating film and the tunnel insulating film can be formed using insulating films formed in the same process. There is no need to form the tunnel insulating film in a separate process, and E
The process of manufacturing a semiconductor integrated circuit device including a PROM and a FLOTOX type EEPROM can be simplified.

Furthermore, by providing the insulating film 106, FLOTO
The MNO, '3 type EEPROM, which can improve the data retention characteristics of the field effect transistor Q2.4 constituting the memory cell of the X type EEPROM, is equipped with the following method, as shown on the right side of FIG. 1A. , information storage field effect transistor Q
0, a memory cell configured with a memory cell selection MISFETQ□ for driving the field effect transistor.

The field effect transistor QHH and the memory cell selection MISFETQ,l are the element isolation insulating film 1.
It is provided on the main surface of the K-type well region 2 provided on the main surface of the p-type semiconductor substrate 1 in a region defined by 00.

M I S F E T Q M for selecting the memory cell
x represents the gate insulating film 101, the gate electrode 24, and a pair of p-type semiconductor regions 8 forming a source region and a drain region.
and a pair of p' type semiconductor regions 10 and the like.

The gate insulating film 101 is provided on the main surface of the substrate. The gate insulating film 101 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate.

The gate electrode 24 is provided on the gate insulating film 101. Said gate 11tii! 24 is the first conductive film subjected to predetermined patterning.

Further, the insulating film 1 is formed on the outer peripheral surface of the gate insulating film 24.
06 is provided. By providing the insulating film 106, the dielectric strength of the end portion of the gate electrode 24 can be improved.

Further, the side wall spacer 107 is provided on the side wall of the insulating film 106.

A pair of P-type semiconductor regions 8 forming the source region and the drain region are formed using, for example, 1×10 ” [ato
ms/cm"] by implanting B by ion implantation. Therefore, the pair of p
The type semiconductor region 8 is provided in self-alignment with the gate electrode 24.

a pair of p° forming the source and drain regions;
The type semiconductor region 10 is formed using, for example, I
X 10” to I X 10” [atoms/cm”]
It is formed by implanting a certain amount of B by ion implantation. Therefore, the pair of p° type semiconductor regions 1
1 is provided in self-alignment with the gate electrode 24 with the sidewall spacer 107 interposed therebetween.

In this way, the source region and the drain region are constituted by the pair of P-type semiconductor regions 8 and the pair of p°-type semiconductor region 10, so that the source region and the drain region have an LDD structure.

One of the pair of p' type semiconductor regions 10 is integrated with one of the pair of p' type semiconductor regions 10 forming the source region and drain region of the field effect transistor QxH. The first layer wiring 40 is connected to the other of the pair of p° type semiconductor regions 10 through a connection hole 50 provided in the front/distribution film 108.

The field effect transistor Q has a gate insulating film 10.
4, a gate electrode 30, a pair of p-type semiconductor regions 8 and a pair of p'-type semiconductor regions 10 forming a source region and a drain region, and the like.

The gate insulating film 104 is provided on the main surface of the substrate. The gate insulating film 104 is a field effect transistor Q that constitutes a memory cell of the EPROM. The second gate insulating film 104 of the FLOTOX type EEPROM
Field effect transistor QW that constitutes the memory cell of
H second gate insulating film 104 and tunnel insulating film 10
4, and is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate.

The gate electrode 30 is provided on the gate insulating film 104. The gate electrode 30 is formed by subjecting the second conductive film to a predetermined pattern.

Further, the insulating film 10 is formed on the outer peripheral surface of the gate electrode 30.
6 is provided.

Further, the side wall spacer 107 is provided on the side wall of the insulating film 106.

a pair of ps forming the source region and the drain region;
The type semiconductor region 8 is formed using, for example, 1×10 ” [at
o@s/cm"] by implanting B by ion implantation. Therefore, the pair of p
The type semiconductor region 8 is provided in self-alignment with the gate electrode 30.

a pair of p° forming the source and drain regions;
The type semiconductor region 10 is formed using, for example, I
X 10” to I X 10” [atoms/cm”]
It is formed by implanting a certain amount of B by ion implantation. Therefore, the p° type semiconductor region 10 is provided in self-alignment with the gate electrode 30 with the sidewall spacer 107 interposed therebetween.

In this way, by forming the source region and the drain region with the pair of p-type semiconductor regions 8 and the pair of p°-type semiconductor regions 10, the source region and the drain region are
It has an LDD structure.

In this way, the gate insulating film 10 having a charge storage portion
4 is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate, so that pinholes etc. are formed in each insulating film constituting the gate insulating film 104. Even if a defect occurs, the defect such as a pinhole in each insulating film is covered by another insulating film, and the defect is substantially eliminated, so that the film quality of the gate insulating film 104 is improved.

Thereby, the gate insulating film 104 of the field effect transistor Q□ constituting the memory cell of the MNO8 type EEPROM can be made thinner.

Furthermore, since the silicon oxide film B is interposed between the silicon nitride film and the gate electrode 30, the electrons (information) trapped in the trap level near the interface between the silicon oxide film A and the silicon nitride film are , leakage to the gate electrode 30 side due to defects such as pinholes in the silicon nitride film is reduced, and a decrease in the amount of stored charge is reduced.

Thereby, the data retention characteristics of the MNO8 type EEPROM can be improved.

Also, the second gate insulating film 104 of the field effect transistor Qmm constituting the memory cell of the EPROM, the second gate insulating film 104 of the field effect transistor QFH constituting the FLOTOX type EEPROM (7) memory cell IJ. Film 104 and tunnel insulating film 104, MNO8 type EE
Gate insulation II of the field effect transistor QNN that constitutes the PROM memory cell! Since each of 1104 can be formed with an insulating film formed in the same process, there is no need to form the gate insulating film and tunnel insulating film in separate processes.
OX type EEPROM and MNO8 type EEPRO
The process of manufacturing a semiconductor integrated circuit device including M can be simplified.

Furthermore, by providing the insulating film 106, the MN6
The data retention characteristics of the field effect transistor QNH constituting the memory cell of the S-type EEPROM can be improved.

the n-channel MISFETQn constituting the peripheral circuit;
and Qna, as shown on the left side of FIG. 1B, in a region surrounded by the element isolation insulating film 100,
The p-type well region 3 is provided on the main surface of the p-type semiconductor substrate 1 .

The n-channel MISFET Qn has a gate insulating film 1
01, a gate electrode 25, a pair of n-type semiconductor regions 7 and a pair of go-type semiconductor regions 9 forming a source region and a drain region, and the like.

The n-channel MISFET Qn has a gate insulating film 1
05, Gate Electric! 31, a pair of n-type semiconductor regions forming a source region and a drain region, a pair of n-type semiconductor regions 9, and the like.

The gate insulating films 101 and 105 are provided on the main surface of the substrate. The gate insulating films 101 and 105 are
For example, it is composed of a silicon oxide film formed by thermally oxidizing a substrate.

The gate electrode 25 is provided on the gate insulating film 101. The gate electrode 25 is formed by subjecting the first conductive film to a predetermined pattern.

The gate electrode 31 is provided on the gate insulating film 105. The gate electrode 31 is formed by subjecting the second conductive film to a predetermined pattern.

Further, the insulating film 106 is provided on the outer peripheral surfaces of the gate electrodes 25 and 31. By providing the insulating film 106, each of the gate electrodes 25 and 31. The dielectric strength of the end portion can be improved.

Further, the side wall spacer 107 is provided on the side wall of the insulating film 106.

A pair of n-type semiconductor regions forming the source and drain regions of the n-channel MISFETs Qn and Qnz are formed using, for example, 1x101'' [ato
ms/am"] by implanting P by ion implantation. Therefore, the pair of n-type semiconductor regions 7 are provided in self-alignment with respect to each of the gate electrodes 25 and 31. There is.

A pair of n° type semiconductor regions 9 forming the source and drain regions of the n-channel MISFETs Qn and Qn are formed using, for example, 1×100 to I
The pair of n° type semiconductor regions 9 are formed by implanting As by ion implantation in an amount of about 2
5 and 31 in a self-aligned manner.

By configuring the source region and the drain region by the pair of n-type semiconductor regions 7 and the pair of go-type semiconductor regions 9 in this way, the source region and the drain region have an LDD structure.

A first layer wiring 40 is connected to one of the pair of go-type semiconductor regions 9 of the n-channel MISFETQn through a connection hole 50 provided in the insulating film 108.

The insulating film 10 is placed on one side of the pair of n° type semiconductor regions 9 of the n-channel M I S F E T Q n.
8 through the connection hole 50 provided in the first layer wiring 4.
0 is connected. The first layer wiring 40 is connected to the second layer through the connection hole 51 provided in the insulating film 109.
One side of the wiring 41 of the layer is connected.

The p-channel MISFETs QP1 and Qpa constituting the peripheral circuit are provided on the main surface of the p-type semiconductor substrate 1 in a region surrounded by the element isolation insulating film 100, as shown on the right side of FIG. 1B. It is provided on the main surface of the A-shaped well region 2.

The p-channel MISFET Qp has a gate insulating film 1
01, a gate electrode 2B, a pair of p-type semiconductor regions 8 and a pair of p-type semiconductor regions 10 forming a source region and a drain region, and the like.

The p-channel MISFET QP has a gate insulating film 1
05, a gate electrode 32, a pair of p-type semiconductor regions 8 and a pair of p-type semiconductor regions 10 forming a source region and a drain region, and the like.

The gate insulating films 101 and 105 are provided on the main surface of the substrate. The gate insulating films 101 and 105 are
For example, it is composed of a silicon oxide film formed by thermally oxidizing a substrate.

The gate electrode 26 is provided on the gate insulating film 101. The gate electrode 26 is formed by subjecting the first conductive film to a predetermined pattern.

The gate electrode 32 is provided on the gate insulating film 105. The gate electrode 32 is formed by subjecting the second conductive film to a predetermined pattern.

Further, the insulating film 106 is provided on the outer peripheral surfaces of the gate electrodes 2B and 32. By providing the insulating film 106, the dielectric strength voltage at each end of the gate electrodes 26 and 32 can be improved.

Further, the side wall spacer 107 is provided on the side wall of the insulating film 106.

A pair of P-type semiconductor regions 8 forming the source and drain regions of the p-channel MISFETs QP and Qpz are formed using, for example, IX I O13 [
It is formed by implanting B by ion implantation at a concentration of about 1 atoms/cm. Therefore, the pair of p-type semiconductor regions 8 are provided in self-alignment with respect to each of the gate electrodes 26 and 32. There is.

A pair of p° type semiconductor regions 10 forming the source and drain regions of the p-channel MISFET QP and Qpi are formed, for example, by using the insulating film 106 and the sidewall spacer 107 as a mask.
It is formed by implanting B by ion implantation in an amount of about I x 10"[atoms/cm"]. Therefore, the pair of p' type semiconductor regions 10 are provided in self-alignment with the gate electrodes 26 and 32, respectively, with the sidewall spacer 107 interposed therebetween.

Since the source region and the drain region are constructed of the pair of n-type semiconductor regions 8 and the pair of P°-type semiconductor regions 10 in this way, the source region and the drain region have an LDD structure.

A first layer wiring 40 is connected to one of the pair of p° type semiconductor regions 10 of the p-channel MISFET QP1 through a connection hole 50 provided in the insulating film 108. The first layer wiring 40 includes the insulating film 109.
The other side of the second layer wiring 41 is connected through the connection hole 15 provided in the second layer. Therefore, one of the pair of go-type semiconductor regions 9 of the n-channel MISFETQn and one of the p°-type semiconductor regions 10 of the p-channel MISFETQ Pi are electrically connected.

The other of the pair of p° type semiconductor regions 10 of the p channel M I S F E T Q Pg is provided with the absolute R film 10.
The first layer wiring 40 is connected through the connection hole 50 provided in the first layer 8 .

Next, using FIGS. 2A and 2B and FIGS. 6A and 6B (cross-sectional views of main parts showing each manufacturing process of the semiconductor integrated circuit device of Example 2), we will explain the example! A method of manufacturing a semiconductor integrated circuit device will be briefly described.

First, a p" type semiconductor substrate made of single crystal silicon is prepared.

Next, an n° type well region 2 is formed. (typed above)
The IJ region 2 constitutes a field effect transistor Qo+x constituting an MNO8 type EEPROM (7) memory cell, a memory cell selection MISFETQ for driving the field effect transistor Q-, . . . constitutes a peripheral circuit. p
In the regions where channel MISFETs Qp and Qpz are formed, an n
It is formed by implanting type impurities. After this, p-
A mold well region 3 is formed. The p-type well region 3 is formed by implanting a p-type impurity into the main surface of the p-type semiconductor base Fi1 in a region other than the region where the π-type well region 2 is formed.

Next, in the element isolation region, a thick element isolation insulating film 100 is formed by selective oxidation. Also, at the same time, p
A type channel I/flange region 4 is formed. The channel stopper region 4 is formed on the main surface of the p'' type well region 3 under the element isolation insulating film 100 in substantially the same step as forming the element isolation insulating film 100.

Next, as shown in FIGS. 2A and 2B, a clean insulating film 101 is formed. The insulating film 101 is, for example, a silicon oxide film formed by a thermal oxidation method.

Through this process, the first gate insulating film 101 of the field effect transistor QEM that constitutes the memory cell of the EPROM, and the first gate insulating film 101 of the field effect transistor QF1 that constitutes the memory cell of the FLOTOX type EEPROM. film 101, the field effect transistor Q8
The gate insulating film 101 of the memory cell selection MISFETQ□ for driving the memory cell selection M1.5FETQ for driving the field effect transistors Q, l, 1 constituting the memory cell of the MNO8 type EEPROM, . Gate insulation ll1101, n-channel MISFETQn
, gate insulating film 101 of p-channel MISFETQP
Each gate insulating film 101 of I is formed.

Next, a first conductive film 20 is formed on the insulating film 101. The first conductive film 20 is, for example, a polycrystalline silicon film deposited by a CVD method. An n-type impurity such as P is implanted into the polycrystalline silicon film constituting the first conductive film during or after film formation. Thereafter, a silicon nitride film 102 is deposited on the first conductive film by, for example, a CVD method. Then, by sequentially performing predetermined patterning on each of the silicon nitride film 102 and the first conductive film 20, the control gate 22 of the field effect transistor QFH constituting the memory cell of the FLOTOX type EEPROM, MISFETQ for memory cell selection for driving field effect transistor Q5, (7
) Gate electrode 23, MNO8 type EEPROM (7) Gate electrode IiT of the memory cell selection MISFET Q□ for driving the field effect transistor Q that constitutes the memory cell. 24, form the gate electrode 25 of the n-channel MISFETQn and the gate electrode 26 of the p-channel MISFETQP, respectively. In this patterning, only the gate I and width direction are defined for the floating gate 21 of the field effect transistor Q g x that constitutes the memory cell of the EPROM.

Next, an insulating film 103 is formed on the sidewalls of the patterned first conductive film 20 using the patterned silicon nitride film 102 as an oxidation-resistant mask. The insulating film 103 is for improving the withstand voltage at the end of the gate electrode. Therefore, the insulating film 103 may be omitted when the applied voltage is low.

When the applied voltage is low, the step of forming the silicon nitride film 102 and the insulating film 103 can be omitted.

Next, although not shown, the FLOTOX type EEPR
A mask is formed using, for example, a photoresist between the control gates 22 of the OM and in a region other than the region where the FLTOX type EEPROM is formed. After this, 3rd A
As shown in the figure and Fig. 3B, FLOTOX type EEPR
Field effect transistor Q that constitutes the memory cell of OM
In the region where PM and the memory cell selection MISFETQ for driving the field effect transistor are formed, the gate electrode 23, the control gate 22, the silicon nitride film 102, and the insulating film 10 are mainly formed.
3, and using the mask as an impurity implantation mask, an n-type semiconductor region 5 is formed by implanting an n-type impurity. Therefore, the n-type semiconductor region 5 is formed in self-alignment with the control gate 22 and the gate electrode 23 with the insulation film 103 interposed therebetween.

Further, the n-type semiconductor region 5 may be formed before the insulating film 103 is formed.

After this, the mask is removed.

Next, the insulating film 101 not covered by the silicon nitride film 102 and the first conductive film 20 is removed. After this, the silicon nitride film 102 is removed.

Next, a new insulating film 104 is formed. The insulating film 10
4 is formed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate. The silicon oxide film A is formed by, for example, a thermal oxidation method.

In this case, the thickness of the silicon oxide film A formed on the main surface of the substrate is approximately 1 to 2 nm.
form. When the first conductive film is a polycrystalline silicon film containing impurities, propagation oxidation occurs depending on the amount of impurity implanted into the polycrystalline silicon film, so that the first conductive film is formed on the main surface of the substrate. The silicon oxide film A formed on the first conductive film is thicker than the silicon oxide film A. The silicon nitride film is deposited by, for example, a CVD method. The silicon nitride film is formed to have a thickness of 10 to 30 nm. The silicon oxide film B is formed, for example, by thermally oxidizing the silicon nitride film.

Next, the insulating film 104 is removed in the region where the MISFET is to be formed.

Next, as shown in FIGS. 4A and 4B, an insulating film 105 is newly formed in the region where the insulating film 104 has been removed. The insulating film 105 is, for example, a silicon oxide film formed by a thermal oxidation method. In this case, the silicon oxide film B constituting the insulating film 104 is thermally oxidized at the same time as the thermal oxidation for forming the insulating film 105, so that it becomes even thicker.

In addition, as another manufacturing process, after forming the insulating film 104 as a composite film in which a silicon oxide film A and a silicon nitride film are sequentially laminated from the bottom layer on the main surface side of the substrate, the insulating film 105 is newly formed. At the same time, it is also possible to form the silicon oxide film B by thermally oxidizing the silicon nitride film constituting the insulating film 104.

Next, a second conductive film is formed on the insulating films 104 and 105. The second conductive film is, for example,
This is a polycrystalline silicon film deposited in the same manner as the conductive film. After that, the second conductive film is subjected to a predetermined patterning. This patterning results in a field effect transistor Q forming the memory cell of the EPROM. control gate 28 of the FLOTOX type EEPROM, floating gate 29 of the field effect transistor Q constituting the memory cell of the FLOTOX type EEPROM, gate electrode 30゜n of the field effect transistor Q0 constituting the memory cell of the MNO3 type EEPROM. Gate electrode 31 of channel MISFETQn2
．． Gate electrodes 32 of each p-channel MISFET QPi are formed.

Next, the insulation WA not covered with the second conductive film
104 is removed. Through this process, field effect transistors Q, , (7
1 Second gate insulating film 104, FLOTOX type EEPR
Field effect transistor Q that constitutes the memory cell of OM
□ second gate insulating film 1゜4 and tunnel insulating film 104
, and gate insulation [10
Form each of 4. Thereafter, a mask is formed using photoresist or the like in a region other than the region where the field effect transistors Q, composing the EPROM are to be formed.

After this, field effect transistors Q, 1. In the region forming l,
a first conductive film 2 defined only in the gate width direction;
By defining the gate length direction of 0, the field effect transistor Q. A floating gate 21 is formed.

Next, as shown in FIGS. 5A and 5B, a new insulating film 106 is formed. The insulating film 106 is, for example, a silicon oxide film formed by a thermal oxidation method.

The insulating film 106 is a field effect transistor 1□FLOTOX type EEP that constitutes a memory cell of an EPROM.
Field effect transistor Q F N that constitutes the memory cell of ROM? And for the field effect transistor Q□ that constitutes the memory cell of the MNO8 type EEPROM,
This is to improve data retention characteristics, and other M
For ISFETs, this is to improve the dielectric breakdown voltage at the end of the gate electrode.

Next, a pair of n-type semiconductor regions 6 are formed which will form the source region and drain region of the field effect transistor Qll11 constituting the memory cell of the EPROM. The n-type semiconductor region 6 is the field effect transistor Q. In the region where IX1 is formed, for example, I
01″ to I x 10″ [atows/c+*”]
It is formed by implanting a certain amount of As by ion implantation. Therefore, the n-type semiconductor region 6 is formed in self-alignment with the control gate 28. The amount of implantation of this n-type impurity is set to a high concentration so that the electric field at the end of the drain becomes strong, and hot carriers are easily generated.

Thereafter, a pair of n-type semiconductor regions 7 are formed to form the source and drain regions of the n-channel MISFETs Qn and Qn2. The n-type semiconductor region 7 is formed using, for example, 1×10” [a
The n-type semiconductor region 7 is formed in self-alignment with each of the gate electrodes 25 and 32. The amount of type impurity implanted is set at a low concentration to alleviate the electric field at the drain end.
It is set to reduce the generation of hot carriers.

Next, MNO8 type EEPROM (7) l='Jt/Lz
MISFETQ for memory cell selection for driving the field effect transistor Q, p-channel) IJM 5FETQp
A pair of n-type semiconductor regions 8 are formed to form the source and drain regions of QPz and QPz, respectively. The p-type semiconductor region 8 includes the field effect transistor QxH1, the memory cell selection MISFET Q□, and the p-channel M
In the regions where I S F E T Qpz and QP2 are formed, the gate electrode 30 of the field effect transistor and the memory cell selection M I S
For example, using the gate electrode 24 of the FET QH, the gate electrodes 2B and 32 of the p-channel MISFET QP and Qpz, and the insulating film 106 as masks,
It is formed by implanting B by ion implantation in an amount of about X 10 ''l:atoms/cm''. Therefore, the n-type semiconductor region 8 is connected to the gate electrode 30,
It is formed in self-alignment with respect to the gate electrode #M24 and the gate electrodes 26 and 32, respectively. The amount of implantation of this p-type impurity is set to a low concentration in order to relax the electric field at the end of the drain, and to reduce the generation of hot carriers.

Next, a silicon oxide film is deposited over the entire surface by, for example, the CVD method. Thereafter, by anisotropic etching, the deposited silicon oxide film is etched by an amount corresponding to the protective thickness, thereby forming sidewall spacers 107.

Next, the field effect transistors Q IEM, n-channel M I , S F that constitute the memory cell of the EPROM are
A pair of n° type semiconductor regions 9 are formed to form the source and drain regions of ETQn and Qn, respectively.

The Go-type semiconductor region 9 is a field effect transistor Q that constitutes a memory cell of an EPROM. , n-channel MIS
In the regions where FET types Qn and Qn2 are to be formed, As is applied mainly using the insulating film 106 and the sidewall spacer 107 as a mask, for example, about l x 10" to I x 10"l:atoms/am". Therefore, the Go-type semiconductor region 9 is formed by implanting the control gate 28 of the field effect transistor QtN, the gate electrodes 25 and 3 of the n-channel MISFET Qn, and Q10.
1 and are formed in self-alignment with each other.

After this, as shown in FIGS. 6A and 6B, MNO8
The source and drain regions of the field-effect transistor QN11 constituting the memory cell of the type EEPROM, the memory cell selection MISFET Q□ for driving the field-effect transistor, and the P-channel MISFETs QPi and Qpz constituting the peripheral circuit. A pair of p' type semiconductor regions 10 are formed. The p° type semiconductor region 1
0 indicates the field effect transistor Q□, the memory cell selection MISFETQ, and the p-channel MISFET
In the region forming E T Q Pt and Qpa,
Mainly using the insulating film 106 and the sidewall spacer 107 as a mask, for example, I
It is formed by implanting B by ion implantation in an amount of about MISFETQ, for.

gate electrode 24. The p-channel MISFETQ
- Formed in self-alignment with the gate electrodes 26 and 32 of P□ and QP2, respectively.

In this way, the floating gate 21 of the field effect transistor QEH constituting the memory cell of the FPROM
Since the gate insulating film 104 between the gate insulating film 104 and the control gate 28 is not used as a mask for 1'-on implantation, no damage is caused to the gate insulating film 104 due to ion implantation, and the film quality of the gate insulating film 104 is improved. improves.

Also, FLOTOX type EEPROM (7) memo IJ-t'
Since the gate insulating film 104 between the control gate 22 and the floating gate 29 of the field effect transistor Q□ constituting /L/ is not used as a mask for ion implantation, the gate insulating film 104 is not used as a mask for ion implantation. Damage no longer occurs, and the quality of the gate insulating film 104 is improved.

Next, an insulating film 108 is formed over the entire surface. After this, connection holes 50 are formed in the insulating film 108.

Next, a first layer of wiring 40 is formed.

Next, an insulating film 109 is formed. After this, the insulating film 1
09, a connection hole 51 is formed.

Next, a second layer of wiring 41 is formed. The wiring 41 may be formed in the same manner as the wiring 40.

Finally, a final passivation film (not shown) is formed on the wiring 41 and the insulating film 109, thereby completing the semiconductor integrated circuit device of the embodiment (2) shown in FIGS. 1A and 1B.

As explained above, in Example I, the EPROM
Field effect transistor Q1H that constitutes the memory cell of
The second gate insulating film 104 of FLOTOX type EEPR
Field effect transistor Q that constitutes the memory cell of OM
The second gate insulating film 104 and the tunnel insulating film 104 of FN, and the gate insulating film 10 of the field effect transistor Q- constituting the memory cell of the MNO8 type EEPROM.
4 is constructed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate. Since it is possible to form a film, there is no need to form each of the above-mentioned insulating films in separate steps.
FLOTOX type EEPROM, MNO8 type EERPOM
It is possible to simplify the process of manufacturing a semiconductor integrated circuit device equipped with the following.

[Embodiment 2] Next, a semiconductor integrated circuit device according to Embodiment 2 of the present invention will be described with reference to FIG. 7 (a sectional view of a main part showing a schematic configuration of the semiconductor integrated circuit device of Embodiment 2).

As shown in FIG. 7, the semiconductor integrated circuit device of the embodiment
X-type EEPROM (7)) L-mo IJ-1! The first gate insulating film 101 and the tunnel insulating film 111 of the information storage field effect transistor Q0 constituting /Lz are composed of silicon oxide films, and the first gate insulating film 101 and the tunnel insulating film 111 are provided. The insulating film 110 provided on the main surface of the substrate in the region not covered by the gate insulating film 110 is made of a silicon oxide film, and the film thickness of the insulating film 110 is set to be equal to that of the gate insulating film 10.
The first conductive film constitutes a floating gate 22, and the second conductive film constitutes a control gate 29. Furthermore, the thickness of the gate insulating film 101 of the memory cell selection MISFET Q for driving the field effect transistor QFX is greater than the thickness of the gate insulating film 101 on the main surface of the substrate in a region other than the region where the gate insulating film is provided. The thickness of the insulating film provided on the insulating film is increased. Further, the n-type semiconductor region 11 forming the source region and drain region of the field effect transistor Q'FH and the memory cell selection MISFET Q□ is formed before forming the insulating films 101 and 110. It is.

The field effect transistor Q0 and the memory cell selection M1.5 FET Q□ were provided on the main surface of the p'' type semiconductor substrate 1 in a region surrounded by the element isolation insulating film 100.p- It is provided on the main surface of the mold well region 3.

The memory cell selection MISFET Q□ includes a gate insulating film 101, a gate electrode 23, a pair of n-type semiconductor regions 11 forming a source region and a drain region, and the like.

The gate insulating film 101 is provided on the main surface of the substrate. The gate MAl# film 101 is composed of, for example, a silicon oxide film formed by thermally oxidizing a substrate.

Further, an insulating film 110 is provided on the main surface of the substrate around the gate insulating film 101. The insulating film 110 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate. The thickness of the insulating film 110 is greater than the thickness of the gate insulating film 101. The insulating film 110 and the gate insulating flllo1 are formed in the same thermal oxidation process, but the insulating film 11
Since the pair of n-type semiconductor regions 11 are provided below the region where 0 is provided, multiplication oxidation occurs due to the influence of the implanted impurity, and the thickness of the gate insulating film 101 is larger than that of the gate insulating film 101.

The thickness of the insulating film 110 becomes thinner.

The gate electrode 23 is provided on the gate insulating film 101. The gate electrode 23 is formed by subjecting the second conductive film to a predetermined pattern.

One of the pair of n-type semiconductor regions 11 forming the source region and the drain region (the field effect transistor Q□
side) is integrated with one of the pair of n-type semiconductor regions 11 (writing semiconductor region) forming the source region and drain region of the field effect transistor Q F H.

The field effect transistor Q F +1 includes a first gate insulating film 101, a tunnel insulating film 111, a floating gate 22, a second gate insulating film 104, a control gate 29 . A pair of n-type semiconductor regions 11 forming a source region and a drain region are provided.

The first gate insulating film 101 is provided on the main surface of the substrate. The first gate insulating film 101 is.

For example, it is composed of a silicon oxide film formed by thermally oxidizing a substrate.

Further, the insulating film 110 is provided on the main surface of the substrate around the first gate insulating film 101.

The tunnel insulating film 111 includes the memory cell selection M
It is provided on the main surface of the substrate above the n-type semiconductor region 11 (write semiconductor region) that is integrated with one of the pair of n-type semiconductor regions 11 of ISFETQ□. The tunnel insulating film 111 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate. The thickness of the tunnel insulating film 111 is thinner than the thickness of the insulating film 110.

The floating gate 22 is provided from above the first gate insulating film 101 to above the tunnel insulating film 111. The floating gate 22 is formed by subjecting the first conductive film to a predetermined pattern.

The control gate 29 is provided on the floating gate 22 with the second gate insulating film 104 interposed therebetween.

The second gate insulating film 104 is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate.

The control gate 29 is formed by subjecting the second conductive film to a predetermined pattern.

Next, the method for manufacturing the semiconductor integrated circuit device of Example (2) will be described in the eighth example.
This will be explained using FIG. 9 and FIG. 9 (a cross-sectional view of a main part showing a part of the manufacturing process of the semiconductor integrated circuit device of Example 2 for each manufacturing process).

First, after forming each of the n-type well region 2, the p-type well region 3, the p-type channel stopper region 4, and the element isolation insulating film 100, a clean film is applied to the main surface of the substrate (not shown). Form an insulating film. The clean insulating film is, for example, a silicon oxide film formed by thermally oxidizing the substrate.

Next, in the region where the field effect transistor Qps and the memory cell selection MISFETQ are formed,
After forming a mask using a photoresist or the like, for example, As is implanted at about I x 101s [atoms/cm''] by ion implantation to form the n-type semiconductor region 11 .

Next, after removing the mask and removing the clean insulating film, a new insulating film 101 is formed as shown in FIG. The insulating film 101 is formed by, for example, a thermal oxidation method. At this time, since impurities are implanted into the n-type semiconductor region 11, photoenhanced oxidation occurs, and the insulating film 110 is thicker than the insulating film 101 formed in other regions. It is formed on the n-type semiconductor region 11.

Next, the insulating film 110 in the tunnel region is removed. After that, a tunnel insulating film 111 having a thickness thinner than the insulating film 110 is newly added to the area where the insulating film 110 has been removed.
form. The tunnel insulating film 111 is formed by, for example, a thermal oxidation method.

Next, a first conductive film is formed. After that, a silicon nitride film is formed on the first conductive film.

Next, the silicon nitride film and the first conductive film are sequentially subjected to predetermined patterning to form the floating gate 22 and the gate electrode 23, respectively.

Next, as shown in FIG. 9, an insulating film 1.3 is formed on each side wall of the floating gate 22 and the gate electrode 23 using the silicon nitride film as an oxidation-resistant mask.

The insulating film 103 is, for example, a silicon oxide film formed by thermal oxidation.

Next, FIGS. 4A and 4B to 6 of the above-mentioned example summer
By carrying out the steps shown in FIGS. A and 6B and the subsequent steps, the semiconductor integrated circuit device of Example 2 is completed.

As explained above, in the semiconductor integrated circuit device of Example 2, the second gate insulating film 104 of the field effect transistor QrN constituting the memory cell of the FLOTOX type EEPROM and the memory cell of the EPROM are The second gate insulating film 104 of the field effect transistor QtN constituting the memory cell and the gate insulating film 104 of the field effect transistor Q 11 H constituting the memory cell of the MNO8 type EEPROM are each oxidized from the lower layer on the main surface side of the substrate. Silicon film A
By forming a composite film in which silicon nitride film and silicon oxide film B are sequentially laminated, each gate insulating film can be composed of an insulating film formed in the same process. There is no need to form it in the process, and EP
ROM, FLOTOX type EEPROM.

It is also possible to commercialize the manufacturing process of a semiconductor integrated circuit device equipped with an MNO8 type EERPOM.

In addition, since the first gate insulating film 101 of the FLOTOX type E E P ROM (7) is made of a silicon oxide film formed by thermally oxidizing the substrate, the gate insulating film of the MISFET constituting the peripheral circuit and the first Since the gate insulating film 101 of 1 can be composed of an insulating film formed in the same process, there is no need to form each gate insulating film in separate processes, and EPROM, FLOTOX type E
EPROM, MNO8 type EEPROM, and MISFE
The process of manufacturing a semiconductor integrated circuit device including a T can be simplified.

Further, by making the thickness of the insulating film 110 thicker than that of the first gate insulating film 101, the dielectric strength voltage of the insulating film 110 is lower than that of the first gate insulating film 101.
[Example 2] Next, the dielectric strength voltage at the ends of the control gate 22 and the gate electrode 23 can be improved in the gate length direction. The semiconductor integrated circuit device of Embodiment ① of the invention is
This will be explained using FIG. 0 (a cross-sectional view of main parts showing a schematic configuration of the semiconductor integrated circuit device of Example 2).

As shown in FIG. 10, the semiconductor integrated circuit device of Embodiment 2 is an n-channel M I S F E constituting the peripheral circuit in the semiconductor integrated circuit device of Embodiment I or H described above.
The gate insulating film of TQn2A is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate. Also, n-channel MI
The gate insulating film of S F E T Q n2m is composed of a composite film in which a silicon oxide film A', a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate. Note that p-channel MISFET is equivalent to n-channel MISFET.
Since it has basically the same configuration as T, the explanation will be omitted.

The n-channel M I S F E T Q n2A and Qnaa are p~ type wells provided on the main surface of the p'' type semiconductor substrate 1 in a region surrounded by the element isolation insulating film 100. It is provided on the main surface of region 3.

The n-channel MISFETQ niA includes a gate insulating film 104, a gate electrode 33, a pair of n-type semiconductor regions 7 and a pair of n-type semiconductor regions 9 forming a source region and a drain region, and the like. .

The n-channel MISFETQn2. includes a gate insulating film 113, a gate electrode 34, a pair of n-type semiconductor regions 7 and a pair of n-type semiconductor regions 9 forming a source region and a drain region, and the like.

The gate insulating film 104 is provided on the main surface of the substrate. The gate insulating film 104 is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate.

The gate insulating film 113 is provided on the main surface of the substrate. The gate insulating film 113 is composed of a composite film in which a silicon oxide film A', a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate.

The silicon oxide film A' is formed by sequentially laminating the insulating film 101 formed in the steps shown in FIGS. 2A and 2B of the above-mentioned Example I and the insulating film (112) not shown from the bottom layer on the main surface side of the substrate. It is something. The insulating film (112) is made of, for example, a silicon oxide film formed by a thermal oxidation method. Therefore, the thickness of the silicon oxide film A' is the same as that of the silicon oxide film A'.
It is thicker than the film thickness of . In this way, the gate insulating film 113 is formed by forming the silicon oxide film A from the lower layer on the main surface side of the substrate.
The thickness of the gate insulating film 113 is the same as that of the gate insulating film 10 because it is constructed by sequentially laminating a silicon oxide film A', a silicon nitride film, and a silicon oxide film B, which are thicker than the gate insulating film 10.
It is thicker than the film thickness of No. 4. The gate insulating film 11
By making the film thickness of No. 3 thicker than the film thickness of the gate insulating film 104, the dielectric breakdown voltage of the gate insulating film 113 becomes larger than that of the gate insulating film 104, so that the n-channel MISFE T The threshold voltage of Qnza is the n-channel MI S F E TQn
, A becomes higher than the threshold voltage of A.

The gate electrode 33 is provided on the gate insulating film 104. The gate electrode 33 is formed by subjecting the second conductive film to a predetermined pattern.

The gate electrode 34 is provided on the gate insulating film 113. The gate electrode 34 is formed by subjecting the second conductive film to a predetermined pattern.

Here, when the voltage applied to the gate electrodes 33 and 34 is large, the insulating films 104 and 113 act as charge storage films, but the M I constituting the peripheral circuit
When used as the gate insulating film of S FET, the voltage applied to the gate electrodes 33 and 34 is small, so
The gate insulating films 104 and 113 do not function as charge storage films, but can be used as gate insulating films.

Next, using FIGS. 11 and 12 (principal cross-sectional views showing a part of the manufacturing process of the semiconductor integrated circuit device of Example (2) for each manufacturing process), the semiconductor integrated circuit device of Example (2) was manufactured. The method will be briefly explained.

First, FIGS. 2A, 2B, and 3A of the above-mentioned Example I
Each of the steps shown in the figure and FIG. 3B is performed in sequence. After this,
In order to form the insulating film 113, a silicon oxide film 112 is formed by a thermal oxidation method.

Next, as shown in FIG.
The insulating film 112 is removed in a region other than the region where QntA is to be formed, that is, the region where the insulating film 113 is to be formed.

Next, as shown in FIG.
form each.

Thereafter, the steps shown in FIGS. 5A and 5B, FIGS. 6A and 6B, and subsequent steps are performed to complete the semiconductor integrated circuit device of Example 2.

As explained above, according to Example 2, n-channel M
The gate insulating film 104 of ISFETQn2A is made of EPRO
Field effect transistor Qg that constitutes the memory cell of M
n second gate insulating film 104, FLOTOX type E
A second gate insulating film 104 of a field effect transistor Qrx that constitutes a memory cell of a P ROM, and a field effect transistor Q that constitutes a memory cell of an MNOS type EEPROM. By having the same structure as the gate insulating film 104 of H, each gate insulating film can be formed with an insulating film formed in the same process, so there is no need to form each gate insulating film in separate processes. is gone, E
PROM, FLOTOX type EEPROM, MNOS type E
The process of manufacturing a semiconductor integrated circuit device including an EPROM and a MISFET can be simplified.

Furthermore, by making the thickness of the gate insulating film 113 of the n-channel MISFET Qnzi thicker than that of the gate insulating film 104 of the n-channel MISFET Qn, the dielectric strength voltage of the gate insulating film 113 is lower than that of the gate insulating film 1.
Since the withstand voltage is higher than that of 04, n-channel MI
Let the threshold voltage of SFETQn, , be the n-channel MI
It can be made larger than the threshold voltage of S F E TQn2A.

[Example ■] Next, the semiconductor integrated circuit device of Example ■ of the present invention was tested in the thirteenth example.
This will be explained using a figure (a sectional view of a main part showing a schematic configuration of a semiconductor integrated circuit device of Example 2).

As shown in FIG. 13, the semiconductor integrated circuit device of Example (2) is similar to the semiconductor integrated circuit device of Example I or (2) described above; An insulating film 116 between the floating gate 29 and the f-type well region 3, a tunnel insulating film 116 between the floating gate 29 and one of the pair of n-type semiconductor regions 5 (semiconductor region for writing), and an n-type film constituting the peripheral circuit. Channel MISFET
The gate insulating WA11B of Qn, respectively, is made of a silicon oxide film formed in the same process.

Also, the upper surface of the control gate 22 of the field effect transistor Q□ and the field effect transistor QF
MISFET Q□ for memory cell selection to drive X
A second gate insulating film 115 is provided only on the upper surface of the gate electrode 23, in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B' are sequentially laminated from the bottom layer on the main surface side of the substrate.

Also, it is not equipped with MNO8 type EEPROM.

The memory cell selection MISFET Q□ includes a gate insulating film 101, a gate electrode 23, a pair of n-type semiconductor regions 5 forming a source region and a drain region, and the like.

A second gate insulating film 115 is provided on the upper surface of the gate electrode fi23. The second gate insulating film 11
5 is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B' are sequentially laminated from the bottom layer on the main surface side of the substrate.

The silicon oxide film B' is composed of a silicon oxide film formed by thermal oxidation, for example.

The field effect transistor QP11 includes a first gate insulating film 101, a control gate 22, an insulation [116] between the p-type well region 3, and the floating gate 29.
, a bloating gate 29 and a pair of n-type semiconductor regions 5
tunnel insulating film 1 between one side (writing semiconductor region) of
16, second gate insulating film 115, floating gate 29, a pair of n layers forming a source region and a drain region
It includes a type semiconductor region 5 and the like.

The insulating film 116 is made of, for example, a silicon oxide film formed by thermally oxidizing the substrate.

The second gate insulating film 115 is provided on the upper surface of the control gate 22.

n-channel MISFETQn2 that constitutes the peripheral circuit
is the gate insulating film 116. It includes a gate electrode 33, a pair of n-type semiconductor regions 7 and a pair of n-type semiconductor regions 9 forming a source region and a drain region, and the like.

The gate insulating film 116 is provided on the main surface of the substrate. The gate insulating film 116 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate.

Next, using FIGS. 14 and 15 (principal cross-sectional views showing a part of the manufacturing process of the semiconductor integrated circuit device of Example (2) for each manufacturing process), the semiconductor integrated circuit device of Example (2) was manufactured. The method will be briefly explained.

First, after the steps shown in FIGS. 2A and 2B of Example I described above, a first conductive film is formed using, for example, a deposited polycrystalline silicon film. Thereafter, a silicon oxide film A and a silicon nitride film are sequentially laminated on the first conductive film to form an insulating film 114. After that, the insulating film 114 and the first conductive film are sequentially subjected to predetermined patterning, and the FLOT
The control gate 22 of the field effect transistor Q□ constituting the memory cell of the OX type EEPROM and the gate electrode 23 of the memory cell selection MISFET QFffi for driving the field effect transistor QFN are formed.

Next, as shown in FIG. 14, an insulating film 103 is formed by thermal oxidation on the sidewall of the patterned first conductive film using the silicon nitride film constituting the insulating film 114 as an oxidation-resistant mask. .

and at least five said field effect transistors Q.
After removing the insulation vA101 in the pw channel forming region, the tunnel insulating film forming region, and the region forming the element whose gate electrode is made of the second conductive film, as shown in FIG. In the region where the insulating film 101 has been removed, a new insulating film 116 is formed by, for example, thermal oxidation. At this time, a silicon oxide film B' is formed on the silicon nitride film of the insulating film 114 by thermal oxidation during the formation of the insulating film 116, and an insulating film 115 is formed at the same time.

Next, FIGS. 5A and 5B, and 6A of the above-mentioned Example I.
The semiconductor integrated circuit device of Example (2) is completed by performing the steps shown in FIG. 6B and FIG. 6B, respectively, and the subsequent steps.

As explained above, according to Example 2, after the silicon oxide film A and the silicon nitride film are sequentially stacked on the first conductive film, a mask is formed, and this mask is used to stack the silicon nitride film. By sequentially patterning each of the silicon oxide film A and the first conductive film, there is no need to pattern each film using separate masks. Type EERO
The process of manufacturing a semiconductor integrated circuit device including M and MISFET can be simplified.

Furthermore, the insulating film 116 and tunnel insulating film 116 between the floating gate 29 of the field effect transistor Q 711 and the p-type well region 3 constituting the memory cell of the FLOTOX type EEPROM, and the n-channel MIS F E
By forming each of the gate insulating films 116 of T Q n2 with a silicon oxide film formed in the same process, there is no need to form each insulating film in separate processes, and EP
ROM, FLOTOX type EEPROM and MISFET
In the semiconductor integrated circuit device equipped with the present invention, it is possible to simplify the process.

Further, in Example 2, the insulating film 116 and the tunnel insulating film 116 between the floating gate 29 of the field effect transistor QFM constituting the memory cell of the FLOTOX type EEPROM and the p'' type well region 3, and the n-channel M
Although an example has been shown in which the gate insulating film 116 of ISFETQn2 is formed at the same time, it is also possible to form this in a separate process. In this case, for example, first, the insulating film 116 is formed in the region where both elements are to be formed, and then the insulating film 116 is removed in the region where the field effect transistor Q is to be formed. In the region from which the insulating film 116 has been removed, an insulating film and a 1-channel insulating film between the floating gate 29 and the p-type well region 3 may be formed by thermal oxidation again. In this way, by forming in a separate process, for example, n-channel M
The thickness of the gate insulating film of ISFET Qn2 is set to be the same as that of the floating gate 29 of the field effect transistor Q.
The dielectric breakdown voltage of the gate insulating film of the n-channel MISFET Qn2 can be set arbitrarily because the thickness can be made thicker than that of the insulating film 116 and the tunnel insulating film 116 between the type well region 3 and can be made to any desired thickness. The threshold voltage can be set arbitrarily.

Further, the manufacturing method shown in FIGS. 14 and 15 is based on Example 1.
1 (7) FLOTOX type EEPROM (7) Applied as is to the process of forming the field effect transistor Q F N constituting the memory IJ cell and the memory cell selection MISFET QPfi for driving the field effect transistor Q□. You can also do that.

[Example ■] Next, the semiconductor integrated circuit device of Example ■ of the present invention was
This will be explained with reference to FIG. 6 (a cross-sectional view of main parts showing a schematic configuration of the semiconductor integrated circuit device of Example 2).

As shown in FIG. 16, the semiconductor integrated circuit device of Embodiment V is similar to the semiconductor integrated circuit device of Embodiment ① or ① described above, and includes a field effect transistor Q F H constituting a memory cell of a FLOTOX type EEPROM. One of the two divided control gates 22 and a memory cell selection M for driving the field effect transistor QPN.
The gate electrodes 23 of ISFETQ and Y are provided in self-alignment with respect to the floating gate 29 of the field effect transistor Q□.

Next, a method for manufacturing the semiconductor integrated circuit device of Example 2 will be briefly described.

First, after the steps shown in FIGS. 2A and 2B of the above-mentioned Example I, the first lead 'fI! Forms a film. After that, a silicon nitride film is deposited on the first conductive film, and an insulating film 10 is formed.
form 2.

Next, predetermined patterning is sequentially applied to each of the insulating film 102 and the first conductive film. By this patterning, one of the control gates 22 of the field effect transistor QI (the memory cell selection MISFET Q) constituting the memory cell of the FLOTOX type EEPROM is
, , side), both the gate width direction and the gate length direction are defined. Further, the other of the control gates 22 of the field effect transistor QFN is an MIS for selecting a memory cell for driving the field effect transistor QFX.
The gate electrode 23 of FETQ, , field effect transistor Q that constitutes the memory cell of EPROM. First, only the gate width direction of each of the control gates 21 is defined.

Note that the other control gate 22 also defines the gate length direction only on the channel forming region side. Further, the gate electrode 23 also defines the gate length direction only on the side where the tunnel insulating film is formed.

Next, a mask is formed between the control gates 22 using photoresist or the like. After that, in the region where the field effect transistor QF II and the memory cell selection MISFET QFI are to be formed, the patterned insulating film 102 and the mask are mainly used as a mask for impurity implantation. For example, n-type impurities are implanted by ion implantation to form an n-type semiconductor region 5 (semiconductor region for writing) forming a tunnel region.
form.

Next, a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate to form an insulation 104.

After this, a second conductive film is formed on the insulating film 104.

Next, a mask is formed using photoresist or the like on the second conductive film. Thereafter, each of the second conductive film, the insulating film 104, and the first conductive film is subjected to predetermined patterning using the mask. Through this patterning, the field effect transistor Q constituting the memory cell of the EPROM is defined only in the gate width direction in the above-described process. floating gate 21,
The gate length direction of the other control gate 22 of the field effect transistor Q F Therefore, by this patterning, the field effect transistor Q is formed. control gate 28 and floating gate 21 of the field effect transistor Q r x
Bloating gate 29 and control gate 22
, the gate electrode 23 of the memory cell selection Ml5FETQ□ is formed.

Next, the insulating film 106 is formed by thermal oxidation.

Thereafter, in the region where the field effect transistor Q F N and the memory cell selection MISFET Q, 11 are formed, an n-type impurity, for example, As, is introduced mainly using the control gate 29 and the insulating film 106 as a mask for impurity introduction. An n-type semiconductor region 12 is formed by implantation by ion implantation.

Next, by performing the steps shown in FIGS. 6A and 6B of the above-mentioned Example I and the subsequent steps, Example
The semiconductor integrated circuit device is completed.

As explained above, according to Example ①, FLOTOX
The control gate 22 and the gate electrode 23 of the memory cell selection MISFET Qpa are connected to the floating gate 1-29 of the field effect transistor QFH constituting the memory cell of the type EEPROM. Since it can be formed by self-alignment, the element size can be reduced by the size equivalent to the mask alignment margin, etc.
FLOTOX type EEPROM, MNOS type EEPROM
, and a semiconductor integrated circuit device including MISFET can be highly integrated.

[Example 2] Next, the semiconductor integrated circuit device of Embodiment 2 of the present invention was
This will be explained with reference to FIG. 7 (a sectional view of main parts showing a schematic configuration of the semiconductor integrated circuit device of Example 2).

As shown in FIG. 17, the semiconductor integrated circuit device of Example 2 is the same as that of Example 1 described above! or p-channel MISFETQPt constituting the peripheral circuit in the semiconductor integrated circuit device of
In a region defined by a pair of p-type semiconductor regions 10 forming a source region and a drain region of QP2, a pair of n-type semiconductor regions 8 are formed below a pair of p-type semiconductor regions 8 forming a source region and a drain region. A semiconductor region 13 is provided.

Note that the p-channel MISFET Qp has basically the same structure as the p-channel MISFET Qp2, so a description thereof will be omitted.

The p-channel MISFET Qpa includes a gate insulating film 105, a gate electrode 32, a pair of p-type semiconductor regions 8 forming a source region and a drain region, a pair of p°-type semiconductor regions 10, and the like. . Furthermore, in a region defined by the pair of p-type semiconductor regions 10, a pair of n-type semiconductor regions 13 are provided below the pair of p-type semiconductor regions 8.

The pair of n-type semiconductor regions 13 are formed by, for example, I
X 10" to I X 1013 [atoms/cmz
Accelerating P of about 1 with energy of 100 to 150 [KeV]
It is formed by implantation using ion implantation. Therefore, the n-type semiconductor region 13 is provided in self-alignment with the gate electrode 32.

Next, using FIGS. 18 and 19 (principal cross-sectional views showing a part of the manufacturing process of the semiconductor integrated circuit device of Example (2) for each manufacturing process), the semiconductor integrated circuit device of Example (2) was manufactured. The method will be briefly explained.

First, a π-type well region 2, a p''-type well region 3, a P-type channel stopper region 4, and an element isolation insulating film 100 are formed.After this, although not shown, a clean insulating film is formed on the main surface of the substrate. Forms a film.

Next, on the main surface of the substrate in the area where the MISFET is to be formed,
Channel ions for threshold voltage adjustment are implanted.

Next, the clean insulating film is removed. Thereafter, the steps shown in FIGS. 2A and 2B to 5A and 5B of Example I described above are performed.

Next, as shown in FIG.
A pair of n-type semiconductor regions 7 are formed in the region where Qn is to be formed.

At the same time, the pair of n-type semiconductor regions 7 are also formed in the region where the p-channel MISFET QP2 is to be formed. Note that the pair of n-type semiconductor regions 7 do not necessarily have to be formed in the region where the P-channel MISFET is to be formed in this step.

Next, as shown in FIG.
In the region where E T Q P2 is to be formed, a pair of n-type semiconductor regions 13 and a pair of p-type semiconductor regions 8 are sequentially formed. Note that it is also possible to reverse the order in which the pair of n-type semiconductor regions 13 and the pair of p-type semiconductor regions 8 are formed.

The pair of n-type semiconductor regions 8 are formed by implanting B, for example, about I x 10"[atoms/Cm"] by ion implantation, mainly using the gate electrode 31 and the insulating film 106 as a mask for impurity implantation. do. In this case, the implantation amount is set to an amount that, if an n-type semiconductor region has been formed in the previous step, converts it into a p-type semiconductor region.

The n-type semiconductor region 13 is formed using the gate electrode 31 and the insulating film 106 as a mask for impurity implantation, for example, I x 1012 to I x 10'' [atoms/
Acceleration energy of P of cm” is 100~l 50 [
KeV] by ion implantation.

After that, by carrying out the steps shown in FIGS. 6A and 6B of the above-mentioned Example (2) and the subsequent steps, Example (2)
The semiconductor integrated circuit device is completed.

As explained above, according to the embodiment (2), a pair of n-type semiconductor regions 8 that act as punch-through stoppers are formed under a pair of n-type semiconductor regions 8 of a p-channel MISFET constituting a peripheral circuit.
By providing the type semiconductor region 13, punch-through does not occur even when the channel length becomes small, so that the P-channel MI 5FET can be miniaturized.

In addition, since the gate insulating film of the n-channel MISFET that constitutes the peripheral circuit is formed after channel ion implantation, the channel impurities are heat-treated in the oxidizing atmosphere during the formation of the gate insulating film, and are buried deep in the substrate in the source and drain regions. A region with a high concentration of p-type impurity is formed in a region extending from near the main surface of the substrate to the bottom of a pair of n-type semiconductor regions, forming a source region and a drain region. Since the expansion of the depletion layer formed between the pair of n-type semiconductor regions 9 and the p-type well region 3 that form the p-type well region 3 is suppressed, punch-through does not occur.
It is possible to miniaturize the n-channel MISFET.

Furthermore, by forming the gate insulating film of the MISFET that constitutes the peripheral circuit after channel ion implantation, there is no deterioration in the film quality of the gate insulating film due to channel ion implantation, so it is possible to improve the dielectric strength voltage of the gate insulating film. .

[Example 2] Next, the semiconductor integrated circuit device of Example 2 of the present invention was tested in the 20th embodiment.
This will be explained using a figure (a sectional view of a main part showing a schematic configuration of a semiconductor integrated circuit device of Example 2).

As shown in FIG. 20, the semiconductor integrated circuit device of Example 2 is the semiconductor integrated circuit device of Example I described above, further comprising a DRAM on the same substrate.

The DRAM includes a memory cell constituted by a series circuit of a memory cell selection MISFET Q, A, and an information storage capacitive element Q0°.

The information storage capacitive element Q0° is a p-type semiconductor substrate 1
The p-type well region 3 is provided on the main surface of the p-type well region 3 .

The information storage capacitive element Q. . is the first electrode n
It includes a type semiconductor region 5, an insulating film 104 which is a dielectric film, a conductive film 36 which is a second electrode, and the like.

The n-type semiconductor region 5, which is the first electrode, is provided on the main surface of the substrate. The n-type semiconductor region 5 is integrated with one of a pair of n-type semiconductor regions 5 forming the source region and drain region of the memory cell selection MISFET QoT. In this way, the memory cell selection M
The ISFET QoT and the information storage capacitive element Qoc constitute a series circuit. The n-type semiconductor region 5 is FLO
Field effect transistors Q and H constituting the memory cells of the TOX type EEPROM and a memory cell selection MISFET for driving the field effect transistor QFM.
It is formed in the same step as the step of forming the n-type semiconductor region 5 which forms the source region and drain region of Q□.

The insulating film 104, which is the dielectric film, extends from the main surface of the substrate,
It is provided so as to extend above the element isolation insulating film 100 . The insulating film 104 is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide film B are sequentially laminated from the bottom layer on the main surface side of the substrate.

The conductive film 36, which is the second electrode, is connected to the insulating film 104.
is placed on top of. The conductive film 36 is a plate electrode. The conductive film 36 is obtained by subjecting the second conductive film to a predetermined pattern.

The memory cell selection MISFETs Q and T are connected to a p'' type well region 3 provided on the main surface of the p- type semiconductor substrate 1.
is provided on the main surface of the

The memory cell selection MI S FET QDT has a gate insulating film 101. It includes a gate electrode 35, a pair of n-type semiconductor regions 5 forming a source region and a drain region, and the like.

The gate insulating film 101 is provided on the main surface of the substrate. The gate insulating film 101 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate.

The gate electrode 35 is provided on the gate insulating film 101. The gate electrode 35 is formed by subjecting the first conductive film to a predetermined pattern.

The n-type semiconductor region 5 forming the source region and the drain region is mainly formed by the gate electrode 32 and the Ma film 106.
It is formed by implanting n-type impurities using as a mask. Therefore, the n-type semiconductor region 5 is provided in self-alignment with the gate electrode 32. Further, the n-type semiconductor region 5 is a FLOTOX type EERPO.
A field effect transistor Q constituting a memory cell of M,
and the field effect transistor Q, formed in the same step as the step of forming a pair of n-type semiconductor regions 5 that form the source region and drain region of the memory cell selection MISFET Qys for driving the field effect transistor Q. has been done.

As explained above, according to the embodiment (2), the DRAM can be formed in the process of forming the semiconductor integrated circuit device of the above-mentioned embodiment (2), so the DRAM can be formed without increasing the number of steps.
RAM can be mounted on the same board.

Also, the information storage capacitive element Q. It is also possible to configure the dielectric film of C with the insulating film 116 shown in Example (2). [Example (2)] Next, the semiconductor integrated circuit device of Example (2) of the present invention will be described in the twenty-first embodiment.
This will be explained using a figure (a sectional view of a main part showing a schematic configuration of a semiconductor integrated circuit device of Example 2).

The semiconductor integrated circuit device of Example (2) is obtained by mounting a DRAM on the semiconductor integrated circuit device of Example H shown in FIG.

The DRAM has a memory cell selection MISFET Q
o- and an information storage capacitive element Q. It is equipped with a memory cell composed of a series circuit of C.

The information storage capacitive element Qoc has a first electrode n
type semiconductor region 11, an insulating film 111 which is a dielectric film, and a second
A conductive film 37, which is an electrode, is provided.

The semiconductor region 11, which is the first electrode, is a pair of go-shaped semiconductor regions 9 that form the source region and drain region of the memory cell selection M, ISFETQoT.
It is integrated with one side. The n-type semiconductor region 11 is formed by forming the insulating film 101 as described in the above-mentioned embodiment (2).
It was formed in a step before forming the .

The insulating film 111, which is the dielectric film, is provided on the main surface of the substrate. The precursor insulating film 111 is composed of, for example, a silicon oxide film formed by thermally oxidizing a substrate. The insulating film 111 is formed in the same process as the tunnel insulating film 111 of the FLOTOX type EEPROM.

The insulating film 111 is composed of a silicon oxide film formed by removing the insulating film 101 and thermally oxidizing the substrate in the removed region. Further, the film thickness of the insulating film 111 is the same as that of the information storage capacitive element Q. It is thinner than the film thickness of the insulating film 110 provided on the main surface of the substrate between C and the memory cell selection MISFET Q0a.

The conductive film 37, which is the second electrode, is connected to the insulating film 111.
is placed on top of. Further, the conductive film 37 is extended from above the insulating film 111 to above the element isolation insulating film 100. The conductive film 37 is a single note electrode. The conductive film 37 is obtained by performing predetermined patterning on the first conductive film.

Further, a conductive film 38 is provided on the conductive film 37 on the element isolation insulating film 100 with the insulating film 104 interposed therebetween. This conductive film 38 is a word line.

The memory cell selection MISFET Q,A includes a gate insulating film 105, a gate electrode 38, a pair of n-type semiconductor regions 7 and a pair of n°-type semiconductor regions 9 forming a source region and a drain region, and the like.

The gate insulating film 105 is provided on the main surface of the substrate. The gate insulating film 105 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate. The insulating film 105 is an n-channel MI constituting a peripheral circuit.
It is formed in the same process as the process of forming the gate insulating film 105 of SFETQn and Qpa.

The gate electrode 38 is provided on the gate insulating film 105. The gate electrode 38 is formed by subjecting the second conductive film to a predetermined pattern.

The information storage capacitive element Q. , and the memory cell selection MISFETQ, on the main surface of the substrate.

The insulating film 110 is provided. The insulating film 110
is composed of a silicon oxide film formed by, for example, thermally oxidizing the substrate after forming the n-type semiconductor region 11. The insulating film 110 is formed at the same time as the insulating film 101, but since impurities are implanted into the n-type semiconductor region 11, propagation oxidation occurs due to the influence of the implanted impurities. and the above n
The thickness of the insulating film 110 formed on the type semiconductor region 11 is greater than the thickness of the insulating film 101.

As explained above, according to Example 2, the DRA is
Since M can be formed, a DRAM can be provided on the same substrate without increasing the number of steps.

Also, the information storage capacitive element Q. By configuring the insulating film 111, which is the dielectric film of C, with an insulating film (tunnel insulating film 111) thin enough to allow a tunnel current to flow, the unit of the dielectric film of the information storage capacitive element Q0° is Since the capacitance per area is large, the information storage capacitive element Q. The element size of C can be reduced.

[Example 2] Next, the semiconductor integrated circuit device of Embodiment 2 of the present invention was
This will be explained with reference to FIG. 2 (a sectional view of main parts showing a schematic configuration of the semiconductor integrated circuit device of Example 2).

As shown in FIG. 22, the semiconductor integrated circuit device of Example (2) is different from D in the semiconductor integrated circuit device of Example (2) described above.
The information storage capacitive element Q0° of the RAM has a stacked structure.

The information storage capacitive element Q. The conductive film 37 is a first electrode, and the insulating film 104 is a dielectric film. A conductive film 39, which is a second electrode, etc. are provided.

The conductive film 37, which is the first electrode, is extended from above the n-type semiconductor region 5 to above the element isolation insulating film 100. The conductive film 37 is obtained by performing predetermined patterning on the first conductive film. The conductive film 37 is obtained by performing predetermined patterning on the first conductive film.

The conductive film 37 is electrically connected to the n-type semiconductor region 5.

The conductive film 39, which is the second electrode, is provided on the conductive film 37 with the insulating film 104, which is the dielectric film, interposed therebetween. The conductive film 39 is obtained by subjecting the second conductive film to a predetermined pattern.

The insulating film 104, which is the dielectric film, is composed of a composite film in which a silicon oxide film A, a silicon nitride film, and a silicon oxide gB are sequentially laminated from the bottom layer on the main surface side of the substrate.

As explained above, according to the embodiment (2), the information storage capacitor Q of the memory cell of the DRAM is manufactured by the same process as that of manufacturing the semiconductor integrated circuit device of the above-mentioned embodiment (2).
Dc can be made into a stacked structure.9 Furthermore, in Example 2, in the semiconductor integrated circuit device of Example 2 described above, the information storage capacitive element Q. Although an example has been shown in which C has a stacked structure, it is also possible to have the information storage capacitive element Qoc in a stacked structure in the semiconductor integrated circuit device of the above-described embodiment (2).

In this case, the first electrode is composed of the n-type semiconductor region 11 and the conductive film 37, the dielectric film is composed of the insulating film 104, and the second electrode is composed of the conductive film 39. Just configure it.

Further, the first electrode 37 is used as a plate electrode,
It is also possible to provide the second electrode 39 so as to be directly connected to one of the pair of n-type semiconductor regions.

Also, M I S F E T Qot for memory cell selection
It is also possible to construct the gate electrode by performing predetermined patterning on the second conductive film.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in this actual flow side I to (2), an example was shown in which the insulating film was composed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film were sequentially laminated from the bottom layer on the main surface side of the substrate. It is also possible to configure the film as a composite film in which a silicon oxide film and a transition metal oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate.

Furthermore, although an example is shown in which one type of p-type well region and one type of n-type well region are provided, the invention is not limited to this, and different types of well regions with different impurity concentrations or depths may be provided for each element. It is also possible to provide It is also possible to provide a region in the semiconductor substrate in which no well region is formed, and to form elements in this region.

It is also possible to configure the semiconductor substrate to be of n-type.

Furthermore, although an example has been shown in which the MNO5 type EEPROM is configured as a P-channel type, it is also possible to form an N-channel type by forming it on the main surface of a p-type well region formed on the main surface of an n-type semiconductor substrate. .

Also, using the conductive film as a resistor for analog processing,
Alternatively, it is also possible to use the interlayer insulating film as a capacitor for analog processing.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device equipped with an EPROM and an MNO8 type EEPROM, it is possible to thin each of the gate insulating film between the floating gate and the control gate of the EPROM and the gate insulating film having the charge storage part of the MNOS type EEPROM. can.

Further, in the semiconductor integrated circuit device, the data retention characteristics of the EPROM and the MNO3 type EEPROM can be improved.

In addition, the EPRO'M and MNO8 type EEPROM
In a semiconductor integrated circuit device equipped with the present invention, high integration can be achieved.

Further, in a semiconductor integrated circuit device equipped with the EPROM and the MNO8 type EEPROM, the process can be simplified.

In a semiconductor integrated circuit device comprising an EPROM and a FLOTOX type EEPROM, a gate insulating film between a floating gate and a control gate of the EPROM;
Each of the tunnel insulating films of the FLOTOX type EEPROM can be made thinner.

Further, in a semiconductor integrated circuit device equipped with the EPROM and FLOTOX type EEPR○M, the process can be simplified.

In a semiconductor integrated circuit device comprising an EPROM, an MNO8 type EEPROM, and a FLOTOX type EEPROM, a gate insulating film between a floating gate and a control gate of the EPROM, and a gate insulating film of the MNOS type EEPROM are provided.
The gate insulating film of the FLOTOX type EEPROM and the tunnel insulating film of the FLOTOX type EEPROM can each be made thinner.

Moreover, the above EPROM, MNO8 type EEPROM and FLO
In a semiconductor integrated circuit device equipped with a TOX type EEPROM, the process can be simplified.

In a semiconductor integrated circuit device equipped with MISFET, EPROM, MNO8 type EEPROM or FLOTOX type EEPROM'&, the process can be simplified.

[Brief explanation of drawings]

1A and 1B are main part sectional views showing a schematic configuration of a semiconductor integrated circuit device according to Embodiment I of the present invention, and FIGS. 2A and 2B to 6A and 6B are FIG. 7 is a cross-sectional view of a main part showing the semiconductor integrated circuit device of Example H of the present invention at each manufacturing process; FIG. 9 is a cross-sectional view of a main part showing a part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment (2) of the present invention, for each manufacturing process, and FIG. 10 is a schematic diagram of the semiconductor integrated circuit device according to the embodiment (2) of the present invention. 11 and 12 are cross-sectional views of main parts showing each manufacturing process a part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment (2) of the present invention. FIG. 13 is a cross-sectional view of main parts showing a schematic configuration of a semiconductor integrated circuit device according to the embodiment (2) of the present invention, and FIG. 14 and FIG. 16 is a cross-sectional view of the main parts showing a schematic configuration of a semiconductor integrated circuit device according to the embodiment (2) of the present invention; FIG. FIGS. 18 and 19 are cross-sectional views of main parts showing a schematic configuration of a semiconductor integrated circuit device according to Example 2 of the present invention. FIGS. 20 is a cross-sectional view of a main part showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment (2) of the present invention, and FIG. Partial sectional view. FIG. 22 is a sectional view of a main part showing a schematic configuration of a semiconductor integrated circuit device according to Example 2 of the present invention. In the figure, 1...p-type semiconductor substrate, 2...n-type well region, 3...p-type well region, 5, 6.7...
n-type semiconductor region, 8...p-type semiconductor region, 9...n
° type semiconductor region, 10... p ° type semiconductor region, 21
, 29...Floating gate, 22.28...
・Control gate, 23, 24. 25, 26° 30
．． 31, 32... Gate electrode, 100... Inter-element isolation insulating film, 101.104, 105, 106... Insulating film. Figure 10 1 (F) Figure 11 Figure 12 Figure 1 (F)

Claims (1)

[Claims] 1. An EPROM in which a memory cell is formed by a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a gate electrode is provided on the gate insulating film having a charge storage portion. In a semiconductor integrated circuit device equipped with an EEPROM in which a memory cell is constituted by a field effect transistor provided, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, and a charge storage portion of a memory cell of the EEPROM. 1. A semiconductor integrated circuit device characterized in that a gate insulating film having a gate insulating film is composed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate. 2. An EPROM in which a memory cell is composed of a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a memory cell in an EPROM in which a field effect transistor is provided in which a floating gate is provided on a tunnel insulating film. In a semiconductor integrated circuit device equipped with an EEPROM, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM and a tunnel insulating film of a memory cell of the EEPROM are oxidized from a lower layer on the main surface side of the substrate. A semiconductor integrated circuit device comprising a composite film in which a silicon film, a silicon nitride film, and a silicon oxide film are sequentially laminated. 3. An EPROM in which a memory cell is composed of a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a field effect transistor in which a gate electrode is provided on a gate insulating film having a charge storage section. EEPROM, in which the memory cell is made up of , and EEPROM, in which the memory cell is made up of a field effect transistor, which has a floating gate on a tunnel insulating film.
In the semiconductor integrated circuit device comprising the EPROM
a gate insulating film between the floating gate and the control gate of the memory cell of the EEPROM, a gate insulating film having a charge storage part of the memory cell of the EEPROM, and a gate insulating film having a charge storage part of the memory cell of the EEPROM;
A semiconductor integrated circuit device characterized in that a tunnel insulating film of a memory cell of a ROM is formed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate. 4. An EPROM in which a memory cell is composed of a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a field effect transistor in which a gate electrode is provided on a gate insulating film having a charge storage section. In a semiconductor integrated circuit device comprising an EEPROM constituting a memory cell, and a MISFET having a gate electrode on a gate insulating film, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, A gate insulating film having a charge storage portion of a memory cell and the MISFET
A semiconductor integrated circuit device, characterized in that the gate insulating film is constituted by a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate. 5. An EPROM in which a memory cell is composed of a field effect transistor in which a control gate is provided with a gate insulating film interposed on a floating gate, and a memory cell in which a field effect transistor in which a floating gate is provided on a tunnel insulating film is constructed. In a semiconductor integrated circuit device comprising an EEPROM and a MISFET having a gate electrode provided on a gate insulating film, a gate insulating film between a floating gate and a control gate of a memory cell of the EPROM, and a tunnel insulation of a memory cell of the EEPROM. A semiconductor integrated circuit device, characterized in that the film and the gate insulating film of the MISFET are composed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate. 6. An EPROM in which a memory cell is composed of a field effect transistor in which a control gate is provided on a floating gate with a gate insulating film interposed therebetween, and a field effect transistor in which a gate electrode is provided on a gate insulating film having a charge storage portion. EEPROM, in which the memory cell is made up of , and EEPROM, in which the memory cell is made up of a field effect transistor, which has a floating gate on a tunnel insulating film.
and a MISFET with a gate electrode provided on the gate insulating film.
In the semiconductor integrated circuit device comprising the EPROM
a gate insulating film between the floating gate and the control gate of the memory cell of the EEPROM, a gate insulating film having a charge storage part of the memory cell of the EEPROM, a gate insulating film having a charge storage part of the memory cell of the EEPROM;
M memory cell tunnel insulating film and the MISFE
1. A semiconductor integrated circuit device characterized in that a gate insulating film of T is formed of a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the bottom layer on the main surface side of the substrate. 7. The semiconductor integrated circuit device according to claim 4, wherein the gate insulating film of the MISFET is made of a silicon oxide film. 8. The semiconductor integrated circuit device according to claim 5, wherein the tunnel insulating film of the memory cell of the EEPROM is thinner than the gate insulating film of the MISFET. 9. The semiconductor integrated circuit device according to claim 1, wherein the composite film is a composite film of a transition metal oxide film and a silicon oxide film.