JPH02296332A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02296332A
JPH02296332A JP11710489A JP11710489A JPH02296332A JP H02296332 A JPH02296332 A JP H02296332A JP 11710489 A JP11710489 A JP 11710489A JP 11710489 A JP11710489 A JP 11710489A JP H02296332 A JPH02296332 A JP H02296332A
Authority
JP
Japan
Prior art keywords
insulating film
layer wiring
interlayer insulating
lower layer
upper layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11710489A
Other languages
Japanese (ja)
Inventor
Naoji Kaneko
直司 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11710489A priority Critical patent/JPH02296332A/en
Publication of JPH02296332A publication Critical patent/JPH02296332A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To flatten the surface of an interlayer insulating film, and flatten also an multilayer wiring layer formed on the interlayer insulating film, by selectively eliminating protruding parts of the interlayer insulating film of the parts where a lower layer wiring and an upper layer wiring intersect each other, and depositing and forming thereon an interlayer insulating film. CONSTITUTION:On the whole surface of an insulating film 2 formed on a semiconductor substrate, e.g. silicon substrate 1, a lower layer wiring film is formed and machined to an arbitrary shape. A lower layer wiring 3 is arranged, and a first interlayer insulating film 4a is formed on the whole surface. By etching, protruding parts of the first interlayer insulating film 4a are selectively eliminated from the intersecting parts of the lower layer wiring 3 and the upper layer wiring 5, e.g. the lower layer wiring 3; a second interlayer insulating film 4b is deposited and formed; thereon an upper layer wiring 5 is formed, thereby forming an interlayer insulating film between the lower layer wiring 3 and the upper layer wiring 5. Hence the surface of the interlayer insulating film can be flattened, processing of the upper layer wiring is facilitated, and a highly reliable semiconductor device wherein disconnection, short, etc., of the upper layer wiring are not present can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野) この発明は、半導体装置の製造方法に係り、特に平坦化
した層間絶縁膜の形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a planarized interlayer insulating film.

(従来技術) 第3図は従来の眉間絶縁膜の形成方法を用いた半導体装
置の断面図である。この図において、1はシリコン基板
、2はこのシリコン基板1上に形成された絶縁膜、3は
この絶縁膜2上に形成された下層配線、4は全面に形成
された層間絶縁膜、5は前記層間絶縁膜4の上に形成さ
れた上層配線である。
(Prior Art) FIG. 3 is a cross-sectional view of a semiconductor device using a conventional method for forming a glabellar insulating film. In this figure, 1 is a silicon substrate, 2 is an insulating film formed on this silicon substrate 1, 3 is a lower layer wiring formed on this insulating film 2, 4 is an interlayer insulating film formed on the entire surface, and 5 is an insulating film formed on the entire surface. This is an upper layer wiring formed on the interlayer insulating film 4.

次に第4図(a)〜(d)によりその形成方法について
説明する。
Next, a method for forming the same will be explained with reference to FIGS. 4(a) to 4(d).

シリコン基板1に形成された絶縁膜2上全面に下層配線
膜3゛を形成しく第4図(a))、これを任意の形状に
加工し、下層配線3を配置する(第4図(b))。
A lower wiring film 3 is formed on the entire surface of the insulating film 2 formed on the silicon substrate 1 (FIG. 4(a)), and this is processed into an arbitrary shape to arrange the lower wiring 3 (FIG. 4(b)). )).

次いで眉間絶縁膜4を下層配線3を含む全面に形成する
。この時、層間絶縁膜4の表面は下層配線3の段差がそ
のまま現れ凹凸の大きな表面となる(第4図(C))。
Next, a glabellar insulating film 4 is formed over the entire surface including the lower wiring 3. At this time, the surface of the interlayer insulating film 4 shows the level difference of the lower wiring 3 as it is and becomes a highly uneven surface (FIG. 4(C)).

さらに、この眉間絶縁膜4上に上層配線5を形成する(
第4図(d))。
Furthermore, upper layer wiring 5 is formed on this glabellar insulating film 4 (
Figure 4(d)).

〔発明が解決しようとする課題) 従来の層間絶縁膜4は、以上のようにして形成されるの
で、眉間絶縁膜40表面の凹凸が大きいため、その上に
形成された上層配線5を加工する際、加工が困難で、か
つ複雑であり、また、層間絶縁膜4の凹凸部での上、下
層配線5,3間士の短絡あるいは断線等が発生しやすい
なとの問題点があった。
[Problems to be Solved by the Invention] Since the conventional interlayer insulating film 4 is formed as described above, the surface of the glabella insulating film 40 has large irregularities, so it is necessary to process the upper layer wiring 5 formed thereon. However, processing is difficult and complicated, and there are problems in that short circuits or disconnections between the upper and lower wirings 5 and 3 are likely to occur at the uneven portions of the interlayer insulating film 4.

この発明は、上記のような問題点を解消するためなされ
たもので、眉間絶縁膜表面を平坦化するとともに、さら
に、上層配線同士の断線、短絡のない半導体装置の製造
方法を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and aims to flatten the surface of the insulating film between the eyebrows and to provide a method for manufacturing a semiconductor device that does not cause disconnection or short circuit between upper layer wirings. shall be.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は、半導体基板上
に配置された下層配線上に層間絶縁膜を形成し、前記下
層配線と交差する部分の前記層間絶縁膜の凸状部を選択
的に除去した後、その上に眉間絶縁膜を堆積形成するこ
とにより、層間絶縁膜表面を平坦化した後、さらにその
上に上層配線を形成する工程により、多層配線構造を形
成するものである。
A method for manufacturing a semiconductor device according to the present invention includes forming an interlayer insulating film on a lower layer wiring arranged on a semiconductor substrate, and selectively removing a convex portion of the interlayer insulating film at a portion intersecting with the lower layer wiring. After that, a multilayer wiring structure is formed by depositing a glabellar insulating film thereon to flatten the surface of the interlayer insulating film, and then forming an upper layer wiring thereon.

〔作用〕[Effect]

この発明においては、下層配線と上層配線の交差する部
分の層間絶縁膜の凸状部を選択的に除去し、その上に層
間絶縁膜を堆積形成させることから、眉間絶縁膜表面が
平坦化され、さらにその上に形成される多層配線層も平
坦化されて形成される。
In this invention, the convex portion of the interlayer insulating film at the intersection of the lower layer wiring and the upper layer wiring is selectively removed, and the interlayer insulating film is deposited thereon, so that the surface of the insulating film between the eyebrows is flattened. Furthermore, the multilayer wiring layer formed thereon is also planarized.

〔実施例〕〔Example〕

以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例による半導体装置の部分断
面図である。この図て、第3図と同一符号は同しものを
示し、4aは前記下層配線3で生じる段差部分、すなわ
ち下層配線3上に形成された層間絶縁膜の凸状部の層間
絶縁膜を除去(エツチング)し、段差を軽減させること
を目的とした第1の層間絶縁膜、4bは前記第1の層間
絶縁膜4aを形成後、その上および露出した下層配線3
上に形成した第2の層間絶縁膜であり、この上に上層配
線5が形成されている。
FIG. 1 is a partial sectional view of a semiconductor device according to an embodiment of the present invention. In this figure, the same reference numerals as in FIG. 3 indicate the same things, and 4a indicates the removal of the interlayer insulating film at the stepped portion that occurs in the lower layer wiring 3, that is, the convex portion of the interlayer insulating film formed on the lower layer wiring 3. After forming the first interlayer insulating film 4a, the first interlayer insulating film 4b is formed by etching the first interlayer insulating film 4b for the purpose of reducing the level difference.
This is a second interlayer insulating film formed thereon, and the upper layer wiring 5 is formed thereon.

次に、第2図(a)〜(f)によりその形成力ン去につ
いて説明する。
Next, the formation and removal will be explained with reference to FIGS. 2(a) to 2(f).

半導体基板、例えばシリコン基板1上に形成された絶縁
膜2上全面に下層配線膜3“を形成しく第2図(a))
、任意の形状に加工し、下層配線3を配置する(第2図
(b))。次いで、第1の層間絶縁膜4aを全面に形成
する。この第1の層間絶縁膜4aは、表面平坦化が主目
的であるため、堆積形成させる膜の厚さは、下層配線3
の厚さと同程度か、それ以上の厚さが必要である(第2
図(C))。
A lower wiring film 3'' is formed on the entire surface of an insulating film 2 formed on a semiconductor substrate, for example, a silicon substrate 1 (FIG. 2(a)).
, it is processed into an arbitrary shape, and the lower layer wiring 3 is arranged (FIG. 2(b)). Next, a first interlayer insulating film 4a is formed over the entire surface. Since the main purpose of this first interlayer insulating film 4a is to flatten the surface, the thickness of the film to be deposited is limited to the thickness of the lower wiring 3.
The thickness must be the same as or greater than the thickness of the second
Figure (C)).

次いで、エツチングにより、下層配線3と上層配線5か
交差する部分、すなわち下層配線3により第1の層間絶
縁膜4aの凸状部を選択的に除去する(第2図(d))
。次いで、第2の層間絶縁膜4bを堆積形成しく第2図
(e))、その上に上層配線5を形成することにより(
第2図(f))、下層配線3と上層配線5間の層間絶縁
膜が形成される。
Next, by etching, the portion where the lower layer wiring 3 and the upper layer wiring 5 intersect, that is, the convex portion of the first interlayer insulating film 4a by the lower layer wiring 3 is selectively removed (FIG. 2(d)).
. Next, a second interlayer insulating film 4b is deposited (FIG. 2(e)), and an upper layer wiring 5 is formed thereon (FIG. 2(e)).
In FIG. 2(f)), an interlayer insulating film between the lower layer wiring 3 and the upper layer wiring 5 is formed.

なお、上記実施例では、2つの配線間の場合について説
明したが、配線層が2つ以上の多層配線においても、各
々の配線層間の層間絶縁膜に適用してもよく、上記実施
例と同様の効果を奏する。
In addition, although the above embodiment describes the case between two wirings, it may also be applied to an interlayer insulating film between each wiring layer in a multilayer wiring having two or more wiring layers, and the same method as in the above embodiment may be applied. It has the effect of

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は半導体基板上に配置さ
れた下層配線上に層間絶縁膜を形成し、前記下層配線と
交差する部分の前記層間絶縁膜の凸状部を選択的に除去
した後、その上に眉間絶縁膜を堆積形成することにより
、層間絶縁膜表面を平坦化した後、さらにその上に上層
配線を形成する工程により、多層配線構造を形成するの
で、層間絶縁膜の表面を平坦化することができ、上層配
線の加工が容易になり、また、上層配線の断面短絡等が
少ない信頼性の高い半導体装置が得られる効果がある。
As explained above, the present invention forms an interlayer insulating film on a lower layer wiring arranged on a semiconductor substrate, selectively removes the convex portion of the interlayer insulating film at a portion intersecting with the lower layer wiring, and then After flattening the surface of the interlayer insulating film by depositing the glabellar insulating film thereon, a multilayer wiring structure is formed by forming the upper layer wiring on top of the planarized surface of the interlayer insulating film. This has the effect that it can be flattened, the upper layer wiring can be easily processed, and a highly reliable semiconductor device with less cross-sectional short circuits of the upper layer wiring can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による半導体装置の断面図
、第2図はこの発明の製造方法を説明するための工程断
面図、第3図は従来の半導体装置の断面図、第4図は従
来の製造方法を説明するための工程断面図である。 図において、1はシリコン基板、2は絶縁膜、3は下層
配線、4aは第1の層間絶縁膜、4bは第2の層間絶縁
膜、 5は上層配線である。 なお、 各図中の同 符号は同 または相当部分 を示す。
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process cross-sectional view for explaining the manufacturing method of the present invention, FIG. 3 is a cross-sectional view of a conventional semiconductor device, and FIG. FIG. 2 is a process cross-sectional view for explaining a conventional manufacturing method. In the figure, 1 is a silicon substrate, 2 is an insulating film, 3 is a lower layer wiring, 4a is a first interlayer insulation film, 4b is a second interlayer insulation film, and 5 is an upper layer wiring. Note that the same symbols in each figure indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に配置された下層配線上に層間絶縁膜を形
成し、前記下層配線と交差する部分の前記層間絶縁膜の
凸状部を選択的に除去した後、その上に層間絶縁膜を堆
積形成することにより、層間絶縁膜表面を平坦化した後
、さらにその上に上層配線を形成する工程により、多層
配線構造を形成することを特徴とする半導体装置の製造
方法。
An interlayer insulating film is formed on a lower layer wiring arranged on a semiconductor substrate, and after selectively removing a convex portion of the interlayer insulating film at a portion intersecting with the lower layer wiring, an interlayer insulating film is deposited thereon. 1. A method for manufacturing a semiconductor device, comprising: flattening the surface of an interlayer insulating film by forming a multilayer wiring structure, and then forming an upper wiring layer thereon to form a multilayer wiring structure.
JP11710489A 1989-05-10 1989-05-10 Manufacture of semiconductor device Pending JPH02296332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11710489A JPH02296332A (en) 1989-05-10 1989-05-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11710489A JPH02296332A (en) 1989-05-10 1989-05-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02296332A true JPH02296332A (en) 1990-12-06

Family

ID=14703502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11710489A Pending JPH02296332A (en) 1989-05-10 1989-05-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02296332A (en)

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