JPH02294849A - Program debugging system - Google Patents

Abstract

PURPOSE:To improve the efficiency of debug against an unexpected internal interruption by outputting automatically an internal interruption name, a message in which an internal interruption factor and its avoiding means are described, operand data of its instruction, and a related register. CONSTITUTION:In the case a generated internal interruption (n) is an unexpected internal interruption, an internal interruption discriminating means 13 delivers a control to a debug information monitor 4. Based on pointer information supplied from the internal interruption discriminating means 13, an internal interruption detailed message editing means 40 edits an internal interruption name INTN for showing an interruption classification of the internal interruption (n) in debug information 30 stored in an external storage device 3, and subsequently, an internal interruption (n) factor message FMn, and in the end, an internal interruption (n) hint message HMn. Next, an executing instruction operand editing means 41 is started, and moreover, an output register editing means 42 is started. In such a way, since an internal interruption or not cannot be discriminated directly, such a defect as the debug efficiency is bad can be eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a program debugging method using a software simulator, and in particular to a method for debugging a program when an unexpected internal interrupt occurs due to a program bug in a program to be evaluated. Regarding program debugging methods.

[Conventional technology]

Conventionally, in this type of program debugging method, when an unexpected internal interrupt occurs due to a program bug in the program to be evaluated, register contents provided by a software simulator are used to investigate the cause. Information was collected manually using the reference function and memory contents reference function.

[Problem to be solved by the invention]

In the conventional program debugging method described above, the necessary information is collected manually, and it is difficult to determine whether an unexpected internal interrupt has occurred or whether the internal interrupt is caused by checking which part of the functional specifications of the hardware and firmware. Since it is not possible to directly determine the cause of the problem and how to avoid it, it is necessary to investigate the cause of the problem and how to avoid it, which is a drawback of poor debugging efficiency.

[Means to solve the problem]

The program debugging method of the present invention provides a simulation system for debugging a program to be evaluated in which an unexpected internal interrupt occurs due to a program hack in a programm to be evaluated. A simulator body that simulates the functions of a processor, a main storage device that stores the program to be evaluated, an external storage device that stores debug information, a debug information monitor that edits and outputs debug information, and a debug information monitor that edits and outputs debug information. Consists of a display device that outputs debugging information for human display,
The simulator includes a starting means, an instruction fetching means, an instruction analysis/execution means, an internal interrupt determining means for determining whether an internal interrupt that has occurred is an expected one, and register details of the information processing device. The tehugu information monitor has a register area simulating the ``operan 1'' data, and an execution instruction operan ``save area'' for temporarily storing the operan 1 data in the simulator body when the instruction is executed. Internal interrupt detail message editing means for editing a message describing the cause/avoidance method of an internal interrupt, execution instruction operand editing means for editing operand data of an execution instruction, and output register editing means for editing registers related to internal interrupts. It is composed of:

〔Example〕

Next, the present invention will be described with reference to the drawings, taking as an example a case where the program to be evaluated is a test program for an apparatus.

FIG. 1 is a block diagram showing the structure of an embodiment to which the present invention is applied, which includes a simulator body 1, a main storage device 2 that stores an evaluation target program 20, and an external storage device 3 that stores debug information 30. , a debug information monitor 4 that edits and outputs debug information, and a display device 5 that displays and outputs unedited debug information. Furthermore, the simulator main body 1 is composed of a startup means 10, an instruction fetching means 11, an instruction analysis/execution means 12, an internal interrupt determination means 13, a register area 14, an execution instruction operand save area 15, and also includes technical information The monitor 4 includes an internal interrupt detail message editing means 40, an execution instruction operand editing means 41, an output register editing means 42, and a debug information output stage 43.

FIG. 2 shows Depaku information 30 stored in the external storage device 3.
format, and corresponds to one internal interrupt n that may occur when checking a certain part of the functional specifications of the processor hardware and firmware simulated by the simulator book (Wed 1). , the internal interrupt name INTN that indicates the internal interrupt insertion, and the internal interrupt n cause that describes which part of the hardware and firmware functional specifications of the device being simulated was checked for the internal interrupt n. Message FMn, internal interrupt n cause message FMLn indicating its length, internal interrupt n hint 1 to message HMn describing the means to avoid internal interrupt n, and internal interrupt n hint message length H indicating its length. M L. and an output register table R in which registers related to internal interrupt n are mixed in a pit pattern.
E.G. It consists of

Next, the operation of the present invention will be described with reference to FIG. 3 (a flowchart showing the processing procedure of this embodiment), taking as an example the case where the program to be evaluated is a device test program l\.

First, the simulator main body 1 is started up using the starting means 10 from outside (step 100).

The activation means 10 activates the instruction retrieval means 11, and the activated instruction retrieval stage 11 retrieves the next instruction to be executed from the evaluation target program 20 stored in the main storage device 2, and analyzes the instruction. /The command analysis/execution means 12 is started (step 101).

The instruction analysis/execution means 12 analyzes the instruction supplied from the instruction extraction means 11, and executes a simulation of the instruction based on the analysis result (step 102).
During the instruction analysis process and instruction execution process in this instruction analysis/execution means 12, whether or not there is an internal interrupt is determined.
The internal interrupt determining means 13 determines the interrupt (step 1031).
). If there is no internal interrupt, the process returns to activation of the instruction fetching means 11 and moves on to the next instruction fetching process (step 101).
).

If there is an internal interrupt in the first step of the internal interrupt determining process (step 103) of the internal interrupt determining means 13 (hereinafter, this internal interrupt will be referred to as internal interrupt n), the process proceeds to the second step of determining. , it is determined whether this internal interrupt n is an unexpected internal interrupt (step 10B2). It should be noted that the determination as to whether or not the internal interrupt is the expected internal interrupt is carried out as follows.

That is, when the program to be evaluated is a test program for an apparatus, due to the nature of the program, an internal interrupt may be intentionally generated and the occurrence of the internal interrupt may be tested. In this case, the test program indicates that the internal interrupt to be generated is the expected internal interrupt by setting the name of the internal interrupt that will occur in a predetermined area of the evaluation target program 2o and the information on the location where it occurs, The internal interrupt determining means 13 refers to a predetermined area within the evaluation target program 20 and determines whether or not the generated internal interrupt is an expected internal interrupt.

If the internal interrupt n that has occurred is the expected internal interrupt, the process returns to activation of the instruction fetching means 11 and proceeds to the next instruction fetching process (step 101).

If the generated internal interrupt n is an unexpected internal interrupt, the internal interrupt determining means 13 uses the pointer + W information indicating the beginning of the message for internal interrupt n in the debug information 30 stored in the external storage device 3. , and supplies it to the debug information monitor 4, and also starts the debug information monitor 4 (step 104) without passing control to the debug information monitor 4. The internal interrupt detailed message editing means 40 of the activated debug information monitor 4 edits the internal interrupt n in the debug information 30 stored in the external storage device 3 based on the pointer information supplied from the internal interrupt determining means 13. Find the beginning of the detailed message for internal interrupt n
Based on the internal interrupt name INTN indicating the interrupt type, then the internal interrupt n cause message FMn based on the internal interrupt n cause message length FMLn, and finally the internal interrupt n cause message FMn.
Edit the internal interrupt n hint message HMn based on the hint message length HMLn (step 105
) and activates the execution instruction operand tri% means 41.

The activated execution instruction operand editing means 41 saves an execution instruction operand save area 15 for temporarily importing the operant into the simulator when an instruction is executed in the simulator body 1, and edits the execution instruction that caused the internal interrupt n. The used operan) data is taken out and edited (step 106), and the output register editing stage 42 is activated.

The activated output register editing means 42 outputs debug information 3.
Output register table RE for internal interrupt n in 0
Referring to the bit pattern of Gn, extract a register that is hit or in an ON state from one register area in the simulator body 1 and edit it (step 107).
At the same time, the debug information output means 43 is activated.

The activated debug information output means 43 outputs the internal interrupt name, internal interrupt n cause message, internal interrupt n hint message edited by the internal interrupt detailed message editing means 40, and the execution command edited by the execution command operand editing means 41. The operand data of the instruction and the register data edited by the output register editing means 42 are displayed on the display device 5 (step 108).

〔Effect of the invention〕

As explained above, the present invention provides a simulation system that performs bugging of a program to be evaluated, and when an unexpected internal interrupt occurs due to a program bug in the program to be evaluated, the name of the internal interrupt,
To automatically output a message describing the cause of an internal interrupt, a message describing the avoidance method, operand data of the instruction that caused the internal interrupt, and registers related to the internal interrupt without human intervention. This has the effect of improving the efficiency of debugging unexpected internal interrupts.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment to which the present invention is applied, FIG. 2 is an explanatory diagram showing the format of debug information in an external storage device, and FIG. 3 is a block diagram showing the format of debug information in an external storage device. It is a flow chart showing a processing procedure. 1...Simulator main body, 2...Main storage device, 3.
...External storage device, 4...Tebug information monitor, 5...
・Display device.

Claims (1)

[Claims] A simulation system for debugging a program to be evaluated in which an unexpected internal interrupt occurs due to a program bug in the program to be evaluated, the simulation system comprising: A simulator body that simulates the evaluation target program, a main storage device that stores the evaluation target program, an external storage device that stores debug information, a debug information monitor that edits and outputs the debug information, and a debug information monitor that edits and outputs the debug information. The simulator main body is composed of a display device that outputs a display, and the simulator main body includes a starting means, an instruction fetching means, an instruction analysis/execution means, and an internal interrupt discriminator for determining whether or not the generated internal interrupt is an expected one. It has a register area that simulates the register group of the information processing device, and an execution instruction operand save area for temporarily importing the operand data into the simulator body when an instruction is executed, and debug information. The monitor includes an internal interrupt detail message editing means for editing a message describing the cause/avoidance method of an internal interrupt, an execution instruction operand editing means for editing operand data of an execution instruction, and an output for editing registers related to internal interrupts. A program debugging method comprising register editing means.