JPH02293958A - Interface apparatus - Google Patents

Abstract

PURPOSE: To communicate data at a high speed by causing the address space of a first bus to correspond to that of a second bus by an address conversion means and directly accessing a device on the second bus based on this correspondence by a bus master of the first bus. CONSTITUTION: Since the bus master of a VME bus can directly access the device on a future bus 12, the efficiency of data communication processing is improved, and consistency of data in a main memory 2 and a cache memory 7 on the future bus 12 is maintained, and noncoincidence between corresponding data in the system is prevented. A computer device on the future bus 12 writes address correspondence (mapping) data in an address conversion circuit 18, and the address and the state of a snoop signal of the future bus 12 which are generated by the address conversion circuit 18 can be selectively changed in accordance with a specific address of the VME bus 10. Thus, high-speed data communication is possible.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interface device that performs data communication between computer systems, and in particular, to a bus master connected to one computer bus (control right of the bus). This relates to an interface device that allows one device (a device that owns a bus) to directly access the address space of another bus.

[Prior Art] A plurality of computer processing devices may be interconnected so that they can communicate with each other so that data from one computer can be used by another computer. Also,
Multiple computer processing units can be connected to the same parallel computer
Some systems connect to a bus and arbitrate control of the bus between these devices, allowing them to access the same main memory. In such systems, one processor can send data to another processor by writing the data to main memory, which the other processor can read. For faster memory access, computer devices on the bus should
Copying data blocks from memory to a high speed cache memory and performing read and write operations only to this cache memory. However, if another computer device on the bus subsequently reads data from the same area of main memory, the data in this area has not been updated to correspond to the updated contents of the corresponding cache memory. , old data will be read. Also, if another computer device writes data to the same area of main memory, the cache
Since the contents of the memory are not updated, the data in the cache memory becomes old data.

Standard I EEE8 9 6 bus (Future bus: F
turebus) executes the following procedure in order to make the corresponding data in the cache memory and main memory consistent. First, when a first bus master attempts a read access to an address in main memory, it sends a "SNOOP" onto the future bus during the address cycle.
outputs a ``snooping'' signal.

If a second bus master on the Future Bus is using cache memory to access data corresponding to data at that address in main memory, the second bus master will perform a "retry ( RETRY signal to cause the first bus master before the completion of the address cycle to relinquish control of the future bus. At this point, the second bus master gains control of the Futurebus and writes the appropriate data from cache memory to main memory. After that, the first bus again
When a master attempts to access data in main memory, the second bus master ignores the snub signal and sends the address cycle and data to the first bus master.
Complete both cycles.

In some bus systems, a bus master may "lock" the bus, thereby preventing other devices from gaining control of the bus. (A "lock" is a state in which one bus master has exclusive control of the bus, preventing other devices from gaining control of the bus.) For example, when generating display data, A computer can first read data from memory, modify the data appropriately, and then return the modified data to memory. In order to execute such read, modify, and write operations at high speed without interrupting bus control,
The computer can lock the bus. The computer may also lock the bus in order to transfer large blocks of data without interruption.

[Problems to be Solved by the Invention] When various computer processing devices employ different parallel buses, these computer processing devices cannot be directly connected to the same bus. In this case, the computer processing devices function only as separate computer systems using separate buses and accessing separate local memories. Typically, each computer system has multiple boats connected to the bus.

These separate computer boats are interconnected so that when a first computer reads data from its local memory and writes it to its port, the data is transferred from that port to the second computer's boat. It is notified that there is data to be transferred. The port of this second computer notifies the second computer that the input data has been transferred. The second computer then reads the data from its port and stores it in its local memory. If necessary, the second computer then converts the input data with the second bus protocol to match the data in the cache memory. However, in order to transfer data from a storage location on a bus of a first computer to a storage location on a bus of a second computer, multiple bus
Because it requires cycles, the data transfer process takes time and limits the processing power of the computers in both systems.

Furthermore, such interconnections between ports and boats lock control of the bus, preventing data from being read or
Operations such as modification and writing and block transfer cannot be sped up.

Accordingly, one of the objects of the present invention is to enable a computer processing device connected to a first bus to directly access memory connected to a second bus;
An object of the present invention is to provide an interface device that allows a computer processing device on a second bus to always maintain the consistency of corresponding data between a main memory and a cache memory on a second bus.

Another object of the invention is that a computer processing device connected to a first bus can lock the other bus and have direct read or write access to the address space of the other bus. The objective is to provide a flexible interface device.

[Means for Solving the Problems J The interface device of the present invention has two computers.
A device responsible for data communication between system buses. In an embodiment of the invention, one computer system uses the well-known VME bus and the other computer system uses the well-known VME bus.
The system uses Future Bus.

The interface device according to the first aspect of the present invention includes an address conversion circuit that associates the address space of the ME bus with the address space of the feature bus. When a computer on the VME bus outputs a first address to the VME bus to perform a read or write access operation, this address conversion circuit generates a corresponding second address on the future bus and A snub signal is also generated in the FutureBus system to indicate whether the second address corresponds to a data storage location in a cache memory on the FutureBus. This snub signal allows it to be determined whether the data in the main memory accessed by the second address corresponds to the data in the cache memory. Thereafter, a control circuit within this interface device takes control of the future bus, outputs an address signal and a snoop signal on the future bus, and performs read or write access.
Start the cycle. When the snoop signal indicates that the data at the second address of the main memory on the Future Bus corresponds to data in the cache memory, the control circuit in the interface device causes the main memory and cache on the Future Bus to・Memory data alignment is executed. That is, the VMEbus bus
When the master attempts a read access, the data in the cache memory causes the second
When the data at the address is updated and the bus master of the VME bus makes a write access, the corresponding data in the cache memory is updated with the write data after the write to the second address in the main memory is completed.

The interface device according to the second aspect of the present invention includes an address conversion circuit that associates the address space of the ME bus with the address space of the future bus. When a computer (bus master) on the VME bus outputs a first address to the VME bus to perform a read or write access operation, the interface device acquires control of the Future Bus and Perform read or write access to the corresponding address. In this Future Bus system, the bus master can lock the bus to prevent other devices from gaining control of the bus. According to the present invention, an address conversion circuit that associates addresses sends a LOCKF signal (lock signals). This lock signal commands the interface device to lock the Future Bus, otherwise the bus master of the VME bus can maintain control of the VME bus.

The second inventive interface device further includes a second address conversion circuit that associates the Future Bus address space with the VME Bus address space. When a computer on the future bus attempts to read or write to an address on the future bus, the interface device acquires control of the VME bus through arbitration and reads to the corresponding address on the VME bus. or perform a write access. When a computer on the Future Bus locks the Future Bus, the interface device maintains (locks) control of the VME bus even after the read or write access to the ME bus is completed, thereby allowing the Future A computer on the bus is then able to perform another read or write access to the VME bus without having to wait for the interface device to arbitrate again to gain control of the VME bus.

[Operation] According to the interface device according to the first invention, ■M
Since the bus master of the E-bus can directly access devices on the Future Bus, it improves the efficiency of data communication processing and maintains the consistency of data in the main memory and cache memory on the Future Bus.
Discrepancies between corresponding data in the system can be prevented.

Further, the computer device on the Future Bus writes address mapping data to the address translation circuit, and the address translation circuit converts the generated Future Bus address and the state of the snoop signal according to a specific address on the VME bus. It is possible to change it selectively.

According to the interface device according to the second aspect of the present invention, the bus master of one bus can directly perform read and write access to the other bus,
In addition, the bus master of one bus can lock control of the other bus while performing a read or write access, allowing data to be transferred between the address spaces of both buses at high speeds as needed. It becomes possible to transfer.

[Embodiment] FIG. 2 shows an interface device (8) according to an embodiment of the present invention.
), in which an interface device (8) functions as an interface between a VME bus (10) and a Future bus (12).
The interface device (8) connects the VME bus (10)
A device such as a computer (2) connected to a main memory (3) connected to a future bus (l2)
or other addressable devices. The interface device (8) has a mapping function that associates the address space of the VME bus (10) with the address space of the future bus (12), so that the computer (2) can During a read or write access, the interface device (8) performs a read or write access to a corresponding address of a device on the Future Bus, such as the main memory (3). The interface device (8) also has the function of mapping the address space of the Future Bus to the address space of the VME Bus, so that a device such as a computer (4) connected to the Future Bus (12) can ), the interface device (8) performs a read or write access to the address of the VME bus (
A read or write access is performed to the corresponding address in the memory (5), for example on the memory (5). The computer (4) or (6) writes mapping data to the interface device (8) so that the computer (4) or (6)
Mapping processing between future buses and between the future bus and VME bus can be adjusted. However, once the mapping relationship is determined, the interface device (8) performs a data transparent operation between the devices on both buses. FIG. 1 is a block diagram showing in detail the configuration of the interface device (8) of FIG. 2. As shown in FIG. Bidirectional local data bus (14) and local address bus (16)
) is VMEbus (10) and Futurebus (l
2) Transfer data and converted addresses between. The devices on the Future Bus (12) are connected to the VME Bus (10).
)(7)7 When a read or write access is attempted to an address associated with the address space, the buffer (26) selectively sends the address of the feature bus to the local address bus (16).

Future bus/VME bus (F-V) conversion time! (2
8) then bit LA (
25:31) into bits A1 and A (25:31) of the corresponding vME bus address. here,
For example, A(25:31) means 7 bits from A25 to A31. The buffer (30) is connected to the local address bus (16)
4) and the bit AI generated by the F-V conversion circuit (28)
and A (25:31) to address bits A (1:31)
output on the VME bus (10) as The F-V conversion circuit (2nd day) connects these addresses to the VME bus (1st day).
0) control bits sent on}LWORD* and AM(0
:5) also occurs. "*" after the VME bus control signal name
” sign indicates that the signal is “true” when it is low level. As will be described in detail later, the bit signal LW
ORD*, in combination with other VME bus control i bits and address bits (DSO*, DS1* and AI),
Represents which 4-byte storage location is accessed during data transfer. Signal AM (address modifier) is used to convey information such as address size and bus cycle type.

The devices on the VME bus (10) are
), the buffer (20
) is connected to the VME bus (10) by converting the upper part A (12:31) into the corresponding upper address part of the future bus (l2). do. The buffer (22) outputs the address of this converted part onto the local address (16). The address generator (47)
The lower part address A (2:11) of the ME bus (10) is output on the local address bus (16) as the address of the corresponding lower part of the future bus address. (The address generator (47
) increments the feature bus address during block transfer. ) buffer (24) transfers the 30-bit translated address to the local address bus (16) during the address cycle of the future bus (12).
) to Future Bus (12) line AD (2:31)
Transfer to. Regardless of whether the device initiating a read or write operation is on the Future Bus (12) or the VME Bus (10), the data is on the VME Bus (10).
A bidirectional buffer (32) routes data from the VME bus (10) to the local data bus (14) as it flows from the VME bus (12) to the future bus (12). A buffer (34) then sends this data on the local data bus (l4) to the future bus (l2). Alternatively, as data flows from the Future Bus (12) to the VME Bus (10), a buffer (36) connects the appropriate line of the Future Bus (12) to the local data bus (
l4). Then the local data bus (
l4) is sent to the VME bus (10) via a buffer (32).

The interface device (8) includes a VME bus arbitration and control circuit (38). A preferred configuration for this circuit (38) is the MLzar VME I O
0 0 type VME bus arbitration circuit and Signetics 6 8 1 7 2 type VM
Contains an E-Bus protocol controller.

The VME bus arbitration and control circuit (38) is a traditional VM
Performs E-bus arbitration and control operations, and performs VME bus (10
) to allow other devices to access the interface device (8), and to allow the interface device (8) to access other devices. Similarly, the Future Bus arbitration and control circuit (40) performs conventional Future Bus arbitration and control operations and interface device (80).
) and other devices on the Future Bus (12). The local arbitration circuit (42) is preferably a 74F786 type arbiter manufactured by Signetics,
VME bus and future bus arbitration and control circuit (
38) and (40) (local data bus (14) and local address bus (14)).
6)). The local strobe generator (44) is connected to the VME bus arbitration and control circuit (3).
8) and the Future Bus arbitration and control circuit (40).

■The bus master connected to the ME bus (10) is a VM that is associated with the address of the future bus (l2)
When attempting read or write access to an address on the E bus, the bus master must access the VME bus (10
), the address is transferred to line A of the VME bus.
(1:31) on the address modifier line AM (0:
5) Output the data to the signal line D (0:31), respectively.

The VMEbus address and address modifier are stored in a buffer (20
) is supplied to the V-F conversion circuit (18).

FIG. 3 shows that when the bus master outputs the AS signal in step (50) to indicate that a valid address is present on the VME bus (10), the interface device (8)
FIG. 2 is a signal flow diagram showing how the controller responds. 1st
In Fig. 3 and Fig. 3, the AS* signal is detected. and V
The -F conversion circuit (18) determines whether or not the address of the VME bus is associated with the corresponding address of the future bus, and if the address is associated, the request signal -LRE is sent.
Q to the VME bus arbitration and control circuit (38) (step 52). In response, the VME bus arbitration and control circuit (38) inputs the request signal V-LREQ' to the local arbitration circuit (42) (step 54). If the local bus is available, the local arbitration circuit (42
) returns a grant signal V-LGNT to the VME bus arbitration and control circuit (38) (step 56). Thereafter, the arbitration and control circuit (38) generates the VGNT signal (step 58) and makes enable signals EN4 and EN3 true (step 59). In response to the enable signal EN4, the bar 777 (22) converts the upper bits of the converted address output of the V-F conversion circuit (18) into the local address.
A buffer (49) supplies the lower address bits from the address generator (47) onto the local address bus (16). In response to the enable signal EN3, the buffer (32) connects the data line of the ■ME bus to the local data bus (14). Local strobe generator (
44) is the local address strobe signal LOC
Generate AS (step 60). The local address decoder (46) checks the address on the local address bus (16) and, upon detecting the LOC AS address strobe signal, outputs the request signal L-F.
REQ to Future Bus arbitration and control circuit (40)
(step 61).

Future bus arbitration and control circuit (40) is LOC
When simultaneous occurrence of the two signals AS and L-FREQ is detected and the future bus (12) is available, the arbitration and control circuit (40) uses the future bus (12) to
12) and sends the L-FONT signal to the local strobe generator (44) (step 62).

Thereafter, the local strobe generator (44) makes enable signal EN6 true (step 64) and sends the address on the local address bus (16) to the future bus (12) via the buffer (24). The local strobe generator (44) then generates another strobe signal UAS (step 66). The Futurebus arbitration and control circuit (40) completes the Futurebus address cycle and returns an acknowledge signal FUAACK to the local strobe generator (44) (step 68). The local strobe generator then makes the enable signal EN6 false (step 69) and turns off the buffer (24).

The VME bus write control signal WRITE* indicates whether the bus master is attempting a read or write access and is activated by the local strobe generator (
44) and Future Bus arbitration and control circuit (40
) will be sent to both.

If this WRITE* signal is true, it indicates a write operation (step 70). The future bus arbitration and control circuit (40) makes the enable signal EN8 true (step 72), and connects the local data bus (14) to the future bus (12) via the buffer (34).
) to the data/address line. If the WRITE* signal is not true, it is a read operation and the future bus arbitration and control circuit (40) outputs the enable signal E.
With N7 true, the local
Connect the data bus (14) to the data/address line of the future bus (12). The local strobe generator (44) is used when the bus master of the ME bus receives data.
It waits until the strobe signal DSO* or DS1* becomes true (step 74). (Passing this step means that valid data is present on the VME bus for write operations, and that the bus master has the data ready for read operations.) Then, the local strobe The generator (44) makes the local data strobe signal LOC_DS true (step 76).
, the strobe signal UDS is also set to true (step 78).

Accordingly, the Future Bus arbitration and control circuit (
40) after completing a data read or write cycle on the Future Bus, the UDACK signal and the LDTA
Make the CK signals true (steps 80 and 82). V
The ME bus arbitration and control circuit (38)
VME bus data acknowledge signal DT according to the signal.
Make ACK* true (step 84). The local strobe generator (44) waits until the bus master of the VME bus asserts DSO* or DS1* false (step 86), then asserts LOC DS and UDS false (step 86).
Step 88). In response, the Future Bus arbitration and control circuit (40) determines that E is currently set to true.
Set the N7 and EN8 enable signals to false to connect the local data bus (14) to the future bus (12).
(Step 90). VME bus arbitration and control circuit (3B), V-F conversion circuit (18) and local address decoder (46)
determines whether the bus master of the vME bus still holds the AS* signal true (step 92). If this AS* signal is not true, the VME bus arbitration and control circuit (38) opens the VME bus (lO), sets enable signals EN3 and EN4 to false, and sets the VME bus arbitration and control circuit (38) to the VME bus (lO).
18) makes the V-LREQ signal false, and the local address decoder (46) makes the L-FREQ signal false (
Step 94). VME bus arbitration and control circuit (38
) detects that the V-F conversion circuit (18) has made the L-FREQ signal false, it makes the V-LREQ' signal false (step 96). The future bus arbitration and control circuit (40) releases the future bus (12) when the L-FREQ signal is set to false (step 98).
). A bus master on the VME bus (10) can read or write variables of up to 256 bytes of data at a series of addresses on the future bus (l2) when performing a "block transfer." It can be done. To perform a block transfer, the bus master sets the address modifier bits to block transfer mode and transfers the appropriate data.
The address strobe signal As* is continuously generated while the strobe signal DSO* or DS1* is repeatedly set to true and false. In the case of a block write, each of the series of data strobe signals indicates when the bus master has placed a new data word on the bus.

In the case of a block read, a series of data strobe signals indicates that the bus master is ready to accept a data word from the bus slave.
Here, a bus slave refers to a device with which a bus master communicates via a bus. The bus slave outputs V when the data strobe signal first goes true.
Read or write the first data at the address output on the ME bus (IO). Thereafter, in response to the generation of a series of data strobe signals, the bus slave stores or reads data at a series of addresses and outputs a data acknowledge signal on the VME bus (IO). For read or write block transfers, the necessary addresses are generated internally. The block transfer ends when the bus master sets the address strobe signal false.

The future bus (12) also has a block transfer mode, but the bus slave of the future bus (12)
Only a fixed small number of data words can be transferred in blocks to ensure data integrity in the cache memory. When a Futurebus bus slave reaches its limit, it sends an end-of-data signal EOD to the Futurebus bus master. Future bus bus
If the master wants to read or write more data, it initiates yet another data transfer operation.

In FIG. 1, the vME in the interface circuit (8)
The address generator (47) connected to the bus (10) is
It receives the address bit signal A (2:11) of the VME bus, and also receives the address strobe signal AS*, data strobe signals DSO* and DS1*, and the BT bit indicating that a block transfer is in progress. When address strobe AS* becomes true, address generator (47) stores and outputs address bits A (2:I1) to buffer (49). The buffer (49) is connected to the local address bus (16) in response to the EN4 signal.
) output these address signals on the

(The remaining bits of the local address bus (16) are provided by the V-F conversion circuit (18) via a buffer (22).) When the block transfer bit signal BT goes true, the address generator ( 47) is LA (
2:9) Increment the signal.

Therefore, during a block transfer operation, the bus master of the VME bus continues to generate the AS* signal after DTACK*,
The future bus arbitration and control circuit (40)
The A* signal is detected at step (92) in the figure. after that,
If the EOD signal is not true (step 99), another data read or write operation is performed in steps (70)-(92). In step (99), when the Future Bus arbitration and control circuit (40) detects the EOD signal, the operation of the interface circuit (8) returns to step (64) and the local strobe generator (44)
) makes the enable signal EN6 true again and outputs the updated address on the future bus (12). Thereafter, write or read operations are repeated in steps (66) to (92). AS* at step (90)
Block transfer operations similar to those described above continue until the Future Bus arbitration and control circuit (40) detects that the signal has become false. Then the interface circuit (
8) executes the operations of steps (94) to (98) as described above, and releases the future bus (12) when the block transfer is completed.

Figure 4 shows how the interface circuit (8) responds when a FutureBus bus master attempts to access a FutureBus address that is associated with an address on the VME bus (IO). It is a signal flow diagram. 1 and 4, the bus master connected to the future bus (l2) is the VME bus (1
When attempting to write or read an address on the Future Bus associated with a Future Bus (1 2), this bus master
is acquired through arbitration, and an address signal AD (2:31) is output on the future bus (12).

The window selection circuit (200) compares the upper bits of the address of the future bus with the data value in the base register (202), and determines whether the address of the future bus is associated with the VME bus (10). to decide. If this address correspondence is established, the window selection circuit (200) sends a request signal F-LREQ to the future bus arbitration and control circuit (40) (step 102). The Future Bus arbitration and control circuit (40) then sends F- to the local arbitration circuit (42).
The LREQ' signal is set to true to request access to the local bus (step l04). If the local bus is open, the local arbitration circuit (42)
The F-LGNT signal is returned to the Future Bus arbitration and control circuit (40) (step 106). Accordingly,
The Future Bus arbitration and control circuit (40) sets the enable signal EN5 true (step 108), turning on the buffer (26) and sending the Future Bus address to the local data bus (16). The arbitration and control circuit (40) also sets the strobe signal UAS to true (step 110). The local strobe generator (44) sets the LOC AS signal true in response to the UAS signal (step 112). Thus, the F-V conversion circuit (28) connects the local address bus (16)
The above Future Bus address is connected to the corresponding VME bus address A (1:31), the appropriate address modifier bit signal AM (0:5) and the appropriate bit signal LW.
Convert to ORD*. When the window selection circuit (200) detects the LOC As signal, it transfers the F-VREQ signal to the VME bus arbitration and control circuit (38).
Step 114). In response, the VME bus arbitration and control circuit (38) arbitrates for control of the VME bus (IO) (7) and then sets the enable signal EN2 to true (step 116). The bus arbitration and control circuit (38) sends the VGNT signal to the local strobe generator (44) (step 118), which sends the VME bus address, address modifier and F-■ conversion circuit via the buffer (30). (28) output LWORD*
is output onto the VME bus (10). Next, the future bus arbitration and control circuit (40) sets the VME bus address strobe signal AS* to true (step 120), sets the enable signal EN5 to false, and turns the buffer (26) off. Make it.

The future bus arbitration and control circuit (40) checks the control signal on the future bus (12), determines whether or not it is a write operation (step 126), and if it is a write operation, sets the enable signal EN7 to true. (Step 128 L buffer (36) transfers the address/data line of the future bus to the local data bus (14)
Connect to. If it is determined in step (126) that it is a read operation, the arbitration and control circuit (40) sets the enable signal EN8 to true (step 129), and the buffer (
34) is turned on. Thereafter, if it is determined that valid data is present on the feature bus (12), the arbitration and control circuit (40) outputs a UDS signal (step 130). The local strobe generator (44) sets a local data strobe signal LOC_DS to true in response to this UDS signal (step 132).
, accordingly, the VME bus arbitration and control circuit (38
) sets enable signal EN3 to true (step 1
34). As a result, data is outputted to the data lines of the Future Bus via the buffer (32), and the appropriate data strobe signals DSO* and/or DS1* for the length and byte position of the data word to be transferred are output. Set to true (step l36). VME bus (1
When the bus slave device No. 0) detects the occurrence of the data strobe signal DSO* or DS1*, it outputs the data acknowledge signal DTACK*.

The VME bus arbitration and control circuit (38)
Waiting for CK* signal (step 13B). after that,
An acknowledge signal LDTACK is sent to the future bus arbitration and control circuit (40) (step 140).
. The Futurebus arbitration and control circuit (40) completes the Futurebus data cycle and receives UDACK.
The signal is set to true (step 144). The arbitration and control circuit (38) of the VME bus includes DSO* and DS1*.
is set to false (step 146) and the enable signal EN
3 to true (step 14B) to signal completion of the VMEbus data cycle and disconnect the local data bus (14) from the VMEbus (1o). At the same time, the Futurebus arbitration and control circuit (40) sets the appropriate enable signal EN7 or EN8 to false, causing the local data bus (14) to
2) (step l50).

The Future Bus arbitration and control circuit (4o) checks the Future Bus address strobe signal to determine whether more data is to be sent. If it is determined that more data is to be sent, the arbitration and control circuit (40) returns to step (126) and performs another data read or write cycle. If the Future Bus address strobe signal AS is false in step (154), the arbitration and control circuit (40) sets the UAS signal to false (step 156).

Thereafter, the local strobe generator (44)
The AS signal is set to false (step 160). When this LOC AS signal becomes false, the VME bus arbitration and control circuit (3rd) sets the EN2 signal to false to turn off the buffer (30) (step 160). 162), and further the arbitration and control circuit (40) sets the F-LREQ' signal to false (step 164), indicating that the Future Bus arbitration and control circuit (40) no longer requires the local bus. The arbitration circuit (42) is notified. The local strobe generator (44) determines whether the Future Bus arbitration and control circuit (4o) has set the LOCKV signal to true (step 165L, if no, the arbitration and control circuit (40) sets the VME bus address strobe signal AS* to false (step 1).
66), indicating that the VME bus (10) is open.

However, in step 165, the Future Bus arbitration and control circuit (40) sets the LOCKV signal to true, causing the Future Bus bus master to
2), the arbitration and control circuit (4o) sets the AS* signal to true to indicate that the interface circuit (8) has released the VME bus (10). Indicates that there is no The operation of the interface circuit (8) returns to step (102) after which, for example, a bus master of the Futurebus performs an operation such as read/modify/write with respect to a data value stored at a location on the VME bus (10). Execute.

FIG. 5 is a block diagram showing a more detailed configuration of the V-F conversion circuit (18) of FIG. 1. In Figure 5, V
-F conversion circuit (1st) is V representing block transfer mode
It includes a decoder (210) that generates block transfer bits BT in response to a combination of address modifier bits of the ME bus.

This BT bit signal instructs the address generator (47) of FIG. 1 when to increment the address in response to a data strobe on the VME bus. The first level RAM (2 1 2) receives as address inputs address modifier bits AM (0:5) and address bits A (24:31) of the VME bus. The second level RAM (2 1 4) has as address input:
It receives the two outputs SO and S1 of RAM (2 1 2) and the address bits A (12:23) of the VME bus. The converted data is localized using the steps described below.
It is written to RAM (2 1 2) and (214) via the bus. Figure 6 shows the structure of the data words stored in each memory location of RAM (2 1 2), and Figure 7 shows the structure of the data words stored in each memory location of RAM (2 1 4). It shows the structure of a word. RAM
Bits SO and S1 in (214) select one of the four second level maps. Bits D (12:31) of RAM (214) provide local address bits LA (12:31). RAM (2 1 2
) bits O and 1 of the data word of rPAG
E FAULTJ and rVALIDIJ bits, and the rVALID2J bit of RAM (214) is
It is used to provide the basic functionality of virtual memory embedded in software. These three bit signals are VME
It is decoded by a decoder (216) in response to the address strobe signal A* of the bus.

If the VALIDI and VALID2 bits are true and the PAG
If the E FAULT bit is false, decode}'(2
16) outputs the V-LREQ signal.

If PAGE FAULT is true, decode (2
16) outputs a PF signal indicating that the bus master of the ME bus is attempting to access an invalid memory area. According to the command of this PF signal, the future bus arbitration and control circuit (40) controls the future bus (l
2) Interrupt the computer above and instruct the VMEbus page to be invalidated, allowing the Futurebus computer to operate properly. V-F conversion circuit (18
) is the LOCKF output bit of the RAM (214
) is stored as bit AO.

In FIG. 1, a V-F conversion circuit (18) generates a LOCKF signal in response to a predetermined combination of address modifier and address signal of the VME bus. This LOCKF signal causes the Future Bus arbitration and control circuit (40) to set a lock mode that prevents devices on other Future Buses from arbitrating the Future Bus and stops data transfer on the Future Bus. command to notify the following devices. After that, this lock mode is released when the bus master of the VME bus writes to the future bus (12) or when the VME bus address strobe AS* becomes false and the L-FREQ signal becomes false. Ru. This LOCKF signal is used for read/modify/write operations on the Future Bus (12), i.e., when a bus master reads data from a specific Future Bus address, modifies the data, or transfers the data to the same Future Bus address. This is usually generated to stop an operation such as writing to an address. In a typical operation, the LOCKF signal is
1 4) is stored in a part of the storage area, and the RAM
The output bits SO and Sl of (2 1 2) represent address modifier AM(0:
5) is output when a specific combination state is reached.

In Figure 2, the computer (6) on the Future Bus (2) transfers data blocks from the slower main memory (3) to the faster cache memory (7).
After that, data is read and written in the cache memory (7) instead of the main memory (3). If another device on the Future Bus (12), such as an interface circuit (8), subsequently reads data from the same area in the main memory (3), this read data will be transferred to the cache memory (
This is old data because it was not updated when the corresponding data in 7) was updated.

Further, when another device on the feature bus (12) writes data to the main memory (3), the corresponding data in the cache memory (7) becomes old data.

In order to ensure that the data in the cache memory and main memory are consistent, when the computer (4) attempts a read access to the main memory (3), the computer (4) uses the Future Bus (12) during the address cycle. A snoop signal SNOOP is output on the top. Computer (6
), other devices on the Future Bus (l2) such as
If the computer (6) is controlling the cache memory in order to make it consistent with the data stored at the address in the main memory, the computer (6) will generate a retry signal RETRY, which will cause the computer (4) to Control of the Future Bus (12) is relinquished. At this point, the computer (6) is connected to the Future Bus (l2).
and writes the appropriate data from the cache memory (7) to the main memory (3). after that,
As computer (4) repeats the address cycle, computer (6) ignores the snoop signal, allowing computer (4) to complete both the address cycle and the data cycle, so that computer (4) The data stored in the cache memory will be the same as the data in the cache memory. The computer (4) is the main memory (3)
Also when performing write access to the computer (6)
controls cache memory to perform similar operations.

However, in this case, in order to make the contents of the cache memory (7) consistent, once the computer (4) completes the write access, the computer (6)
Reads data from memory and stores it in cache memory (7
). In FIG. 1, the V-F conversion circuit (18) uses the Future Bus to indicate whether or not a snub operation should be performed on the Future Bus (12) in order to align the data in the cache memory of the Future Bus. A snoop signal SNOOP is output when generating a specific address on the bus. The Future Bus arbitration and control circuit (40) includes:
This snoop signal is output onto the feature bus (12), and an appropriate operation is executed in response to a try request from the cache mask on the feature bus. Referring to FIGS. 1, 5, and 7, V-F in FIG.
The snub signal output SNOOP of the conversion circuit (18) is R
It is controlled by the bit signal DI stored in AM (2 1 4). As described below, Future Bus (
l2) The above device is capable of writing data to each memory location of RAM (2 1 4), and the VM
In addition to adjusting the address conversion between the E bus and the future bus, it is also possible to appropriately set the state of the snoop signal SNOOP when snub operation is required.

FIG. 8 is a block diagram showing the configuration of the F-V conversion circuit (28) of FIG. 1 in more detail. F-V conversion circuit (28
) has local address bits LA (25 7 2B) as address inputs (3 0
0). As shown in Figure 9, RAM (30
0) is the address modifier bit AM(0:
5), address bits AC25:31) and bit signal rQUADLETJ are stored and output. These conversion data are written to RAM (3 0 0) via the local data bus in the procedure described below. The decoder (302) decodes the local address bits LA
A read enable signal is transferred to the RAM (3 0 0) according to a specific combination of (29:3 1). RAM (3 0 0) bit output signal QUAD
LET, select bit of the Future Bus arbitration and control circuit (40) in FIG. local address signal LOC As
and data strobe signal LOC_DS are input to the word length logic circuit (304). Bit signal Q
When set, UADLET is, for example, 32 bits (
may indicate the word length of a long word). The word length logic circuit (304) generates bit signals DSO', DSI'AS', LWORD* and AI' which are appropriately set according to the state of the input signal. Bit signal DSO'
and DSI' determine how the states of DSO* and DS1* should be set by the arbitration and control circuit (3) of the VME bus.
8). (The DSO*, DS1*, LWORD*, and AI signals together indicate which data byte location is accessed during the data transfer.)
The S' signal is the address strobe signal A of the VME bus.
It tells the arbitration and control circuit (38) when S* occurs. The control data that the Futurebus bus master transfers during the Futurebus data cycle indicates the word length and byte location to be accessed, and the Futurebus arbitration and control circuitry (40
) transfers the LANE data containing this data to the circuit (304) in FIG. The bus slave of the VME bus is connected to the VM when the address strobe signal AS* is generated.
Bit signal LWORD* output on E bus (10)
and A1 partially determine the length and byte position of the data transfer, so the arbitration and control circuit of the VME bus (
38) is up to the Futurebus data cycle,
The occurrence of AS* must be delayed. Specifically, if the output bit QUADLET of the F-V conversion circuit 28 is not true, the word length logic circuit (304) in FIG.
is the L output from the Future Bus arbitration and control circuit (40) during the Future Bus data cycle.
AI, DSO'DSI' and L based on ANE data
Determine the appropriate state of the bits in WORE until the local strobe generator (44) generates the LOC DS signal before the AS' signal is sent to the circuit (38).
The word length logic circuit (304) waits. In this case, the address strobe signal AS* on the VME bus is applied after step (118) of FIG.
Set to true after 32). By delaying setting this AS signal to true, the VME bus operation becomes slower because the ME bus slaves have a longer waiting time to capture and confirm address data.

However, all data stored in a particular portion of the VME bus address space is 32 bits (i.e., a long word).
If the format is known, the bit signal QUADLET in the storage location of the RAM (300) corresponding to that portion of the address space of the VME bus may be set to true. When this QUADLET bit is set to true, the word length logic circuit (304) uses AI, DSO', DS! to instruct a 32-bit data transfer. ' and LWORD
Set * to true and local address strobe LO
The AS' signal is generated immediately after the detection of C As. This A
The arbitration and control circuit (38) indicates that the S' signal causes the AS* signal to be generated immediately after step (120) in FIG.
).

Devices connected to the Future Bus (12) modify mapping data and other data stored in RAMs (2 1 2) and (214) in Figure 5 or RAM (3 0 0) in Figure 8. You can.

1 and 5, the data storage locations of RAM <2 1 2) and (214) are located in the base register (
202) is associated with a Future Bus address within a range determined by the data value LSP stored in LSP. (The base register (202) is associated with a fixed address on the Future Bus, and devices on the Future Bus can access the base register (202) via the conventional Future Bus interface circuit (204).
) may adjust the data vSP and LSP within. ) No. 10
As shown in the figure, when the window selection circuit (200) detects an address within the range indicated by the data LSP on the future bus (12), the window selection circuit (200) transmits the F-LREQ signal to the future bus arbitration and control circuit (40). (step 220). The future bus arbitration and control circuit (40)
- Send the LREQ' signal to the local arbitration circuit (42) (
Step 222). When this local bus is open, the local arbitration circuit (42)
Return the signal (step 226). Thereafter, the Future Bus arbitration and control circuit (40) receives the enable signal E.
Set N5 to true to turn on the buffer (26) (
Step 228), and setting the UAS strobe signal to true (Step 230). Local strobe generator (
44) then sets the LOC AS signal to true (
step 232), the various addressable devices on the interface device (8) (i-F conversion circuit (18) and F
−V conversion circuit (28)) to the local address
Capture the address on the bus. After that, the future bus arbitration and control circuit (40) sets the enable signal EN5 to false (step 234), and sets the read/write signal R/W supplied to the V-F conversion circuit (18) to true. setting and instructing a write operation (step 235). The feature bus arbitration and control circuit (40) sets the enable signal EN7 to true to connect the feature bus (12) to the local data bus (l) via the buffer (36).
4) (step 236) and connect to the Future Bus (
12) When there is valid data on, set the strobe signal UDS to true (step 238). The mouth-to-cal stroke generator (44) sets the LOC DS signal true in response to this UDS signal (step 240).
,．． :． This causes the data at the address output on the local address bus to be stored in one of the RAMs the last time the LOC AS signal was set true. The local strobe generator (44) sets the enable signal EN7 false (step 244) and then sets the UDACK signal true (step 246). Thereafter, the arbitration and control circuit (40) sets the UAS signal to false (step 247), and in response, the local strobe generator (44) sets the LOC AS signal to false (step 248). ．． Future bus arbitration and control circuit (4
o) sets the F-LREQ' signal false to release the local bus (step 250). Future bus (
12) can change the data stored in the RAM (300) in FIG. 8 through a similar procedure.

FIG. 11 is a block diagram showing a more detailed configuration of the address generator (47) of FIG. 1. Address generator (4
7), when the VMEbus address strobe signal is generated, the VMEbus address bit A (2:
9) to local bus address bit LA (2
: 9) includes a programmable counter (308) for storing and outputting. VME bus address bits A(10:11)L directly control local address bits LA(10:11). D.S.O.
The * and DS1* signals are fed to the inverting input of an OR gate (310). The output of the OR gate (310) and the block transfer bit BT output from the V-F conversion circuit (18) control the input of the AND gate (312). The output of the AND gate (312) is applied to the counter (30
B) and local address bit L
A(2:9) is incremented during each data cycle on the VME bus. Although preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described herein.
It will be apparent to those skilled in the art that various modifications and changes can be made as necessary without departing from the spirit of the invention.

[Effects of the Invention] According to the interface device according to the present invention, the address space of the first bus is associated with the address space of the second bus by the address translation means, and the bus master of the first bus is can directly access devices on the second bus, enabling high-speed data communication. Furthermore, since the data in the main memory and cache memory connected to the second bus are appropriately matched as necessary, confusion such as data mismatch in the entire system can be avoided. Furthermore, while the bus master of the first bus is executing read or write access to the second bus, control of the second bus can be locked as necessary. This enables high-speed data transfer without interrupting the access operation to the second bus by the bus master.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the interface device of the present invention, FIG. 2 is a block diagram showing an outline of the entire system including the interface device of the present invention, and FIG. 3 is a block diagram showing the configuration of an embodiment of the interface device of the present invention. Figure 4 is a signal flow diagram showing the processing of the interface device when a bus master accesses a VME bus address that corresponds to a Future Bus address. FIG. 5 is a block diagram showing the configuration of the V-F conversion circuit in FIG. 1 in more detail, and FIG. , a diagram showing the allocation state of data words stored in the RAM of FIG. 5, and FIG.
8 is a block diagram showing the configuration of the F-V conversion circuit of FIG. 1, and FIG. 9 is a diagram showing the allocation state of data words stored in the RAM of FIG. FIG. 10 is a signal flow diagram showing the processing when the Futurebus bus master writes mapping data to the interface device. FIG. FIG. 2 is a block diagram showing the configuration of an address generation circuit. (3) Two main memories (7): Cache memory (8): Interface device: First bus (VME bus): Second (Future bus): Address conversion means (F-V conversion circuit): Control means ( arbitration and control circuit)

Claims (1)

[Claims] 1. A second bus connected to a first bus controlled by a first bus master, a main memory and a cache memory;
An interface device that performs data communication with a bus, the first address space of the first bus being connected to a second address space of the second bus.
address translation means for converting a first address supplied from the first bus master to the first bus into a corresponding second address in the second address space; If the first bus master is connected between two buses and the data at the second address in the main memory corresponds to the data in the cache memory, the first bus master is connected to the second address in the main memory. , the data at the second address of the main memory is updated with the corresponding data in the cache memory, or the first bus master writes the data to the second address of the main memory. an interface device comprising: a control means for updating corresponding data in the cache memory with the write data after writing the write data. 2. An interface device for performing data communication between a first bus and a second bus, the interface device associating the address space of the first bus with the address space of the second bus, and transmitting data from the bus master of the first bus to the address conversion means for converting a first address supplied to the first bus into a corresponding second address in the address space of the second bus and generating a lock signal; connected between the first and second buses; the bus master of the first bus performs a write or read operation on the second bus by obtaining control of the second bus and providing the second address on the second bus. control means for locking the second bus in response to the lock signal to prevent another device connected to the second bus from acquiring control of the second bus during a period when the second bus is in control; An interface device characterized by the ability to