JPH0229050A - Tone detector - Google Patents

Abstract

PURPOSE:To vary the detected frequency by providing a storage device (RAM) able to readout and write so as to rewrite a data in the RAM. CONSTITUTION:Since a tone signal has a reference level (d) or over, a level discriminator 4 releases a reset signal (e) and a counter circuit 5 reaches the count enable state. A gate signal (a) goes to an H level for n-period of a tone signal by an n-period segmentation circuit 2. The time when the gate signal (a) reaches an H level is n/i(sec). When the frequency (i) of the tone signal to be detected, a data '1' is written in an address n(-)j/i0 of the RAM 10 and a data '0' is written in other address and a contact of an address switch 7 is connected to the position of the counter signal (f). Thus, it is possible to change the tone detection frequency simply by rewriting the data of the RAM 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tone detection device, and particularly to an improvement of a period counting type tone detection device.

[Conventional technology]

Conventionally, this type of tone detection device has used a read-only memory (ROM) as a memory portion for detecting frequencies.

[Problem to be solved by the invention]

The above-mentioned conventional tone detection device uses a read-only memory (ROM) for the memory portion, and therefore has the disadvantage that the detection frequency is fixed and cannot be easily varied.

SUMMARY OF THE INVENTION An object of the present invention is to provide a tone detector that detects tone frequencies without using a ROM.

[Means to solve the problem]

The tone detection device of the present invention includes a readable and writable memory (RAM), and an address switcher that switches and connects the address input of the RAM to one of the external address signals and the count value of a counting circuit that detects the period. It has a feature that the detection frequency can be made variable by rewriting the data in the RAM.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Reference numeral 1 denotes a tone input terminal, into which a tone signal from the outside is input. Reference numeral 2 denotes an n-cycle extraction circuit, which sets the gate signal a to H level during n-cycle periods of the tone signal (n is a certain integer value). 3 is an AND circuit which applies a gate to a reference clock signal having a certain frequency using a gate signal a, and outputs a counting clock signal C. Reference numeral 4 denotes a level determiner, which outputs a reset signal e when the input tone signal is lower than the reference level d. A counting circuit 5 counts the number of pulses of the counting clock signal C during a period when the reset signal e is not output, and outputs a count value signal f. 6 is an address input terminal to which an external address signal g is input. 7 is an address switch which selects either the count value signal f or the external address signal g and outputs it as an address signal. 8 is a data input terminal;
Data from the outside is input, and 9 is a tone detection output terminal which outputs a signal indicating that a tone has been detected.

Reference numeral 10 denotes a memory (RAM), which performs the operation of writing data from the data input terminal 8 to an address corresponding to the address signal and transmits the read data to the tone detection pressure terminal 9.
Perform the operation of outputting to.

Next, the operation of the apparatus will be explained step by step using FIG.

Reference level 6 at frequency 1 (Nz) from tone input terminal 1
Consider a case where a tone signal with a level higher than that is input. Since the tone signal has a reference level of 6 or higher, the level determiner 4 releases the reset signal e, and the counting circuit 5 becomes ready for counting. The n-cycle cutout circuit 2 sets the gate signal a to H level during the n-cycle period of the tone signal. The time for the gate signal a to reach the H level is n/i (seconds).

The AND circuit 3 applies a gate to the reference clock signal C and outputs the counting clock signal C. If the frequency of the reference clock signal C is J, the number of pulses of the counting clock signal C is n-j/i, so the value of the count signal f, which is the output of the counting circuit 5, is also n-j/i. At this time, in advance, connect the contacts of the address switch 7 to the external address signal g side, control the address input terminal 6 and the data input terminal 8, and control the frequency i of the tone signal to be detected.
When this happens, data "1" is written to addresses n-j/i, , of RAM 10, and "0" is written to other addresses, and then the contact of the address switch 7 is connected to the count value signal f side. It is assumed that

The count signal f is output as an address signal and becomes an address signal for the RAM 10. When the frequency of the input tone signal is equal to the frequency to be detected (i=io), 'RAM
The data at the address n·J/1 read from l0 becomes "1"' and is output to the tone detection output terminal 9, indicating that a tone has been detected. If the frequency of the input tone signal is not equal to the frequency you want to detect, the RAM
The data from l0 becomes 0'', indicating that no tone is detected. As described above, by rewriting the data in RAM l0, it is possible to easily change the tone detection frequency.

〔Effect of the invention〕

As described above, the present invention has the advantage that it is possible to easily and dynamically vary the tone detection frequency by rewriting the data in the memory device iAM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Tone input terminal, 2...n cycle extraction circuit, 3...AND circuit, 4...
・Level judger, 5... Counting circuit, 6...
・Address input terminal, 7...Address switch,
8...Data input terminal, 9...Tone detection output terminal, 10...Storage device (RAM), a
...Gate signal, b...Reference clock signal, C...Counting clock signal, d...
Reference level, e...Reset signal, f...
...Count value signal, g...External address signal, h
...Address signal. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] an n-cycle extraction circuit that extracts an arbitrary n-cycle time from a tone signal input having a constant cycle; a level determiner that determines whether the level of the tone signal is equal to or higher than a preset reference level; and the n-cycle an AND circuit that gates the reference clock signal by the output of the cutout circuit and outputs a number of pulses proportional to the n period of the tone signal;
When the level of the tone signal is determined to be equal to or higher than the reference level by the level determiner, a number of pulses proportional to the n cycles of the tone signal outputted from the AND circuit is counted, and a count proportional to the n cycles of the tone signal is calculated. a counting circuit that outputs a numerical value; an address switch that selects between the counted value output from the counting circuit and an external address signal and outputs it as an address signal;
Memory device (RAM) that can read and write data for the address input from the output of the address switch
A tone detection device having.