KR100319632B1 - Memory testing apparatus - Google Patents

Abstract

The present invention relates to a memory test apparatus, and in the related art, since the address is no longer increased when the final address of the user area is detected by the decoder, writes and reads to other areas than the user area are performed. There was a problem in that the data path and control path of the () cannot be tested. Therefore, the extended memory area test mode is detected by a simple internal circuit while using various input stages used in the conventional memory test apparatus, and all areas of the memory beyond the user area are controlled by adjusting the high voltage and the voltage applied to the control signal. By counting the addresses so that they can be tested, the extended memory area can be tested without changing the external interface specification of the memory test device.

Description

Memory Test Device {MEMORY TESTING APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory test apparatus. In particular, the data path between the memory and the CAPIU is tested by programming a specific area for the test in addition to the user area, and the end user writes to the memory after shipping the product. The present invention relates to a memory test apparatus capable of testing a write failure of a protected memory.

1 is a circuit diagram showing a configuration of a conventional memory test apparatus, and a high voltage input terminal Vpp for receiving a high voltage for a program as shown therein; An AND gate AND1 for ending the clock and the last address detection signal of the user area; An address counter (1) for counting the output of the AND gate (AND1) to output an address signal; A last address detector (2) for decoding the address output from the address counter (1) to the memory (3) to detect the last address of the user area; A memory 3 for storing actual data while being divided into several areas; A write / read control section (4) for writing / reading data in the memory (3) by a control signal; It is composed of a buffer unit 5 that is enabled by the signal output from the write / read control unit 4 to control the input and output to the memory 3, for the test of the memory (EPROM) configured as described above Operations and actions will be described with reference to the accompanying Figure 2 as follows.

First, in order to write / read data to the memory 3, a clock as shown in (c) while a predetermined high voltage (12.5V to 13.5V) is applied to the high voltage input terminal Vpp as shown in Fig. 2A. When is input, the address counter 1 outputs one address for one clock period as shown in (d). During this period, the write / read control unit 4 toggles the control signal as shown in (b). Each time, as shown in (f) and (g), the light and lead signals are alternately outputted, and the test is repeatedly performed until the final address of the user area is reached.

At this time, the last address detector 2 receives the input and decodes the address and outputs a 'low' level detection signal to the AND gate AND1 as shown in (e) if it is an address signal of the last address for the user area. The test is completed by preventing the address counter 1 from increasing.

However, in the conventional technique, since the address is no longer increased when the decoder detects the final address of the user area, the data path of writes and reads to other areas other than the user area. And there was a problem that can not test for the control pass.

Therefore, the present invention was created to solve the above-mentioned conventional problems, and when testing the area after the user area, the address can be continuously counted to widen the test range, thereby making the claim due to the memory defect ( It is an object of the present invention to provide a memory test apparatus that can reduce the incidence rate.

1 is a circuit diagram showing the configuration of a conventional memory test apparatus.

FIG. 2 is an exemplary diagram of waveforms output from each component of FIG. 1. FIG.

3 is a circuit diagram showing a configuration of a memory test apparatus according to the present invention.

4 is an exemplary diagram of waveforms output from each component of FIG. 3.

*** Description of the symbols for the main parts of the drawings ***

10: extended test mode detection unit 10a: counter unit

10b: decoder 10c: high voltage detector

10d: rising edge detection unit RS1: RS latch

OR1: OR gate AND1-AND3: AND gate

In order to achieve the above object, the present invention includes an AND gate AND1 for ending a clock and a final address detection signal of a user region; An address counter which counts the output of the AND gate AND1 and outputs an address signal; A final address detection unit for decoding the address output from the address counter to the memory and detecting a final address of the user area; In a memory device having a memory for storing actual data, which is divided into several areas, the high voltage Vpp and the clock CLK are reset by an AND gate AND2, and the high voltage is clocked. A counter unit for receiving a count; A decoder unit for detecting whether the counter unit counts more than a predetermined number; A high voltage detector for detecting whether a high voltage is applied to the control signal terminal; A rising edge detector detecting a rising edge of a high voltage applied to the control signal terminal; An RS latch and an inverter for inverting and outputting an edge detection signal output from the rising edge detector; An AND gate AND3 for ending the output of the inverter and the decoder; And an OR gate configured to perform an OR operation on the AND gate AND3 and an output of the last address detection unit, and output the OR gate AND3 to the AND gate AND1.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram showing a configuration of a memory test apparatus according to the present invention. In the memory device capable of testing a user area of a memory as shown in the drawing, an extension for detecting a mode for testing a region other than the user area A test mode detector 10; An OR gate (OR1) for ringing the output of the extended test mode detector (10) and the output of the last address detector (2); An AND gate AND1 for ending the output of the OR gate OR1 and a clock clk; And an address counter 1 for counting the output of the AND gate AND1 to output an address.

In this case, the extended test mode detector 10 may include: a counter unit 10a for resetting a high voltage and a clock by an AND gate AND2, and counting the high voltage as a clock terminal; A decoder unit (10b) for detecting whether a predetermined number or more is counted in the counter unit (10a); A high voltage detector 10c for detecting whether a high voltage is applied to the control signal terminal; A rising edge detector (10d) for detecting a rising edge of a high voltage applied to the control signal terminal; An RS latch RS1 and an inverter INV1 for inverting and outputting an edge detection signal output from the rising edge detector 10d; And an AND gate AND3 for ending the output of the inverter INV1 and the decoder 10b.

Hereinafter, with reference to Figure 4 attached to an embodiment according to the present invention configured as described above are as follows.

Next, the counter is cleared with the reset activated when the high voltage input terminal Vpp and the clock clk are 'low'. When the clock clk is kept high as shown in (f) and a high voltage is input as the clock source of the counter, the counter counts the clock and decodes a specific count value so that the signal at the high level as shown in (h). Outputs

In addition, the control signal input through the control signal input terminal (Control pin) is input to the write / read control unit 4 as in the prior art, the write / read signal (Write-en, Read-en) as shown in (i), (j) ) And at the same time, when a high voltage is detected through the high voltage detector 10c and the rising edge detector 10d as shown in (d), the high voltage level is continuously output as shown in (e) through the latch unit RS1. The 'high' level combined through the AND gate AND3 is input to the AND gate AND1 again through the OR gate OR1, thereby continuously applying a clock to the address counter to increase the address as shown in (g).

As described above, the memory test apparatus of the present invention detects the extended memory region test mode by a simple internal circuit while using various input stages used in the conventional memory test apparatus, and controls the high voltage and the voltage applied to the control signal. By counting the addresses so that all areas of the memory beyond the user area can be tested, the extended memory area can be tested without changing the external interface specification of the memory test apparatus.

Claims (1)

An AND gate AND1 for ending the clock and the last address detection signal of the user area; An address counter which counts the output of the AND gate AND1 and outputs an address signal; A final address detection unit for decoding the address output from the address counter to the memory and detecting a final address of the user area; In a memory device having a memory for storing actual data, which is divided into several areas, the high voltage Vpp and the clock CLK are reset by an AND gate AND2, and the high voltage is clocked. A counter unit for receiving a count; A decoder unit for detecting whether the counter unit counts more than a predetermined number; A high voltage detector for detecting whether a high voltage is applied to the control signal terminal; A rising edge detector detecting a rising edge of a high voltage applied to the control signal terminal; An RS latch and an inverter for inverting and outputting an edge detection signal output from the rising edge detector; An AND gate AND3 for ending the output of the inverter and the decoder; And an OR gate configured to perform an OR operation on the AND gate (AND3) and the output of the last address detector to output the AND gate to the AND gate (AND1).