JPH02288975A - Vector arithmetic unit - Google Patents

Abstract

PURPOSE:To decrease the number of operations and to shorten a whole operation time by executing no unnecessary operations when a mask bit shows '1.' CONSTITUTION:When the mask bit read from a memory 7 by an address, for which '1' is added to the output of an address register 5, is '1,' '1' and '1' are added to the output of the address register 5 by an adder 8 and stored to the address register 5. Samely, the data of vector registers 1 and 2 are read by the address of the address register 5 and calculated by an arithmetic part 3. At such a time, the output of the address register 5 is increased by '2.' Namely, at such a time, when the address is stored to a vector register 4, data to be abandoned when the mask bit of the memory 7 is referred are stored. Accordingly, the arithmetic is not executed but operation is skipped. Thus, when the mask bit is '1,' the number of the unnecessary operations is decreased and a whole processing time is shortened.

Description

TECHNICAL FIELD The present invention relates to a vector arithmetic device, and more particularly to a vector arithmetic device in which arithmetic results are stored in storage means in accordance with instructions from storage instructing means.

PRIOR ART In general, vector arithmetic units are used in arithmetic machines that have basic instructions that process multiple operations with one instruction, and the length of one step is short, so there is little content that can be processed within one step. Many of them increase the number of steps or simplify processing.

Conventionally, this type of vector calculation device has a configuration as shown in FIG. A vector register 1.2 that stores calculation data, a calculation unit 3, and a vector register 1 that stores calculation results.
an address register 5 that stores the read address of the flat register 12 and the write address of the vector register 4, a counter 6 that creates an address, and a mask pick that indicates whether or not to write to the flat register 4. The memory 7 stores 1 to 1.

The data stored in vector registers 1 and 2 is read out according to the address indicated by address register 5, and is computed by arithmetic unit 3, and the result is sent to the address indicated by address register 5 of vector register 4. Stored. In this case, if the value read at the address indicated in the address register 5 of the memory 7 is 1'',
Since it is masked, storage into the vector register 4 is stopped and the operation result is discarded.

Note that a vector register is a register configured such that all data in the register can be operated on by one vector instruction.

A series of conventional solid-state arithmetic units are masked with a mask bit of "1", and even if the result of an operation is discarded, all operations are performed, resulting in a longer overall operation time. , there is a drawback.

Purpose of the Invention It is an object of the present invention to solve the following drawbacks: When a masked address is included, the masked address must be operated at least once, which is completely unnecessary. An object of the present invention is to provide a vector calculation device capable of reducing the calculation time and the overall calculation time.

Structure of the Invention The vector I-L calculation device according to the present invention includes a vector storage f stage for storing a plurality of data, a calculation means for performing calculations using data read from the storage means, and a calculation means for performing calculations using data read from the storage means. A solid 1 to 3 calculation device comprising a calculation result storage means for storing a result, and an instruction means for instructing whether or not to write the calculation result in the calculation result storage means, At the time of reading, the content of the instruction means corresponding to this readout address is read out, and at the same time, the content corresponding to the next address is also read out. There is obtained a vector arithmetic device characterized in that it includes means for generating an address.

EXAMPLES Hereinafter, the details of the present invention will be explained by way of examples with reference to the drawings.

FIG. 1 is a diagram 11772 of one embodiment of the present invention.

A vector register 2 stores a plurality of pieces of operation data.The arithmetic unit 3 performs an operation using the data in the registers 1 to 2, and stores the result of the operation in a vector register 4. The memory 7 serving as an instruction means is a register file in which different data can be read out at the same time by two 7' addresses, and mask picks 1-, which indicate whether or not to write operation results in the registers 1-4, are stored. There is an adder 8 and an address register 5 as means for creating an address. This is an adder that adds "1" to the read value.Address register 5 is a register that stores the read address of register register 2 and the insertion address of register register 1.

Next, the operation of this embodiment having the above configuration will be explained. The data stored in the vector register 2 is sequentially outputted to the address indicated by the address register 5, and an operation is performed in operation 83. Here, if the mask bit read out at the address indicated by the address register 5 among the mask bits stored in the memory 7 is 0'',
Write the result of the arithmetic unit 3 to the vector register 4 at the address indicated by the address register 5, and at the same time, write the mask bits 1 to 1 read from the memory 7 at the address obtained by adding 1''' to the output of the address register 5 to be '0''. For example, adder 8
As a result, the output of address register 5 is 1″ and “o”.
are added and stored in address register 5.

In the next step, the data in the vector registers 1.2 is similarly read out using the address in the address register 5, and the arithmetic unit 3 calculates it. Here, if the mask bit 1~ read out at the address indicated by the address register 5 among the mask bits 1~ stored in the memory 7 is "0'", then
The results of the arithmetic unit 3 are written to the address registers 5 and 4, and at the same time, the memory 7
If the mask bit read at the address obtained by adding " ] " to the output of the address register 5 is '1', the adder 8 adds 1' and '1' to the output of the address register 5.
'° is added and stored in address register 5.

In the next step, the data in the vector registers 1.2 is similarly read out using the address in the address register 5, and the arithmetic unit 3 calculates it. At this time, the output of the address register 5 has increased by "2" from the previous step. In other words, when storing the address in the vector register 4, the address at this time is
Since the data that would be discarded when the mask bit of is referenced is stored, it was skipped without performing any calculations. Therefore, by doing this, the mask bit becomes "1".
In this case, the number of unnecessary operations can be reduced and the overall processing time can be shortened.

Effects of the Invention As described above, according to the present invention, the mask bit or "'1"
”, unnecessary calculations are not performed, so the number of calculations is reduced by that amount, which has the effect of shortening the overall calculation time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional vector calculation device. Explanation of symbols of main parts 1.2.4...Vector register 3...
- Arithmetic unit 5...Address register 7...Mask pin 1 to memory 8...Adder

Claims (1)

[Claims] (1) vector storage means for storing a plurality of data; calculation means for performing calculations using data read from the storage means; calculation result storage means for storing the calculation results;
A vector arithmetic device comprising: instruction means for instructing whether or not to write the arithmetic result in the arithmetic result storage means,
means for reading the contents of the instruction means corresponding to the read address when reading the vector storage means, and at the same time reading the contents corresponding to the next address; A vector arithmetic device comprising means for generating the read address accordingly.