JPH02287657A - Channel device - Google Patents

Abstract

PURPOSE:To execute the read-out control of a CCW (channel command word) in a channel device at a high speed and to improve the use efficiency of the channel device by providing a means for executing the arbitration of a first and a second requests from a microprocessor. CONSTITUTION:A microprocessor 21 gives a first request (CCW read-out request) for reading out the corresponding CCW to a DMA (direct memory access) control part 25 in accordance with an input/output instruction from a CPU 11. Subsequently, in the control part 25, the arbitration to a second request (transmitting and receiving data read-out/write request) is executed. In this case, the priority of a first request is dealt with equally to a second request or above, and even in a period in which a transmitting and receiving data read-out/write cycle by the DMA is executed repeatedly, a first request is selected quickly and given as a third request to a system bus control part 24. In such a way, a system bus 15 is obtained and the corresponding processing is executed, therefore, the read-out control of the CCW is executed at a high speed, and also, the use efficiency of a channel device 13 can be improved.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is directed to a channel command word (hereinafter referred to as , CCW), reads and decodes the channel device, activates the corresponding input/output control device connected to the device, and transfers data.

(Prior Art) In this type of channel device, when an input/output command is generally issued from a CPU (Central Processing Unit) to the device, the channel assigned to the device and the device When an I/O command is issued that specifies a subchannel assigned to an I/O control device connected to the I/O controller, the following operations occur. First, the microprocessor that controls the entire channel device retrieves the CCW start address (the start address of the CCW storage destination on the main memory) written in the input/output instruction, and specifies this address.
A CCW succession request is output to the system bus control unit that controls system bus acquisition within the channel device. The system bus control unit receives CCW read requests from the microprocessor and read/write requests for transmitted/received data to and from the main memory from the DMA control unit that controls DMA (direct memory access) transfers to and from the main memory. Perform priority control between requests such as

If the system bus is open, the issuer of the request prioritized in the system bus control unit acquires the system bus and starts data transfer between the main storage device and the channel device.

Now, in the system bus control section of the channel device,
Generally, requests from the DMA control unit are treated as having higher priority than requests from the microprocessor. Therefore, while an input/output controller (to which a subchannel is assigned) is transferring data with the main storage device using DMA control, an input/output controller (to which a subchannel is assigned) is connected to the same channel device. If the CPU issues an input/output command that targets a subchannel that has A CCW read l-request cannot be accepted if there is a request from the DMA control unit to read/write transmitted/received data to the main memory. In other words, even if the microprocessor issues a CCW read request to the system bus control unit, the CCW
Acquisition of the system bus necessary for reading W is made to wait until DMA control by the DMA control section is completed or interrupted.

(Problems to be Solved by the Invention) As described above, conventionally, when an input/output control device connected to a channel device is transferring data to and from a main storage device under DMA control, an input/output control device connected to the same channel device When an I/O command for an I/O control unit is issued from the CPU to a channel device, a wait state occurs because the microprocessor in the channel device cannot easily acquire the system bus even if it issues a CCW read request. The problem is that it lasts for a long time and the startup of the human output control device is significantly delayed, making it unsuitable for high-speed processing. In addition, since the microprocessor of the channel device remains in a waiting state for reading the CCW for a long time, even if the CPU attempts to issue the next input/output command, the reception cannot proceed to processing, reducing the usage efficiency of the channel device. There was also the problem.

Therefore, the problem to be solved by the present invention is to make it possible to speed up the read control of CCW (channel command word) in a channel device and improve the usage efficiency of the channel device.

[Configuration of the Invention (Means for Solving Three Problems) This invention provides a microprocessor in a channel device,
A function to issue the first request to read the corresponding ccwc channel command word from the main memory in response to an input/output command from the CPU, and read/write the transmission/reception data specified by the CCW read from the main memory. A DMA control unit that performs DMA transfer with the main storage device is provided with a function of issuing a second request for performing the above-mentioned microprocessor.
Issue a third request to the system bus control unit to acquire the system bus, assuming that the priority of the request is equal to or higher than the priority of the second request, and the request indicated by the corresponding first or second request. It is characterized by having a function of executing processing using DMA.

(Operation) According to the above configuration, the first request (CCW read request) from the microprocessor is given to the DMA control unit instead of the system bus control unit, and in this DMA control unit, the first request (CCW read request) from the microprocessor is sent to the DMA control unit. 2nd request (transmission/reception data read/write request) given to the unit in the same way as before
Mediation will be held. In the DMA control unit, the priority of the first request is treated as being equal to or higher than that of the second request. Therefore, the first request is not processed during the period when the DMA transmit/receive data read/write cycle is repeated. Even if the third
It is given to the system bus controller as a request. This third
When the system bus control unit acquires the system bus in response to a request, the DMA control unit performs CC control using the DMA.
W read processing is performed. On the other hand, the microprocessor that issued the first request to the DMA control unit and passed control of the CCW successive processing to the same control unit is released from the requested process, so it can perform other processes, such as the next input/output from the CPU. Upon reception of the command, it is possible to proceed to processing.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a computer system having a channel device of the present invention. In the figure, 11 is a CPU (Central Processing Unit) that forms the core of the system, and 12 is a main storage device used to store various programs and data.

13 is a channel device, and 14 is a human output control device connected to the channel device 13. Channels are assigned to the channel device 13, and subchannels are assigned to the input/output control device 14, respectively. Channel device 13 is CPU II
In response to an input/output command issued from the main storage device 12, CCW (channel command word), which is input/output operation information, is read out and decoded, and the corresponding input/output control device 1
It has the function of starting 4 and transferring data. In addition, the input/output control device 14 performs input/output operations with input/output devices (not shown) and the channel device 1 based on instructions from the channel device 3.
It has the function of issuing input/output interrupts to 3. A plurality of input/output control devices 14 are connected to the channel device 13 .

CPU IL main storage device 12 and channel device 13
are interconnected by a system bus 15 consisting of control, address, and data buses.

It is assumed that similar channel devices other than the channel device 13 are connected to the system bus 15.

The channel device 13 includes a microprocessor 21. which controls the entire device. A memory (hereinafter referred to as local memory) 22 used to store control microprograms and transmitted/received data necessary for the operation of the microprocessor 21
, and a microprocessor 21 bus (hereinafter referred to as local bus) 23 consisting of control, address, and data buses. Also, the channel device 13
has a system bus control unit 24 and a DMA control unit 25 that perform control related to acquisition of the system bus 15, giving top priority to requests for reading/writing transmitted and received data (DMA transfer requests). The DMA control unit 25 has a boat 25a that receives a CCW read request from the microprocessor 21 and a boat 25b that receives a read/write request for transmitted/received data from the microprocessor 21. Arbitration is performed on the D, and the determined request is output to the system bus control unit 24 to perform bus acquisition processing.
CCW reading or data transfer is performed under MA control.

In addition, the channel device 13 uses the subchannel specification part (subchannel number) in the input/output command issued from the CPU II and the CCW start address (CCW on the main storage device 12).
A stack register 2B (first-in, first-out system) for stacking (the first address of the storage destination of W), a CCW address register 27 for specifying the address of the CCW to be read from the main memory 12, and a CCW address register 27 for specifying the address of the CCW to be read from the main memory 12. It has a CCW data register 28 for holding the CCW. The channel device 13 further includes a data address register 29 with a built-in counter that specifies the read/write destination address of transmitted/received data to the main memory 12, and a write data register 29 for holding the data (received data) to be written to the main memory 12. It has a register 30 and a read data register 81 for holding data read from the main memory 12 (transmission data).

Next, the operation of the configuration shown in FIG. 1 will be explained.

First, an input/output command is issued that specifies the channel (channel number) assigned to the channel device 13 and the subchannel (subchannel number) assigned to the human output control device 14 connected to the channel device 13. , CPUII
It is assumed that the information is issued on the system bus 15 from In this case, the subchannel number and CCW start address in the input/output instruction are stacked in the stack register 26 in the channel device 13 specified by the channel number in the instruction, and an interrupt is generated in the microprocessor 21. As a result, the microprocessor 21 processes the reception of the above input/output command, and if the currently stacked (subchannel number and) CCW start address becomes the start information of the stack register 26, that is, the stack register at the time of the above interrupt. If the CCW address stacked in 26 is the address for the next CCW readout to be executed, first take out the CCW start address from the stack register 26 and set the same address in the CCW address register 27 via the local bus 23. . Next, microprocessor 2
1 outputs a CCW read request to the boat 25a of the DMA control unit 25, and the CCW read request 1.1 in the DMA control unit 25 is executed. Start request processing. In contrast, stack register 2
If another CCW address is already stacked at 6, the microprocessor 21 refrains from the above processing.

When a CCW read request is output from the microprocessor 21 to the port 25a, the DMA control unit 25 arbitrates with a request for reading/i1 input of transmitted and received data given to another boat 25b. Here, boat 2
Requests from 5a side are set with higher priority, and DM
The A control unit 25 selects the CCW read request applied to the port 25a. In this case, the DMA control unit 2
5 issues a system bus acquisition request to the system bus control unit 24 to issue CCW=. On the other hand, after the microprocessor 21 issues a CCW continuation request to the DMA control unit 25, it is released from processing related to the requested CCW continuation, regardless of whether the request is executed or awaited. Therefore, the microprocessor 21
Even if the CW reading is made to wait, other processing can be performed, and if the CPU issues the next input/output command, the reception of the command can proceed to the processing.

Now, the system bus control section 24 monitors the usage status of the system bus 15, and as mentioned above, the DMA control section 25
When a request (CCW read request) is issued, the system bus 15 is acquired as soon as the system bus 15 is released. Here, both the CCW read request and the transmit/receive data read/write request (DMA transfer request) are
Since the request is output from the A control unit 25 to the system bus control unit 24, both requests are not output to the system bus control unit 24 in parallel. Therefore, the system bus control section 24 always accepts the CCW continuous output request from the DMA control section 25. When the system bus control unit 24 receives a request from the DMA control unit 25 and acquires the system bus 15, it notifies the DMA control unit 25 of this fact, and in the case of a CCW read request as in this example. sends the request and the address set in the CCW address register 27 to the main storage device 12 via the system bus 15. As a result of this CCW read request and address sending, the corresponding CCW is read from main storage device 12. The CCW read from the main storage device 12 is transferred to the channel device 13 via the system bus 15, and
The data is held in the CCW data register 28 within the CCW data register 28.

When the CCW is transferred from the main storage device 12 in response to the CCW read request, the microprocessor 21 reads the CCW.
W is fetched from the CCW data register 28 via the local bus 23 and decoded. and microprocessor 2
1 causes the input/output control device 14 to which the subchannel number in the first information stacked in the stack register 26 is assigned to start the operation indicated by the CCW in accordance with the CCW decoding result, and Remove information from stack register 2B. At this time, if the decoded CCW specifies a read/write operation of transmission/reception data between the main storage device 12 and the input/output control device 14 and a data transfer using DMA, the microprocessor 21 transfers data to the main storage device 12. When writing received data to the DMA controller 25, the address is set in the data address register 29, the received data from the input/output controller 14 stored in the local memory 22 is set in the write data register 30, and the DMA controller 25 A write request for the received data is output to the boat 25b. In addition, the microprocessor 21
When reading transmission data from the main storage device 12, only the address setting operation to the data address register 29 is performed, and a request for reading transmission data is output to the port 25b of the DMA control unit 25.

When the microprocessor 21 completes the above processing, it checks whether the stack register 2B is empty or not. If it is not empty, it extracts the CCW start address from the top information stacked in the register 2B and stores the same address locally. It is set in the CCW address register 27 via the bus 23. Next, the microprocessor 22 outputs a CCW read request to the boat 25a of the DMA control section 25, and causes the DMA control section 25 to start CCW read request processing.

When the microprocessor 21 gives the boat 25b a request to read/write data transmitted/received to/from the main storage device 12, the DMA control section 25 arbitrates with a CCW read request given to another boat 25a. The DMA control unit 25 then reads/receives the transmitted/received data.
When a write request (a request to read transmitted data or a request to write received data) is selected, a system bus acquisition request is issued to the system bus control unit 24. In addition, D
In the MA control unit 25, as described above, the boat 25b
If a read/write request for transmitted/received data is given, the read/write request is processed as if the request had been given until a series of data transfers (DMA data transfers) corresponding to the request are completed. I do.

When the system bus control section 24 receives a system bus acquisition request from the DMA control section 25, it acquires the system bus 15 as soon as the system bus 15 is released, and returns a response to that effect to the DMA control section 25. When writing received data, the system bus control unit 24 sends the address held in the data address register 29 and the received data held in the write data register 30 to the main storage device 12 via the system bus 15. do. As a result, the data from the write data register 30 is written to the address of the main storage device 12 specified by the data address register 29, and the contents of the data address register 29 are counted up. On the other hand, when reading transmission data, the system bus control section 24 sends only the address held in the data address register 29 to the main storage device 12 via the system bus 15. As a result, the data at the address specified by the data address register 29 is read from the main storage device 12.

The data read from the main memory 12 is stored on the system bus 1.
5 to the channel device 13 and held in the read data register 31 within the device 13. The data held in the read data register 31 (received data read from the main storage device 12) is temporarily stored in the local memory 22.

Now, the period (D
During MA transfer), the microprocessor 21 sends a C corresponding to the next input/output command to the port 25a of the DMA control unit 25.
When a CW read request is issued, the DMA control unit 25 arbitrates with the read/write request processing of transmitted/received data for the DMA transfer being executed. in this case,
The DMA control unit 25 selects a CCW read request with a high priority and outputs the same request to the system bus control unit 24.

The subsequent operations are as described above.

Note that in the above embodiment, in the DMA control section 25, the C
Although we have explained that the CW read request is always set to a higher priority than the transmitted/received data read/write request, the priority is switched between high and low for each request output, and as a result, the priority of both requests is may be treated as the same level.

[Effects of the Invention] As described in detail above, according to the present invention, arbitration between the CCW read request process and the transmitted/received data read/write request process is performed in the DMA control unit with the priority of the former being equal to or higher than that of the latter. The request selected in this arbitration is sent from the DMA control unit to the system bus control unit, and when the system bus is acquired, the corresponding processing is performed by the DMA. Therefore, when the microprocessor issues a CCW read request, the CCW read Processing becomes faster. In addition, the microprocessor issues a CCW read request to the DMA control unit and entrusts the request processing to the DMA control unit, so that other processing, such as reception of the next input/output command, can proceed to the processing, and the channel device Improved usage efficiency. This effect becomes more pronounced in systems where there is a high possibility that input/output commands will be issued continuously, for example, in systems where there are a large number of input/output control devices connected to a channel device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a channel device according to an embodiment of the present invention. 11... CPU, 12... Main storage device, 13...
Channel device, 14...Person output control device, 15...
System bus, 21...Microprocessor, 22...
・Local memory, 23...Local bus, 24...
- System bus control unit, 25...DMA control unit, 26
...Stack register, 27CCW address register, 28...CCW data register. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A channel command word, which is input/output operation information, is read from the main storage device via the system bus in response to an input/output command given from the CPU, and is decoded, and the command is sent to the own device according to the decoding result. In a channel device that controls activation of a connected input/output control device and data transfer between the device and the main storage device, a microprocessor that controls the entire channel device and controls input/output from the CPU. Issues a first request to read the corresponding channel command word from the main memory in accordance with the command, and reads/writes transmission/reception data specified by the channel command word read from the main memory. a microprocessor that issues a second request to acquire the system bus; and a microprocessor that arbitrates between the first and second requests issued from the microprocessor to issue a third request to acquire the system bus, and a corresponding first or second request. 2
A DMA control means for executing request processing indicated by a request by DMA (direct memory access), and a system bus control means for controlling system bus acquisition in response to the third request issued from the DMA control means. and the DMA control means sets the priority of the first request to the priority of the second request.
A channel device characterized by treating requests with the same or higher priority.