JPH02285967A - Pwm control circuit for voltage type inverter - Google Patents

Abstract

PURPOSE:To eliminate saturation of line voltage by outputting the excessive component of the amplitude of each phase voltage command, which is higher than half of DC source voltage for an inverter main circuit, as an offset. CONSTITUTION:Assuming that Ed is DC source voltage for an inverter main circuit 2, an offset operating means 31 detects such portion of phase voltage output commends Vr(1)-Vr(3) as exceeding over Ed/2 if the amplitude of phase voltage command Vr(m) of a poly-phase PWM inverter is larger then Ed/2, and produces on offset Vofst. Subtracting means 32-34 subtract the excessive compo nent Vofst from each phase voltage commands Vr(1)-Vr(3). Since the magnitude of the control signals Vr(1)-Vr(3) does not exceed over Ed/2 and the comparing means is not saturated, first and second phase line voltages and an average waveform can be produced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to pulse width modulation (PWM) of voltage source inverters.
Regarding control circuits.

(Prior Art) A conventionally known pulse width modulation control circuit (hereinafter simply referred to as rPWM circuit) for a multiphase voltage source inverter will be described with reference to FIG. The figure shows a voltage-type PWM inverter system (number of phases n=2°3.4...), and the PWM circuit 1' is a carrier signal generating means 12.
．． Each switching element S constitutes the inverter main circuit 2 and is constituted by the comparing means 13 to 15 and the driving means 16.
LxgSx□, S2□, S! ! ,...Snx, Snz
The output voltage of the inverter main circuit 2 is controlled by outputting pulses to the inverter main circuit 2.

The operating waveforms of each part of the PWM circuit 1' are shown in FIG.
That is, the PWM circuit 1' uses voltage commands Vrx to Vrn for each phase, in which 172 of the DC power supply voltage Ed is given as a reference potential, and a triangular carrier signal Vc (
PWM signal signals -1 to Pn switching elements S1t, Sxz, S2□, Stz, . . .
・, Determine the opening/closing of Sn□ and Snz, and adjust the output voltage of each phase V
The inverter main circuit 2 is controlled by applying pulses from the driving means 16 to each of the switching elements so that the average value of Vr□ to Vn matches each phase voltage command Vr□ to Vrn.

(Problem to be Solved by the Invention) However, in the conventional PWM circuit 1', as shown in FIG.
Each phase voltage command V
When the amplitude of rx to Vrn exceeds (DC power supply voltage Ed)/2, each phase output voltage v1 to V of the inverter main circuit 2
n becomes saturated.

Therefore, in the past, it was not possible to obtain each phase output voltage v1 to Vn with a peak value larger than (DC power supply voltage Ed)/2, and the line voltage was also saturated according to these voltages v1 to Vn. Therefore, there was a problem that a wide range of control was not possible. Note that FIG. 4(b) shows the average waveform of the first phase output voltages v1 and 1 of the inverter main circuit 2 at this time.

The present invention was proposed in order to solve the above problems, and aims to provide a pulse width modulation control circuit for a voltage source inverter that eliminates line voltage saturation and expands the control range. purpose.

(Means for Solving the Problem) In order to achieve the above object, in the present invention, when the amplitude of the output voltage command of a certain phase exceeds 1/2 of the DC power supply voltage Ed, the excess of the phase voltage command is offset. By subtracting from the phase voltage command of each phase, the output voltage of the phase where saturation occurs is suppressed within the range of ±(DC power supply voltage Ed)/2, and at the same time, the excess voltage is transferred to other phases that are not saturated. I decided to make it up to him.

That is, the present invention relates to a pulse width modulation control circuit that inputs a carrier signal and a reference signal to a comparison means to generate a pulse width modulation signal, and controls a voltage source inverter main circuit based on this pulse width modulation signal.

offset calculating means for outputting as an offset an excess amplitude of each phase voltage command greater than 172 of the DC power supply voltage of the inverter main circuit; and generating the reference signal by subtracting the offset from each phase voltage command. The method is characterized by comprising a subtraction means.

(Function) First, the PWM circuit has n (n = 213141'') phase voltage commands Vr+m>(m = 1, 2.-, i, -, n
) has been received.

It is assumed that the PWM circuit outputs pulses for opening and closing to each switching element of an n-phase voltage type inverter whose DC power supply voltage is Ed.

Now, if the amplitude of a certain phase voltage command Vr<1 exceeds E+/2, the offset calculation means will calculate the phase voltage command Vr+a+
A portion where the magnitude (absolute value) of + exceeds Ea/2 is detected and an offset vafst is output. Here, the offset V o f s t is, for example, the phase voltage command Vr of the i phase.
When +i+ exceeds Ed/2.

Vorst= Vr+i> −Ed/ 2
(1), and when the phase voltage command ■r(1) becomes smaller than -EH11, VIltst=Vr<ir+Ed/2 (2
) and is output to the subtraction means.

Each subtraction means calculates the difference vr (ugly) between each phase voltage command vr (iris) and the above offset Vofst
(3) are calculated respectively.

Therefore, the i-phase reference signal Vr(i+' is determined by the equation (3) where m = i, and from the equations (1) and (2), when Vr+i> exceeds EH11, Vr(i)' =Ec+/2 (
4), when Vrci) becomes smaller than -Ed/2.

Vr(i)' = -Hd/2
(5) becomes.

At this time, there is another phase 1 other than the i phase, for example, the j phase.

The k-phase control signal Vr (j+', +' to Vr+ is (3)
Formulas where m = j or k in the formula, and (1), (2)
From the formula, when Vr(i> exceeds Ed/2.

Vr+j>' = Vr(j)-V@fnt=Vr+j
)-Vrci)+Ed/2 (6)Vrck)'
= Vr(kt-V*fst=Vr(kt-Vr
(i) + Ed/ 2 (7), Vr + i)
When becomes smaller than Ed/2.

Vr+j+' = Vrcj+-Vofst=Vrcj
>-Vr(i>-Ed/2 (8)+' to Vr+
= Vr(k>-Vafst=Vr(k+-Vr(L
+ Ed/2 (9).

The subtraction means converts these calculation results into a reference signal vr (1
1)' is outputted to each comparing means, and each comparing means compares the reference signal V r <m>' with the carrier signal and provides a control pulse to each switching element constituting the inverter.

Looking at the line voltage on the AC side of the inverter at this time, for example, the i-phase and j-phase line voltage Vij is Vr (i+ is E
(4) - (6) or (5) when Vr(i) exceeds d/2 and when Vr(i) becomes smaller than Ed/2.
- From (8).

Vij=Vrci+-Vr(j+ (
to).

In addition, the voltage between the j phase and the k phase V j k is Vr (i) is Ed
/2 or when Vr+i+ becomes smaller than Ed/2, (4)-(7) or (5)
- From (9).

Vjk= Vrtj+ −Vr<k>
(11).

Therefore, when the magnitude (absolute value) of the i-phase voltage command Vr(i+) exceeds 172 of the inverter's DC power supply voltage Ed, the magnitude of the phase voltage command Vr(m+(m≠i) of the other phase When it is smaller than 172, as can be seen from equations (10) and (11), it is possible to suppress the occurrence of saturation in the comparison means as in the conventional case, and each l1ArJj voltage command vIIIm', that is, Vru+++-Vr+rs' +(
m, m'=1. .

..., n, m≠m r ), the phase voltage output of the inverter is obtained that more closely matches. Furthermore, lVr+i+
-Vrtj>I≦Ed or IVr+i+ -Vrck>
If the relationship I≦Ed is always satisfied, the above (6) to (9)
) equations vr(j)' and Vrtk+' are never larger than Ed, so VrtJr' and Vr(k)' are never saturated in the comparing means, and the line voltage command Vr+m+-Vr(+s' +(m, m'=1,...
, n, m≠m') can be obtained.

Note that the amplitude of the phase voltage command Vr++u is the DC power supply voltage Ed.
If the offset does not exceed 1/2 of
Therefore, each phase voltage command is input as is to the comparison means as in the conventional case.

(Example) Figure 1 shows an example of the present invention, in which a voltage source inverter (
The PWM circuit 1 that controls the number of phases (n=3) includes a carrier signal generating means 12, comparing means 13 to 15, and driving means 16 similar to those shown in FIG.
It has a circuit configuration in which subtracting means 32 to 34 are added. Note that the configuration of the inverter main circuit 2 is substantially the same as that in FIG. 3.

When the DC power supply voltage of the inverter main circuit 2 is Ed, the offset calculation means 31 determines whether the phase voltage commands Vr(1) to Vl-(3) of the first to third phases exceed ±Ed/2. is detected and outputs an offset V6 (st) according to the detection result, and the subtracting means 32 to 34 calculate each phase voltage command Vrcb=
The offset V a l s t is subtracted from Vr(3), and the subtraction results Vr<L)' to Vrc3>' are output to comparison means 13 to 15, respectively.

Comparison means 13 to 15 compare the above Vr(1+' to Vrch'
is compared with the triangular wave carrier signal Vc generated by the carrier signal generating means 12 as a reference signal, and a PWM signal P~P3 for controlling the output of each phase of the inverter is created. The driving means 16 drives each switching element S4 based on these PWM signal signals -1 to P3. S1□.

Outputs pulses for Sat, Szz, S3□, and 8 ports.

Here, the operation of each part is determined by the phase voltage command Vr (+l) (m =
Depending on the amplitude of L2.3), it becomes as follows.

1) Offset Vsfs output by the offset calculation means 31 when the amplitude of the phase voltage command vr (+1) is ≦Ed/2
t becomes O, and the comparison means 13 to 15 obtain the phase voltage command Vr(
1) ~Vr+: PWM signal signals -1 to P3 are generated by directly comparing h with the carrier signal Vc.

2) When the amplitude of the phase voltage command Vruw+ is >Ed/2 FIG. 2 shows the waveforms of various parts in this case.

This will be explained below with reference to the same figure.

The offset calculation means 31 outputs the phase voltage output command Vl-(1)
~Vrr: A portion where the magnitude of h exceeds E, .+/2 is detected and an offset V a f s t is output.

For example, if the magnitude of #i voltage command Vt-(1) of the first phase exceeds Ed/2, ■Vr(1>>Ed/2, Votst=Vrt1) Ed/2 (12) ■
When Vr(1)<E d/2, Vafst=
Vrcl)+Ed/2 (13).

The subtraction means 32-34 each phase voltage command Vr(1)-Vr
(3) and Vafst of the above equation (12) or (13) are subtracted, respectively. That is, each of the subtracting means 32 to 34 uses the reference signal Vr as 1)' to Vrr:b', and in the case of (2) above, Vr(l)' : Vrrl)-V++fi
t= Ed/ 2 (14) Vrc2+' =
Vr(2)-Vatst=Vrth-Vr(1)+
Ed/2 (15) Vr(:b' = Vr+
3+ −Vofst=Vr(3)−Vrcl++Ed/
2 (16) respectively, and in the case of (■) above, Vrr1+'=Vrcl)-Vafst=-Ed/
2 (17) Vrt2>' = Vrc2+ -V
afst=Vr<2)-Vrrb-Ed/2
(18) Vr(3)' = Vrt:b −Vafst
=Vr+3+-Vr+1+-Ed/2 (19
) are output respectively.

At this time, the line voltage of the inverter main circuit 2 is 2°V.
zz * V a 1 is V,, = Vrrl>'-Vrt2>' = Vr
t1> -Vrt2)V,, = Vr(2+' -V
rt:h' = Vr+2+ -Vr(:bV,,=
Vr(3>'-Vr+1+' = Vr+3+ -V
r<b.

All three phases are lVr+j+ -Vr(k+l≦Ed(jt
When k=1.2,3゜j≠k), (14)
~As seen from equation (19), the control signal Vrd+'~
Since the magnitude of V r< 3 >' will never exceed Ea/2 (that is, it will never be saturated by comparison means),
The line voltage v of the first phase and second phase illustrated in FIG.
1□ and its average waveform can be generated.

In this way, since the offset is canceled between each phase, the line voltage command (Vr (l) - Vr (2), Vrch - V
r(3) pVrc: line voltage V as h-Vrcld
11 T V 23 +vJ□ can be obtained, making it possible to significantly expand the control range.

In the above embodiment, a PWM circuit of a three-phase inverter was explained, but it goes without saying that the present invention can also be applied to a multi-phase inverter other than three-phase.

(Effects of the Invention) As described above, according to the present invention, when the phase voltage command of the multiphase PWM inverter exceeds 1/2 of the DC current gWt pressure,
Since we decided to subtract the excess from the phase voltage command for each phase, the maximum value of each line voltage does not saturate in the range below the DC power supply voltage.

This has the effect of expanding the output control range of the inverter.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of a voltage source PWM inverter system showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing the operation of each part in Fig. 1, and Fig. 3 is a diagram for explaining a conventional PWM circuit. Configuration diagram of voltage source PWM inverter system, No. 4
The figure is a waveform diagram showing the operation of each part in FIG. 3. 1...PWM circuit 2...Inverter main circuit 1
2...Carrier signal generation means 13-15...Comparison means 16...Driving means 31...Offset calculation means 32-34...Subtraction means

Claims (1)

[Claims] A pulse width modulation control circuit that inputs a carrier signal and a reference signal to a comparison means to generate a pulse width modulation signal, and controls a voltage source inverter main circuit based on this pulse width modulation signal, an offset calculation means for outputting as an offset an excess amplitude of each phase voltage command which is larger than 1/2 of the DC power supply voltage of the inverter main circuit; and a reference signal by subtracting the offset from each phase voltage command. 1. A pulse width modulation control circuit for a voltage source inverter, comprising: subtraction means for generating pulse width modulation.