JPH02285887A - Method and circuit device for forming auxiliary signal - Google Patents

Abstract

PURPOSE: To reduce residual time errors within several ns in case of time error correction by inserting a data signal, which is provided on the output side of a programmable fixed value memory, into the data stream of digital video signals as an auxiliary signal within a horizontal frequency flyback erasure period. CONSTITUTION: Inside a programmable fixed value memory 9, a data word having the amplitude value of curved line passage characteristics of the auxiliary signal is stored while depending on an address. In this case, eight amplitude values are respectively filed in this programmable fixed value memory 9 for each vibration cycle of a reference signal. By applying an address signal, these amplitude values are used as data words in case of reading. The data extracted from the output side of the programmable fixed value memory 9 are guided to a register 12 in the format of eight low-order bits. A clock pulse signal CLK prepared by a logic step 6 is guided to a reset step 7, address counter, programmable fixed value memories 9 and 10, control step 11 and register 12.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Field of Application The invention is based on the method specified in the preamble of claim 1.

PRIOR ART In an earlier patent application filed by the present applicant (German Patent No. P373 (5741)), an apparatus for detecting time base errors in HDTV video signals extracted from magnetic tape is proposed.
The video signal has a reference signal consisting of packets of plural sinusoidal oscillations, similar to the color synchronization signal in color video No. 1G, in the region of the horizontal return interval. In contrast to the color synchronization signal which is transmitted on the rear black shoulder, ie on the back porch, this reference signal is superimposed galvanically on the average gray value within the horizontal blanking interval. The frequency of the reference signal is combined with the frequency of the clock pulse signal using the following equation.

1 clock pulse auxiliary signal (Σ (2n+4))
=f n=0 Therefore, the clock pulse frequency is f. Tsuku/'? tb
If 2=27 MHz and the integer n=i, then the frequency of the reference signal is f auxiliary signal=6-375 MHz.

This frequency f. The clock pulse signal with the
It is combined with a frequency that is 864 times the horizontal frequency of the video signal. A reference signal added to the horizontal frequency #IIN erasure section on the recording side is used to calculate the time error present in the reproduced HDTV video signal. In this case, the respective time error is calculated using a special phase detector using the phase of the reference signal to be reproduced.

Problems to be Solved by the Invention It is an object of the present invention to calculate the curve profile of a sine wave of a reference signal with extremely high phase and amplitude accuracy in a method of the type described in Section 1, and to further convert the reference signal into a synchronizing signal. It is also added to the video signal as an auxiliary signal.

Means for Solving the Problem This problem is solved by the features indicated in the characterizing part of claim 1.

This configuration has the following advantage: the reference and synchronization signals added on the recording side can be derived in digital form, i.e. with high precision, reducing the residual time error during time error correction.
It has the advantage of reducing - to several nanoseconds.

Claim 1 may be structured as indicated in the dependent claims. Particularly advantageous is the dynamic region of the digitized video signal defined by the 8-bit wide data words - this corresponds to the black value Ov.
An additional synchronization pulse with a negative amplitude -0.3v is required, which lies outside the dynamic range of this 8-bit scheme, with an analog image area of 0.7v corresponding to the white value. Sometimes there are benefits that do not need to be limited.

Description of examples Next, an embodiment of the present invention will be explained using all the drawings.

In the block diagram of FIG. 1, a video signal in digital form having a word width of 8 bits is applied to terminal 1.

Into the horizontal frequency blanking section A of this video signal, an auxiliary signal in the form of a negative synchronization pulse S of the horizontal frequency synchronization signal and a reference signal R in the gray phase G are inserted. The reference signal R is the period I21i! It contains ft1o sinusoidal vibrations with a frequency of 3375 MHz.

In FIG. 2a, the horizontal frequency blanking interval A is shown together with the front uncolored area "[Jv, the synchronization pulse S, the reference signal R, the gray phase G and the rear black shoulder DN. The gray stage G exists in the range of amplitude from 0% to 100% in the image area, which corresponds to the level Ov ~ 0,7v, and when the image amplitude is 50%, it corresponds to 0.35 V The synchronizing pulse S of the synchronizing signal occupies an amplitude range of Ov to -0,6v of the entire amplitude range IVss.

As mentioned in the introduction, this reference signal is combined in frequency and phase with the horizontal synchronization signal of the HDTV video signal. For this reason, the horizontal synchronization signal HD transmitted to terminal 2 at the same time as the digital video signal is
be led to. From the output side of this loop, the signal is phase-coupled with 864 times the horizontal frequency of the HDTV video signal.
A clock pulse signal CLK having a clock pulse frequency of 27 MHz is taken out. This clock pulse signal C'LK and the horizontal blanking signal A applied to terminal 4
H and also the vertical synchronizing signal 2v led via the terminal 5 are combined in the logic stage 6 to form one control signal. This control signal is transferred via the reset stage 7 to the control input of the address counter 8.

The output of the address counter 8 is connected via a 9-bit data bus to a programmable fixed value memory 9.
and 10, and on the other hand to the control stage 11. The control stage 11 controls the address value ?? provided at the end of the vibration packet. To detect. Its purpose is to set the address counter 8 to a predetermined W via the reset stage 1.
This is to reset the initial address value.

Data words with the amplitude values of the curve profile of the auxiliary signal are stored in the programmable fixed value memory 9 as a function of the address.

In this case, eight amplitude values are stored in this programmable fixed value memory 9 for each oscillation period of the reference signal. These amplitude values are used as data words when reading by applying an address signal.

The data retrieved from the output of the programmable fixed value memory 9 is passed to the processor 12 in the form of eight lower order bits. Most significant bit MSB money Zosta 12
is received from a programmable fixed value memory 10 in which, depending on the address, the pulse profile of the negative synchronization pulse is stored.

Reset stage 7. Address counter, programmable fixed value memory 9 and 10. Control stage 11 and register 1
2, the clock pulse signal C prepared by logic stage 6
LK is guided.

Register 12, like another register 13 in the signal path of the digital video signal, has a three-state output. This output side has this overconnection. Registers 12 and 13 therefore take on the function of a demultiplexer as follows. The demultiplexer switches between applied input signals depending on the logic level of the horizontal blanking signal AH. , # The data signal sent from the fixed value memory 10 capable of Zorogramming as the upper bits reaches directly via the register 12tl- to the input for the most significant bit value of the KD/AD/A converter. This D/A converter is also cyclically controlled by the clock pulse signal CLK Vc. The D/A converter 14 therefore has a data input for receiving a 9-bit wide data word. The analog value converted by the D,/A converter 14 according to the applied data word is passed through a low-pass filter 15 and after fIit
Via a connected equalizer stage 16 it is led to a clamping stage 17. This clamping stage then clamps the video signal, which is now present in analog form - with the horizontal frequency flange pulse signal Hc in the area of the front black shoulder PV - to a predetermined DC potential.

The D/A converter 14 has an amplitude decay curve that follows a 5in(X)/X function. The low-pass filter 15 connected downstream of the D/A converter 14 also has a predetermined amplitude decay profile. This low-pass filter 15 is about 10-
It is a 7-pole Tievisiev filter with a linear frequency profile up to 5 MHz. Amplitude attenuation losses due to A/D converter 14 and low pass filter 15 are then compensated for in equalizer stage 16 by a puzzling frequency response rise to the cutoff frequency.

An analog video signal is taken off at the output of the clamping stage 17. This analog video signal includes a synchronization pulse S, a reference signal R and a gray stage G in the region of the horizontal frequency blanking interval, as shown in FIG. 2a.

FIG. 2C shows the horizontal synchronization signal H on a corresponding time scale which shows, under varying time scales, a plurality of horizontal periods of the video signal at the output at the terminal 18. The horizontal blanking signal AH is shown in FIG. 2d. In this case, the blanking signal is indicated by A and the scan line period by H.

An auxiliary device having a reference signal and a synchronization signal of horizontal frequency and a fixed time allocation of said reference signal and synchronization signal in relation to a fixedly defined scanning instant in the auxiliary signal being formed. The derivation of the signal in analogue form produces a sinusoidal waveform that is substantially independent of the tolerances of the analog components, so that the phase and girth characteristics of the formed auxiliary signal are influenced in a component-dependent manner. disappears.

Due to the auxiliary signal formed according to the present invention, the residual time error due to time error correction on the Nyu side of the HDTV magnetic tape device can be reduced to about 3 ms. This corresponds to approximately one-sixth of a pixel in an HDTV video signal.

Effects of the Invention The invention makes it possible to generate an auxiliary signal with which the residual time error during time correction can be limited to a few nanoseconds.

A voltage-time diagram for explaining the operation of the block diagram is shown.

3... Phase control loop, 6... Logic stage, T... Reset stage, 8... Address counter, 9.10... Fixed II memory, 11... Control stage, 12.13 ...Register, 14...D/A converter, 15...Low pass filter, 16...Equalizer.

Claims (1)

Claims: 1. A method for forming an auxiliary signal which is combined in frequency with a synchronization signal of a video signal and added to said video signal in the region of a horizontal frequency blanking period, comprising: deriving a combined clock pulse signal such that the frequency of the clock pulse signal is multiple times the frequency of the auxiliary signal; and during the blanking period of each horizontal frequency, said derived clock pulse signal a fixed value memory (9) which is programmable and stored in dependence on the signal profile of said auxiliary signal;
, 10), and the programmable fixed value memory (9, 1).
0) is inserted into the data stream of a digital video signal as an auxiliary signal within a blanking period of the horizontal frequency. 2. A method as claimed in claim 1, characterized in that the frequency of the clock pulse signal is related to an integral multiple of the frequency of the auxiliary signal, for example 8 times. 3. File the signal profile of the reference vibration (R) in the auxiliary signal in the first programmable fixed value memory (9) and also in the second programmable identification value memory (10). A first programmable fixed value memory (9) for storing the signal profile of the synchronization pulse (S) in the auxiliary signal and also into the data stream of the digital video signal during the blanking period of the horizontal frequency. a data signal in the form of a reference signal (R) as the data value of the lower digit, obtained at the output of the second programmable fixed value memory (10); 2. A method as claimed in claim 1, characterized in that data having a data signal in the form of a synchronization pulse (S) as a digit data value is subjected to D/A conversion. 4. A circuit arrangement implementing the method according to one of claims 1 to 3, further comprising a clock pulse generator (3) which is coupled to a horizontal synchronization pulse of the video signal, the clock pulse generator (3) being coupled to a horizontal synchronization pulse of the video signal. An address counter (8) is provided for counting the clock pulses taken from the generator (3), and a first programming for storing the curve profile of the reference vibration (R) in the auxiliary signal. A possible fixed value memory (9) is provided, in which case the address input of the first programmable fixed value memory is connected to the address output of the address counter (8), and A second programmable fixed value memory (10) is provided for storing the curve profile of the synchronization pulses in the auxiliary signal, an input of this second programmable fixed value memory (10) being provided. Address counter on the side (8)
A demultiplexer device (12, 13) which can be switched depending on the horizontal frequency blanking signal is also provided, and a D/A
The converter (14) is a demultiplexer device (12, 13)
A low-pass filter (15) is provided on the output side of the D/A converter (14) and is further connected to the output side of the D/A converter (14), and the filter is configured to control the blanking period of the horizontal frequency. Synchronous pulse (S
) and a reference vibration (2). A demultiplexer device (12, 13) is provided having a first register (13) with a 5.3-state output, to which the digital video signal is guided via an 8-bit wide data bus. In addition, the demultiplexer device has a second register (12) with a three-state output, the input side of which is connected to the first and second programmable fixed value memories (9, 10).
In this case, a part of the output side of this fixed value memory is led to the input side of the D/A converter (14) in parallel with the output side of the first register (13). and further in this case, the other part on the output side of the memory is provided for directly transmitting the data of the highest digit to the other input side of the D/A converter (14). 4. The circuit device according to 4. 6. According to claim 4, further comprising an equalizer stage (16) downstream of the low-pass filter (15) for linearizing the frequency characteristic of the upstream transmission device. circuit device.