JPH02285750A - Communication controller - Google Patents

Abstract

PURPOSE:To send a data within a permissible range from the transmission of a synchronizing signal by supplying a data retarded for a required value to a terminal equipment applied with a synchronizing signal controlled with a synchronizing signal end signal from a transmission control section at the trailing of the transmission data. CONSTITUTION:When a data TXD is sent from a microcomputer 10 at a transmission control section, a synchronizing signal generating circuit 11 outputs a low level synchronizing signal SYN via a FF 13, a gate circuit 14 and an inverter 16 at the trailing of a start bit of a data TXD and the signal is fed to a terminal equipment 12 consecutively with a low level till the synchronizing signal end signal outputted from a terminal P3 of the computer 10 after a prescribed period is applied. On the other hand, the data TXD is retarded by a prescribed period at a data transmission circuit 16 provided with the counter 17 and the shift register 18 controlled by the clock, fed to the terminal equipment 12 and the communication controller able to send a data within a permissible period range from the transmission of the synchronizing signal with high reliability is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a communication control device with improved data transmission timing.

(Prior art) For example, a communication control device used in a vending machine device consists of a main control unit installed on the door side of the vending machine and a terminal installed in the vending machine body. . A selection switch and a vending switch are connected to the main control unit, as well as a coin mech for processing coins, etc. In addition, a sold-out switch, a solenoid coil for transporting products, etc. are connected to the terminal. Then, data such as the operation details of the selection switch is transmitted from the main control section to the control section of the terminal through the communication line. FIG. 4 is a schematic configuration diagram of such a communication control device, in which a synchronization signal is sent from the main control section 1 to the terminal 2 when transmitting data. Here, the transmission timing of the data, evening, and synchronization signals is set so that the synchronization signal is set at a low level and the data is transmitted after a predetermined period has elapsed, as shown in FIG.

The specific operation will be explained with reference to the transmission flowchart shown in FIG. 6. The main control section 1 sends out a low-level synchronization signal in step s1, and counts the signal from the timer 3 in step s2.

Then, as a result of counting, when a predetermined period t has elapsed, the main control section 1 sends out data in step S4.

As mentioned above, data is transmitted for a predetermined period [
However, in reality, it may not be sent after the predetermined period has elapsed.

The vestibule indicates the allowable period range from the time the synchronization signal is sent to the time the data is sent, and the actual period.

As can be seen from this table, in the case of standard A, the maximum value of the allowable period range is 530μ, far exceeding the standard value of 313μSee.
See, and in the case of standard B, the minimum value of the allowable period range is 1140 μ, which is much shorter than the standard value of 1667 μ See.
See. If the data is not sent within the allowable time range, it will be difficult for the terminal to receive the data accurately.

(Problems to be Solved by the Invention) As described above, there are cases where data is not sent within the permissible period from the time when the synchronization signal is sent, making it difficult for the terminal to accurately receive data.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a highly reliable communication control device that can send data within a permissible period from the time when a synchronization signal is sent.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a transmission control unit that transmits data, transmits an end signal of a synchronization signal after transmitting the data, and generates a clock signal, and a synchronization signal generation circuit that detects the synchronization signal, generates a synchronization signal, sends it to the terminal, and ends the generation of the synchronization signal upon receiving the synchronization signal end signal, and delays the data by a predetermined period based on the clock signal and sends it to the terminal. A communication control device is provided with a data transmission circuit to achieve the above object.

(Function) By providing such a means, when data is sent from the transmission control section, the synchronization signal generation circuit detects the falling edge of the data, generates a synchronization signal, and sends it to the terminal and transmits it. Upon receiving a synchronization signal end signal from the control section, generation of the synchronization signal is terminated.

Further, the data transmission circuit delays the data by a predetermined period based on the clock signal from the transmission control section and transmits the data to the terminal.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a communication control device. 10 is a microcomputer, and this microcomputer 10
has the function of transmitting data TXD from the terminal P, and after transmitting this data TXD, transmitting the end signal e of the synchronizing signal SYN and transmitting a 400 ns clock signal from the CLK terminal.

Reference numeral 11 denotes a synchronization signal generation circuit, which detects the falling edge of data TXD, generates a synchronization signal SYN, sends it to the terminal 12, and generates an end signal e of the synchronization signal SYN.
It has a function of receiving the synchronization signal SYN and terminating the generation of the synchronization signal SYN, which is kept at a low level for a period of 625 μs to 1667 μs.

Specifically, a flip-flop 13 is provided, to which an end signal e of a synchronization signal is input as a set signal, and data TXD is input as an input signal. The output terminal of this flip-flop 13 is connected to the inverter 15 through one end of the gate circuit 14.
It is connected to the.

Note that the other end of the gate circuit 14 is connected to the microcomputer 1.
It is connected to the p terminal of 0.

On the other hand, 16 is a data transmitting circuit, and this circuit 16 has a function of transmitting data TXD to the terminal 12 with a delay of a predetermined period, for example, 104 μs to 313 μs, based on a clock signal. The specific configuration includes a counter 17 that divides the clock signal by 32, and a counter 17 that divides the clock signal by 32.
The shift register 18 shifts the output of the clock by 18 clocks and outputs the shifted signal. Note that when the microcomputer 10 sends data TXD, control signals and the like are exchanged with the terminal 12. If an abnormality occurs in the terminal 12 at this time, the microcomputer 10 sends p and the output signal a of the terminal. L
It has a function of forcibly resetting the signal to a low level for a period of ooses to 800m5.

Next, the operation of the apparatus constructed as described above will be explained with reference to the timing chart shown in FIG.

When sending data TXD, the microcomputer 10
sets the output e of the p2 terminal to a high level, and also sets the output a of the p terminal to a high level. As a result, the flip-flop 13 is set and the output a of the terminal p is input to the gate circuit 14 as a gate signal. In this state, the microcomputer 10 is at time 11 I)
Data TXD is sent from the + terminal. Note that the beginning of this data TXD is a start bit, and its level is low. However, this data TXD is sent to the flip-flop 13 and also to the shift register 18.

When the flip-flop 13 detects the fall of the start bit of the data TXD, it sets the output signal S to a low level. As a result, the output level of the gate circuit 14 becomes high level, and the inverter 15 outputs a low level synchronization signal SYN. The terminal 12 receives this synchronization signal SY.
When N is received, it is determined that data TXD will be sent within the allowable period from the time of reception.

On the other hand, the counter 17 divides the clock signal by 32 and sends it to the shift register 18. The shift register 18 shifts the data TXD by 18 according to the output of the counter 17, delays it, and sends it out. Specifically, dividing a 400ns clock signal by 32 results in 12.8μs, which is further divided by 1
By shifting by 8, the delay period t of data TXD becomes 230.4 μs. Therefore, after a period has elapsed since the low-level synchronization signal SYN was sent, the data TXD'
is sent to the terminal 12. Terminal 12 thus receives data TXD'. Then, the microcomputer 10 sets the output signal e of the p2 terminal to a high level at time t2 after a predetermined period of time has passed after sending out the data TXD, and sends this signal to the flip-flop 13 as the end signal of the synchronizing signal SYN. Ru.

As a result, the output of the flip-flop 13 becomes high level, and the synchronizing signal SYN becomes high level. In this way, a synchronization signal SYN with a period range of 625 μs to 1667 μs is created.

By the way, the microcomputer 10 sends and receives control signals and the like to and from the terminal 12 when transmitting data TXD, but if an abnormality occurs in the terminal 12 at this time, for example, at time t3, the terminal p, The output signal a is set to low level. As a result, the synchronization signal qsYN becomes high level, and the transmission of data TXD is forcibly reset at this time t3.

In the above-mentioned embodiment, when the data TXD is sent, the start bit of the data TXD is detected, the synchronization signal SYN is sent to the terminal 12, this synchronization signal is terminated by the end signal e, and the data Since TXD is delayed by a predetermined period t based on the clock signal and sent to the terminal 12, data TXD can be reliably sent within the allowable period from when the synchronization signal SYN becomes low level. Furthermore, since the period of the synchronizing signal SYN and the period from when the synchronizing signal SYN is sent to when the data TXD is sent are directly controlled by the microcomputer 10, it is not affected by external noise and costs can be reduced. .

Next, a case where the above embodiment is applied to a vending machine will be described with reference to FIG. 3. The figure shows the vending machine divided into a door side and a main body side, and the main control section 20 is provided on the door side. This main control section 20 includes a microcomputer 10, a synchronization signal generation circuit 11, and a data transmission circuit 16 shown in FIG. The main control unit 20 is connected to an amount display 21, a coin mech 22, a selection switch, a sales lamp, a sold-out lamp, and the like. On the other hand, a terminal control section 23 is provided on the main body side, and this terminal control section 23 and the main control section 20 are connected via a communication line 24. A bill validator 25 for processing banknotes is connected to the terminal control unit 23, as well as a sell-out switch, a solenoid, and the like.

With this configuration, the main control section 20 sends a low-level synchronization signal SYN to the terminal control section 23, and after a predetermined period has elapsed, sends data TXD to the terminal control section 23. However, the terminal control unit 23 operates a solenoid or the like according to the contents of the data TXD to carry out the product.

As described above, if the device shown in FIG. 1 is applied to a vending machine, data TXD can be reliably transmitted while being compatible with the communication system of the vending machine.

Note that the present invention is not limited to the above-mentioned embodiment, and may be modified without departing from the spirit thereof.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a highly reliable communication control device that can transmit data within a permissible period from the time of transmitting a synchronization signal.

[Brief explanation of drawings]

1 to 3 are diagrams for explaining the communication control device according to the present invention, in which FIG. 1 is a configuration diagram, FIG. 2 is an operation timing diagram, and FIG. 3 is a communication control device applied to a vending machine. FIGS. 4 to 6 are diagrams for explaining the conventional technology. DESCRIPTION OF SYMBOLS 10... Microcomputer, 11... Synchronous signal generation circuit, 12... Terminal, 13... Flip-flop, 14... Gate circuit, 15... Inverter, 1
6...Data transmission circuit, 17...Counter 1.18
...Shift register. Applicant's Representative Patent Attorney Takehiko Suzue Figure 4 Figure 1 Figure 2 Figure 5

Claims (1)

[Claims] a transmission control section that transmits data and, after transmitting the data, transmits an end signal of a synchronization signal and generates a clock signal; a synchronization signal generation circuit that receives a signal end signal and ends the generation of the synchronization signal;
A communication control device comprising: a data transmission circuit that delays the data for a predetermined period based on the clock signal and sends the data to the terminal.