JP2560141B2 - Data compensation method in asynchronous data transfer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A data compensation method in start-stop synchronous data transfer between a terminal and a control device in which a large number of terminals are connected to the control device. The purpose is to provide a data compensation method in asynchronous data transfer that enables long data to be transmitted using an asynchronous signal even when connected, and each terminal starts the first byte of data. Equipped with a transmission / reception control unit that transmits and receives by synchronizing the internal clock with the bits,
A data counter that determines the predetermined number of bytes (N) at which the synchronization deviation is less than or equal to the allowable value according to the internal clock accuracy of each terminal, counts the transmission data from the terminal, and outputs when the predetermined number of bytes is reached. When the output from the data counter is generated, the generation of the transmission data is stopped for a predetermined time so that the data is divided and transmitted.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compensation method in start-stop synchronous data transfer between a terminal and a control device in which a large number of terminals are connected to the control device.

A system that installs one control device in the center, connects many terminal devices in a potato system (daisy chain), collects data input from many terminals, and outputs the processing result to each terminal, For example, it is used in various fields such as voting systems (betting tickets, etc.).

In such a system, the data length transmitted between the control device and the terminal is usually short (several pick-up bytes to hundreds of bytes), the configuration of the synchronization relationship is simple, and it is possible to arbitrarily select it without being aware of the other side. Asynchronous data transmission is used because it can be transmitted.

However, the data transmitted from the terminal (or from the control device) may be long, and in that case, accurate synchronization may not be achieved.

[Prior Art] FIG. 4 is an explanatory diagram of a conventional example.

A of FIG. 4 shows a system configuration in which a potato is connected, and a large number of terminal devices are sequentially connected to the control device 40.
41 is connected by a vine-line going line 42. This terminal device 41 is provided with a driver / receiver (D / R), and the data sent from the control device 40 to each terminal device 41 is taken in by the corresponding destination terminal device 41, and the data is sent from the terminal device 41 to the control device 40. The data addressed to is transmitted to the control device 40 via the return line 43 via the potato connection in sequence.

Each terminal device 41 discriminates whether the data is destined from the control device 40 to its own terminal device, the data destined to another terminal device, or the data sent to the control device 40, and controls a gate (not shown). By doing so, control is performed to take in the data to the own terminal device via the receiver or to flow the data to another terminal device (from the driver). In the case of A., the data sent to the control device 40 is transmitted via the return line 43 as shown in the figure, but the data sent from each terminal device 41 to the control device 40 is transmitted to the return line 43. There is also a technology to output directly. In such a system, data is transferred by the start / stop synchronization interface signal structure as shown in C. of FIG. That is, low (LO
The data bit (8 bits + 1 parity bit) is followed by the start bit of W level, and finally the stop bit of high level is provided.

However, in terminal devices such as A., the waveform distortion in the driver / receiver of each terminal device gradually increases, so the number of connected devices is limited. Therefore, in order to connect a large number of terminal devices, for example, 100 or more terminals, a compensating circuit 411 for compensating for driver / receiver distortion as shown in B. of FIG.
Need to have.

The compensating circuit 411 is synchronized with the start bit of the first byte and is corrected by the internal counter.

[Problems to be Solved by the Invention] In the configuration shown in B. of the above-mentioned conventional example, a clock having a transfer frequency is required for the compensation circuit. Even if a crystal oscillator with a very high precision is used, each oscillator cannot have completely matched frequency characteristics. In addition, since synchronization is performed with the start bit of the 1st byte, counting is performed with the internal clock, so if the transfer data becomes long, a synchronization deviation occurs. That is, when a large number of terminal devices are connected and transferred to a plurality of terminals, they are sent as long continuous data. Since the continuous data is sampled by the internal clock of each terminal device, a long message cannot be synchronized due to the clock shift between the devices. Therefore, the data length that can be transferred at one time can be limited, and it is necessary to divide the data by software and repeat the transfer procedure (including control signals for characterizing the other party) many times.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data compensation method in an asynchronous data transfer that enables long data to be transmitted using an asynchronous signal even when a large number of terminal devices are connected to the control device. And

[Means for Solving the Problems] FIG. 1 is a principle configurational diagram of the present invention.

In FIG. 1, 10 is a terminal device, 11 is a transmission / reception control unit, and 12
Is a data output unit, 13 is a data counter, and 14 is a stop signal generating means.

The present invention, when transmitting data, has a constant bit deviation (eg, 50%) corresponding to the clock accuracy in the terminal.
A constant data length (number of bytes N) that can be compensated is obtained in advance below, and the data is divided into smaller data lengths and transferred, and the data is resynchronized with the start bit of the next data divided.

[Operation] In the terminal device 10, the transmission / reception control unit 11 receives the data sent from the control device input from the adjacent terminal device (left side of the figure) and the data sent to the control device, and extracts the data addressed to the own terminal device. As for the data to be transmitted, the data output from the data output unit 12 is sent out to the transfer path to the adjacent terminal device (right side in the figure) by the start / stop synchronization signal in the transmission / reception control unit 11.

The frequency of the clock provided in the transmission / reception control unit 11 of the terminal device 10 depends on the degree of deviation with respect to the bit signal due to the accuracy of the basic oscillation circuit, and based on the accuracy, the number of bytes of data makes the 1-bit Calculate if the signal deviates by a constant percentage (50%). In that case, the difference between the sending side and the receiving side is considered (round-trip data length).

Thus, when the maximum data length N satisfying the above conditions is obtained, the number N is set in the data counter 13 of FIG. Then, the number of data output from the data output unit 12 and sent out from the transmission / reception control unit 11 is counted by the data counter 13, and when the set value N is reached, the stop signal generation means 14 is driven and the stop signal generating means 14 is driven for a certain length. A stop signal is generated and supplied to the data output unit 12. The data output unit 12 stops data output while the stop signal is generated. When the data output is stopped, the transmission / reception control unit 11 sends dummy data to the transfer path.

When the signal from the stop signal generating means 14 is completed, the data output section 12 starts data output again, and the subsequent divided start / stop synchronization signals are continuously sent out. Sequential transfer is performed while the division control by 14 is performed.

[Embodiment] FIG. 2 is a configuration diagram of the embodiment, and FIG. 3 is a timing chart of the embodiment.

In FIG. 2, 20 is a control device, 21 is a terminal device, 22 is a receiver for receiving data input from the control device, 23 is a driver for outputting data to a line to an adjacent terminal device, 24--
1 to 24-3 are gate 1 to gate 3, 25 is a waveform correction circuit for correcting the waveform of data passing through the terminal device 21, 26 is a data transmission / reception control circuit, 27 is a data length counter, 28 is a stop pulse generation circuit , 29 is a CPU that processes data of the terminal device, 30
Is a memory (MEM) for storing data received from the control device or data sent to the control device, 31 is a channel device, and 32 is an operation unit including a display unit and a keyboard.

The operation of the configuration of FIG. 2 will be described with reference to FIG.

The data transmitted from the control unit 20 is received by the receiver 22 of the terminal device 21 and input to the gate 1. The data transmission / reception control circuit 26 determines whether or not the data is addressed to its own terminal by the transfer control procedure as in the conventional case. If the data is addressed to another terminal, it controls gates 1 and 2 to correct the waveform. The waveform is corrected through the circuit 25 and sent from the driver 23 to the connection path connecting to the adjacent terminal device.

If the data is addressed to its own terminal device, the input data from the gate 1 is the data transmission / reception control circuit as shown in FIG.
It is input to 26, and then stored in the memory 30 via the data bus and the CPU bus.

The data input from the operation unit 32 of the terminal device 21 is stored in the memory 30 via the channel 31 and requests the data transmission / reception control circuit 26 to transmit via the control line. At the timing of data transmission (when there is no data on the line), the data transmission / reception control circuit 26 generates the signal shown in FIG. It is sent to the gate 3 as shown in FIG. This data request signal serves as a count input to the data length counter 27 and is counted. On the other hand, at this time, since the stop pulse is not generated from the stop pulse generating circuit 28, a data request is output from the gate 3 as shown in FIG. CPU29 for this data request
Memory 30 by DMA (dynamic memory access)
One byte of transmission data is taken out from and is supplied to the data transmission / reception control circuit 26 via the data bus.

The asynchronous signal from the data transmission / reception control circuit 26 is the third
When it is sent out as shown in the figure, the next data request signal (and) is generated and data is sent out from the memory 30 one byte at a time, and the data length counter 27 is counted up each time and the preset value is set. When it becomes N, the stop pulse generating circuit 28 is driven and the stop pulse as shown in FIG. As a result, the gate 3 is closed and the generation of the data request signal is prohibited.

In this case, the number N set in the data length counter 27 is
If the clock accuracy (crystal oscillator) is 150 PPM (a unit that represents a shift of 150 bits at 1,000,000 bits), the shift between the transmitter and the receiver and 1 byte 11 bits (start bit, 8 bits of data, 1 bit) Assuming that the deviation of up to 50% is compensated for as the parity and stop bit configuration of, it can be obtained by the following formula.

50/100> 150 × N × 11 × 2 (However, × 2 means sending and receiving) 151> N is obtained from this equation.

Therefore, in this case, N = 150.

In the embodiment of FIG. 2, when the number of data requests is counted by the data length counter 27 and the count value reaches 150, a stop pulse is generated.

The stop time must be stopped for 12 bits or more because the terminal device and control device in the subsequent stage detect that the data has been lost. After a certain period of time, the gate 3 is opened and the data length counter is reset. When the data transfer is restarted, the above operation is repeated from the memory 30 to the set data length under the control of the CPU 29.

[Effect of the Invention] According to the present invention, it is possible to compensate data by dividing and transferring data when a large number of terminals are connected to a control device by a potato connection to transfer data in start-stop synchronization and when transferring long data. ， Although it is an inexpensive potato connection using start-stop synchronization, it is possible to transfer long data without being aware of the software.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment, FIG. 3 is a time chart of the embodiment, and FIG. 4 is an explanatory view of a conventional example. In FIG. 1, 10: terminal device 11: transmission / reception control unit 12: data output unit 13: data counter 14: stop signal generation means

Claims (1)

(57) [Claims] 1. A data compensating method in start-stop synchronous data transfer between a terminal and a control device, wherein a large number of terminals are connected to the control device. Each terminal uses an internal clock as a start bit of the first byte of data. It is equipped with a transmission / reception control unit that performs transmission / reception in synchronization with each other, and determines a predetermined number of bytes (N) at which the synchronization deviation is less than or equal to an allowable value according to the internal clock accuracy of each terminal, counts the transmission data from the terminal, and determines the predetermined bytes A start-stop synchronous data characterized by providing a data counter that generates an output when the number of data reaches a number, and by suspending the generation of transmission data for a predetermined time when an output is generated from the data counter, dividing long data and transmitting the divided data. Data compensation method in transfer.