AU620754B2

AU620754B2 - Improved synchronization technique

Info

Publication number: AU620754B2
Application number: AU71919/91A
Authority: AU
Inventors: Stephen L. Spear; Charles L. Whittington
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1990-02-27
Filing date: 1991-02-26
Publication date: 1992-02-20
Anticipated expiration: 2011-02-26
Also published as: GB2241411A; GB9104085D0; AU7191991A; FR2658969A1; DE4105267A1

Description

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AUSTRALIA

Patents Act 620754 COMPLETE SPECIFICATION

(ORIGINAL)

Class Int. Class Application Number: Lodged: Complete Specification Lodged: Accepted: Published: Priority Related Art:

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U tq Applicant(s): Motorola, Inc.

1303 East Algonquin Road, Schaumburg, Illinois, 60196, UNITED STATES OF AMERICA Address for Service is: PHILLIPS ORMONDE FITZPATRICK Patent and Trade Mark Attorneys 367 Collins Street Melbourne 3000 AUSTRALIA 4*I

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Complete Specification for the invention entitled: IMPROVED SYNCHRONIZATION TECHNIQUE Our Ref 206094 POF Code: 1437/1437 The following statement is a full description of this invention, including the best method of performing it known to applicant(s): 600- 1 6006 la- IMPROVED SYNCHRONIZATION TECHNIQUE This application relates to a method for synchronizing nodes in a 10 network, such as a cellular radio telephrne system, containing a plurality I of nodes.

t I -Background of tho Invontion- Networked systems such as cellular radio telephone systems, for example, are well known. As is known, such systems typically have a I large number of nodes that are physically dispersed over a large geographic area. It will be appreciated that it is a requirement to control the timing relationships between the various components of such a system. Typically this means controlling all nodal clocks with respect to a system-wide "master clock", the clocks not necessarily being associated S; with those clocks which may be required to transport data through the network.

SAs a result, the timing relationship between all system clocks must i be synchronized not only in a relative sense but also in an absolute sense. Thus, each node in the system must be controlled so its clock has the same (or nearly the same) phase and frequency as the master clock.

CE02077R Further, each nodal clock must also be synchronized in the sense that it has the same absolute reading as the master clock.

According to one aspect of the present invention there is provided a method for measuring time delay of a channel coupled between a master node and a target node, comprising: at said master node: sending a first signal to said target node; at a time generally fixed with respect to step starting a first timer; at said target node: receiving said first signal; at a time generally fixed with respect to step starting a second timer; sending a second signal to said master node; at a time generally fixed with respect to step providing a holding time based on said second timer; :20 sending said holding time to said master node; at said master node: receiving said second signal; at a time generally fixed with respect to step providing an elapsed time based on said first timer; providing said holding time; o computing said time delay based on the difference between said elapsed time and said S .r.o holding time.

According to a further aspect of the present i invention there is provided a method for measuring time delay of a channel coupled between a master node and a target node, comprising: at said master node: sending a first signal to said target node; at a point in time generally fixed with respect to step starting a first timer; at said target node: 39 2 A 4" r:i;-i I I 20 o, 2 o le receiving said first signal; at a point in time generally fixed with respect to step starting a second timer; sending a second signal to said master node; at a point in time generally fixed with respect to step providing a holding time based on said second timer; at said master node: receiving said second signal; at a point in time generally fixed with respect to step providing an elapsed time based on said first timer; sending said elapsed time to said target node; at said target node: providing said elapsed time; computing said time delay based on the difference between said elapsed time and said holding time.

According to a still further aspect of the present invention there is provided a method for synchronizing a target node with a master node, said target node having a clock and coupled to said master node via a channel, said method comprising the steps of: at said master node: providing the time delay of said channel; sending said time delay to said target node; sending said target node a message indicating that it will send a predetermined signal at a predetermined time; sending said predetermined signal; at said target node: receiving said time delay; receiving said message; receiving said predetermined signal; adjusting said clock based on said predetermined time and said time delay.

According to a still further aspect of the present invention there is provided a method for synchronizing a C C 3 5 39 A 41Z' s ~ti~Al 2a 4, .20 target node with a master node, said target node having a clock and coupled to said master node via a channel, said method comprising the steps of: at said master node: sending said target node a message indicating that it will send a predetermined signal at a predetermined time; sending said predetermined signal; at said target node: providing the time delay of said channel; receiving said message; receiving said predetermined signal; adjusting said clock based on said predetermined time and said time delay.

According to a still further aspect of the present invention there is provided a method for synchronizing a target node with a master node, said target node having a clock and coupled to said master node via a channel, said method comprising the steps of: at said master node: sending a first signal to said target node; at a point in time generally fixed with respect to step starting a first timer; at said target node: receiving said first signal; at a point in time generally fixed with respect to step starting a second timer; sending a second signal to said master node; at a point in time generally fixed with respect to step providing a holding time based on said second timer; sending said holding time to said master node; at said master node: receiving said second signal; at a point in time generally fixed with respect to step providing an elapsed time based on said first timer; receiving said holding time; 2b

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computing a time delay for the channel based on the difference between said elapsed time and said holding time; sending said time delay to said target node; sending said target node a message indicating that it will send a predetermined signal at a predetermined time; sending said predetermined signal; at said target node: receiving said time delay; receiving said message; receiving said predetermined signal; adjusting said clock based on said predetermined time and said time delay.

According to a still further aspect of the present invention there is provided a method for synchronizing a target node with a master node, said target node having a clock and coupled to said master node via a channel, said method comprising the steps of: :20 at said master node: sending a first signal to said target node; at a point in time generally fixed with o respect to step starting a first timer; at said target node: receiving said first signal; i at a point in tine generally fixed with respect to step starting a second timer; sending a second signal to said master node; at a point in time generally fixed with respect to step providing a holding time at based on said second timer; at said master node: receiving said second signal; at a point in time generally fixed with respect to step providing an elapsed time based on said first timer; S(i) sending said elapsed time to said target node; at said target node: 39 2c rY, I I receiving said elapsed time; computing a time delay for the channel based on the difference between said elapsed time and said holding time; at said master node: sending said target node a messare indicating that it will send a predetermined signal at a predetermined time; sending said predetermined signal; at said target node: receiving said message; receiving said predetermined signal; adjusting said clock based on said predetermined time and said time delay.

The master node may start a timer while simultaneously sending a predetermined signal known as a "token" to a target node. Upon receipt of the token, the target may start a timer and store the token. The target may then wait for the next available time when it can 1.:20 return the token to the master. When it later returns the token to the master, the target may stop its timer, thereby generating a "holding time" for the token. Upon receipt of the token, the master may stop its timer, thereby generating an "elapsed time" for the token. The time delay for the channel interconnecting a target and the master may then be computed a one-half the difference between the elapsed time and the holding time. Moreover, based on this time delay information, the target may then by synchronized to the master.

A preferred embodiment of the present invention will now be described with reference to the accompanying drawings wherein: Fig. 1 is a block diagram showing a communications system comprising a plurality of nodes.

Fig. 2 is a block diagram showing a first embodiment of an improved synchronization technique, according to the invention.

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4 lc-- -3- Fig. 3 is a first flow diagram according to the invention.

Fig. 4 is a second flow diagram according to the invention.

Fig. 5 is a third flow diagram according to the invention.

Fig. 6 is a fourth flow diagram according to the invention.

Petai!Q d~r*n~n h rro~n T tV 1 r ift) *r V Fig. 1 is a block diagram showing a networked system, such as a cellular radio telephone communications system, comprising a plurality of nodes. The system includes a hierarchical set of nodes such as, for example, 111, 113, 115, 117, and 119, interconnected in a tree style via channels such as, for example, 101, 103, 105, and 107. Each node in the network may be interconnected, for example, by a T1 or CEPT- type channel or any other digital communications medium. In such a communications system it will be appreciated that it is necessary to maintain synchronization throughout the entire network. As will be seen, other types of channels may also be used. There is virtually no limit to the number of nodes that may be synchronized.

Referring still to Fig. 1, node 111 at the top of the tree structure contains a reference timing source. The present invention addresses a technique for synchronizing other nodes to this time source. In this context, the node containing the reference clock source is referred to as the "master" node, whereas the adjacent node that is being synchronized to the master node is referred to as a "target" node. Thus, if node 111 is in the course of synchronizing node 113, then in this context node 111 is referred to as the master node and node 113 is referred to as the target node. Although it is illustrated in Fig. 1 that node 111 at the top of the

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-3- CE02077R "4tree structure contains the reference timing source, any node in the network may contain the reference timing source. If, for example, node 117 in Fig. 1 were to contain the reference timing source, the sequence of synchronization would be first from node 117 to synchronize node 113, then for node 113 to synchronize node 111, followed by node 111 synchronizing other nodes to which it is attached.

Figs. 2 is a block diagram showing a master node 201 coupled to a target node 221 via a channel 261. It will be assumed the channel 261 is a T1-type facility with 24 time slots.

The method of the present invention centers on having node 201, designated as the master, synchronize node 221, designated as the target. The synchronization of the target 221 to the master 201 may be implemented with the algorithm herein described combined with special purpose timer hardware on each node's interface to its telecommunications interconnect. This synchronization method will not require that this interconnect be dedicated to the synchronization process, but only that a time slot within this interconnect and associated with channel 261 be assigned to the synchronization process. Moreover, the time slot need be utilized only for the duration of the synchronization task which typically will be a few seconds.

tO." Each node contains an interface to its interconnect which will be i referred to as the Inter Connect Controller (ICC), a computational A capability which will be referred to as the CPU, and a local clock source which which will be referred to as the CLK. Thus, master node 201 contains an ICC 203, a CPU 205, and a CLK 207. Similarly, target node 221 contains an ICC 223, a CPU 225, and a CLK 227.

CE02077R When the network is completely synchronized, all network CLKs will have a predetermined timing relationship.

According to the invention, the master first establishes a communications path 261 via a designated time slot of the telecommunications interconnect to the target. The master 201 then starts its timer 209 and simultaneously sends a predetermined signal, referred to as the "token", to the target 221. The process of the master node 201 initially sending the token to the target node 201 is represen'ted 4 *9 by the arrow 263 in Fig. 2.

Upon receipt of the token, the target node 221 starts its timer 229 S""o and stores the token. The target node then waits for the next available time slot by which it can return the token to the master node 201. The S.o process of the target node 221 temporarily holding the token until a point in time when it is abie to return the token to the master node 201 is represented by the arrow 265 in Fig. 2.

o:0o8. When the appropriate time slot becomes available, the target node 221 then stops its timer 229 and simultaneously sends the token to the l" master node 201. The time period during which the target node 221 holds the token before returning it to the master node is defined as the "holding time" arid may be conveniently measured by the timer 229. The F process of the target node 221 returning the token back to the master Rnode 201 is represented by the arrow 267 in Fig. 2.

Upon receipt of the token, the master node 201 stops its timer 209.

I' The period of time between the master node 201's initially sending the token to the target node 221 and subsequently receiving it back from the CE02077R

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-6target node 221 is defined as the "elapsed time", and may be conveniently measured by timer 209.

It will be appreciated that, once either node 201 or 221 learns both the holding time and the elapsed time, it can compute the time delay At for channel 261 based on one-half the difference between the elapsed time and the holding time. Moreover, rnce the target node 221 learns the value of At, the target node can be synchronized to the master node 201 as follows: The master node 201 informs the target node 221 that it will sr'isd a predetermined signal to the target at a predetermined time, 10 To. [i.b.dafter, the target node 221 waits to receive this predetermined signal. Upon receiving this signal, the target node 221 adjusts its clock 227 to the value To At.

This method may be used to achieve an absolute node-to-node synchronization resolution of better than 1 microsecond, and may be 1 5 used to synchronize an entire network of elements.

4 The ICC has three synchronize.tion modes, as follows: In the first mode, the ICC will contain the capability to generate a j unique bit pattern to be transmitted on a given interconnect time slot, ,start a timer when that pattern is transmitted, and stop the timer when that pattern is received back on the corresponding input time slot. The timer's t *resolution will be per the clock utilized on the interconnect (1.544 MHz for T1, 2.048 MHz for CEPT). The CPU can read 'his timer.

In the second mode, the ICC has the capability to start the timer when the unique bit pattern is received on a given interconnect time slot and stop the counter when that pattern is transmitted back on the -6- CE02077R -7corresponding transmit time slot as the result of an internal loop back mechanism. The CPU can read this timer also.

The third mode of the ICC extends its second mode to include issuing a signal to its CLK concurrent with the recognition of the unique bit pattern on the designated incoming time slot of the given interconnect.

The CLK will accept that signal and initialize its timing chain to a value preset by the CPU.

The interconnect interface on the ICC board would normally ooo, contain an elastic buffer to accommodate the timing differences between oooo 10 the incoming and outgoing data rates. To be more precise, the elastic o buffer is there to accommodate the "phase" difference between incoming ooo, and outgoing data. Due to the fact that the CLK is synchronized with the o ,««incoming interconnect, the incoming clock rate and the node's clock rates may be considered equal in frequency although they may be different in phase. (the preferred-embodiment implementation will also be equal in phase and will therefore achieve better synchronization resolution).

o While this may not be valid for the long term due to drift, it is true for the oo short term (seconds). As a result, the time that any given datum spends in the elastic buffer can be considered as a constant during the interval o0 20 required for the synchronization process.

e o o ,006 The ICC uses the CLK as its clocking source for data being transmitted through the interconnect. Therefore, all information being transmitted on the interconnect is frame aligned to and synchronized with the CLK's timing chain.

Information being received on the interconnect is not frame aligned to nor is it synchror'.zed with the CLK's timing chain.

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-8- The synchronization process can be performed via the CPU/ICC in the master and target according to the procedure outlined below. In this discussion, actions taken by the master/target indicate a cooperative effort involving the CPUs on both ends of the interconnect. It is assumed that the ICCs are being directed by their respective CPUs. The term "master" will be used to indicate the node that is controlling the synchronization process, and the term "target" wtil be used to indicate the node that is being synchronized.

The procedure will now be detailed: Step 1. The master sends a message to the target requesting that it enter a mode whereby it will loop back a designated time slot of a o.o,,e designated interconnect.

Step 2. The target puts the designated time slot into the loop o 099 back mode.

Step 3. Coincident with the next major framing clock o (seconds), the master's ICC will transmit to the target's ICC the unique bit pattern. This bit pattern will be on the designated time slot of the designated interconnect. The master's ICC will start a hardware counter when the unique bit pattern is transmitted.

Step 4. The target's ICC will search the designated time slot of the designated interconnect for the unique bit pattern. When it finds the unique bit pattern, it will start its hardware counter. When the unique bit pattern is transmitted back to the master as a result of the target's ICC being in a loop back mode on the designated time slot, the counter will be stopped. The value of the counter represents the delay through the target. The target sends the value of the counter to the master.

CE02077R I -I I~I -9- Step 5. Upon the unique bit pattern being received at the master's ICC after being looped back from the target, the master's ICC will stop its hardware counter. The value of the counter represents the total round trip delay.

Step 6. Steps #1-5 may be repeated several times and histogrammed if necessary to ensure that the measured delays are repeatable. The master then calculates the half trip delay as being the value of the master's counter minus the value of the target's counter with o 0 the result being divided by two.

-O 10 Step 7. The master then sends a message to the target to o D request that it stay in the loop back mode on the designated time slot of "°°the designated interconnect, but now enabling the synchronization signal to its CLK, and that it load a specified value as calculated from step 6 above into the CLK's preset mechanism for its timing chain.

Step 8. The master's ICC will transmit the unique bit pattern o to the target, coincident with the next major framing clock. When this 6 unique bit pattern is received by the target, the value noted in item of o step 7 above is loaded into the target's CLK timing chain. When the unique bit pattern is received back at the master's ICC as a result of the 20 target's ICC having looped it back, the synchronization process is oe 0o complete. At this time, both the master's and the target's CLK timing chains will be synchronized to within less than 1 microsecond.

Referring now to Fig. 3 there is shown a first flow diagram for the invention. This flow diagram depicts a method for computing the time delay for the channel interconnecting the master node and the target CE02077R 7 ;r i 12 r Cc~

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node. In this flow diagram it is assumed that the master node ultimately computes the value of this time delay.

Beginning now with the master, the master node starts the process at step 301 and then proceeds to step 303. Here the master sends a unique bit pattern, or token, to the target. Coincident with this step 303, the master starts a clock or timer, step 305. It will be appreciated that the timer here referred to may be, for instance, any suitable hardware or software timing source available to the master node.

The token is thereupon transmitted to the target via the channel.

This transmitting or sending step is represented by the broken line 321.

The master then proceeds to step 307, where it waits to receive the token back from the target.

Referring now to the target node, the target node initially waits to receive the token from the master. This is represented by determining step 331, where the target waits until it determines that it has received the token. Once it receives the token, the target starts a clock or timer, step 333. It will be appreciated that the timer here referred to may be, for instance, any suitable hardware or software timing source available to the target node.

The target next goes to step 335, where it waits for the next available time slot of the interconnecting T1 facility to return the token to the master. When the desired time slot becomes available, the token is sent. This step of returning the token to the master is represented by the broken line 323.

After returning the token to the master, the target next goes to step 337, where it determines the time period that it held the token. Stated CE02077R I i -11- I *p a otherwise, this "holding time" is the time interval beginning with the target receiving the token and ending with the target sending the token. This holding time, of course, may be obtained directly from the target timing source that was previously triggered in step 333.

After providing the holding time, the target goes to step 339, where it sends the holding time information to the master. The target may accomplish this task, for example, by encoding the holding time as one or more binary words and sending them to the master via the T1 channel.

This step of sending the holding time to the master is represented by the broken line 325.

Referring again to the master, the master's next task is to wait until it receives the token from the target. This is depicted by determining step 307, where the master determines whether it has received the token.

After receiving the token, the master goes to step 309, where it 15 determines the time period elapsed since sending the token to the target.

Stated otherwise, this "elapsed time" is the time interval beginning with the master sending the token and ending with the master receiving the token. This elapsed time, of course, may be obtained directly from the master timing source that was previously triggered in step 305.

The master next waits to receive the holding time information from the target. This is depicted by determining step 311, where the master determines whether it has received the holding time. After receiving the holding time, the master proceeds to step 313, where it computes the time delay based on the difference between the elapsed time and the holding time.

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After computing the time delay, the process next returns (step 315) to the beginning step 301.

Referring now to Fig. 4 there is shown a second flow diagram for the invention. This flow diagram depicts an alternate method for computing the time delay for the channel interconnecting the master node and the target node. In this flow diagram it is assumed that the target node ultimately computes the value of this time delay.

Beginning now with the master node, the master node starts the process at step 401 and then proceeds to step 403. Here the master 10 sends the token to the target and starts a clock or timer, step 405.

The token is then sent to the target, represented by the broken line 421. The master then proceeds to step 407, where it waits to receive the token back from the target.

Referring now to the target node, the target node initially waits to receive the token from the master, step 431. Once it receives the token, the target starts a clock or timer, step 433.

The target next goes to step 435, where it waits for the next available time slot of the interconnecting T1 facility to return the token to the master. When the desired time slot becomes available, the token is sent, represented by the broken line 423.

After returning the token to the master, the target next determines the holding time, step 437. This holding time, of course, may be obtained directly from the target timing source that was previously triggered in step 433. After providing the holding time, the target next goes to step 461, where it waits to receive the elapsed time information from the master.

-12- CE02077R t' -e I I

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-13- Referring again to the master, the master's next task is to wait until it receives the token from the target. This is depicted by determining step 407, where the master determines whether it has received the token.

After receiving the token, the master goes to step 409, where it determines the elapsed time. This elapsed time, of course, may be obtained directly from the master timing source that was previously triggered in step 405.

After providing the elapsed time (step 409), the target goes to step 451, where it sends the elapsed time information to the target. The 1 10 master may accomplish this task, for example, by encoding the elapsed time as one or more binary words and sending them to the master via the 0 T1 channel. This step of sending the elapsed time to the target is represented by the broken line 453.

Referring again to the target, the taiget next waits to receive the elapsed time information from the master. This is depicted by determining step 461, where the target determines whether it has received the elapsed time. After receiving the elapsed time, the target proceeds to step 463, where it computes the time delay based on the difference between the elapsed time and the holding time.

After computing the time delay, the process next returns (step 465) to the beginning step 401.

Referring now to Fig. 5 there is shown a third flow diagram for the invention. This flow diagram depicts a method for the target node to synchronize itself with the master node, based on the value (At) of the time delay of the interconnecting channel. In this flow diagram it is assumed that the master node computes the value of this time delay.

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S l -14- Beginning now with the master node, the process starts at step 501 and then proceeds to step 503. Here the master node provides the value of the time delay, At. The master node may provide this time delay, for example, by the method of Fig. 3.

After providing the time delay the master node goes to step 505, where it sends the time delay information to the target. The master node may accomplish this task, for example, by encoding the value of the time delay as one or more binary words and sending them to the target via the T1 channel. This step of the master node sending the time delay value (At) to the target node is represented by the broken line 521.

After sending the time delay value to the target, the master node a, goes to step 507, where it sends a message to the target node informing the target node of a future point in time (To) at which time the master e node will send a synchronizing signal to the target. The master node may transmit this message by any convenient method such as, for example, by encoding the message as one or more binary words and o sending them to the target via the T1 channel. This step of the master j .node sending the message indicating the time (To) that the master node will send the synchronizing signal to the target node is represented by 11 C t the broken line 523.

The master node next proceeds to step 509, where it waits until t To. At precisely t To, the master node proceeds to step 511, where it sends the synchronizing signal to the target node. The synchronizing signal may, of course, be a unique bit pattern similar to the token used to measure the time delay. This step of the master node sending the -14- CE02077R o a Doo o v

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0 9 0 a oo a 9 9a0 0a F: synchronizing token at precisely t To is represented by the broken line 525.

Referring now to the target node, the target node initially waits to receive the time delay information from the master, step 531. After receiving this information, the target node goes to step 533, where it receives the message indicating that the master will send a synchronizing signal to the target at precisely t =To. The target node then goes to step 535, where it receives the synchronizing signal.

As a result of the channel's time delay, At, however, the target receives this synchronizing signal not at t =To, but at a later time t =To At. The target node then goes to step 537, where it synchronizes or adjusts its own clock based on t To At.

The synchronization process being complete, the process returns (step 539) to the beginning step 501.

15 Referring now to Fig. 6 there is shown a fourti flow diagram for the invention. This flow diagram depicts a method for the target node to synchronize itself with the master node, based on the value of the time delay (At) of the interconnecting channel. In this flow diagram it is assumed that the target node computes the value of this time delay.

20 Beginning now with the target node, the process starts at step 601 and then proceeds to step 603. Here the target node computes and provides the value of the time delay, At. The target node may provide this time delay value, for example, by the method of Fig. 4.

Referring now to the master node, at the appropriate time (step 607) the master node sends a message to the target node informing the target node of a future point in time (To) at which time the master node CE02077R -16will send a synchronizing signal to the target node. The master node may transmit this message by any convenient method such as, for example, by encoding the message as one or more binary words and sending them to the target node via the T1 channel. This step of the master node sending the message indicating the time (To) that master node will send the synchronizing signal is represented by the broken line 623.

The master node next proceeds to step 609, where it waits until t To. At precisely t To, the master node proceeds to step 611, where it 10 sends the synchronizing signal to the target node. The synchronizing signal, of course, may be a unique bit pattern similar to the token used to measure the time delay. This step of the master node sending the synchronizing toke:; at precisely t To is represented by the broken line 625.

Referring again to the target node, at the appropriate time (step 633) the target node receives the message indicating that the master node will send a synchronizing signal to the target node at precisely t =To. The target node then goes to step 635, where it receives the synchronizing signal.

As a result of the channel's time delay, At, however, the target receives this synchronizing signal not at t =To but at a later time t =To At. The target node next goes to step 637, where it synchronizes or adjusts its own clock based on t To At.

The synchronization process being complete, the process returns (step 639) to the beginning step 601.

-16- CE02077R 4000 0 0 0$ 00040 0000 0 40 00 0 0 .000.0 0 0 00 00 0 0,0 000000 4 0 0000 0 00 *0 0 4* 0 04 S t; 5, 4 44 t V ~4 -17- While various embodiments of an improved synchronization technique, according to the present invention, have been described hereinabove, the scope of the invention is defined by the following claims.

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Claims

1. A method for measuring time delay of a channel coupled between a master node and a target node, comprising: at said master node: sending a first signal to said target node; at a time generally fixed with respect to step starting a first timer; at said target node: receiving said first signal; at a time generally fixed with respect to step starting a second timer; sending a second signal to said master node; a" a time generally fixed with respect to step providing a holding time based on said second timer; sending said holding time to said master node; :at said master node: receiving said second signal; at a time generally fixed with respect to step providing an elapsed time based on said first timer; providing said holding time; computing said time delay based on the difference between said elapsed time and said holding time.

2. The method of claim 1 wherein said target node step includes a step of sending a third signal to said master node based on said holding time, and said master node step includes a step of receiving said third signal from said target node.

3. A method for measuring time delay of a channel coupled between a master node and a target node, comprising: at said master node: sending a first signal to said target node; at a point in time generally fixed with 39 respect to step starting a first timer; A;1 MV11 ihJQ N fi A 'f -18- at said target node: receiving said first signal; at a point in time generally fixed with respect to step starting a second timer; sending a second signal to said master node; at a point in time generally fixed with respect to step providing a holding time based on said second timer; at said master node: receiving said second signal; at a point in time generally fixed with respect to step providing an elapsed time based on said first timer; S(i) sending said elapsed time to said target node; at said target node: providing said elapsed time; computing said time delay based on the difference between said elapsed time and said holding time.

4. The method of claim 3 wherein said master node step includes a Step of sending a third signal to said l c target node based on said elapsed time, and said target node step includes a step of receiving said third o signal from said master node.

5. A method for synchronizing a target node with a master node, said target node having a clock and coupled to said master node via a channel, said method comprising t /the steps of: j tllc at said master node: providing the time delay of. said channel; sending said time delay to said target node; sending said target node a message indicating that it will send a predetermined signal at a predetermined time; sending said predetermined signal; at said target node: receiving said time delay; receiving said message; 39 receiving said predetermined signal; 371 -19- S 454 adjusting said clock based on said predetermined time and said time delay.

6. A method for synchronizing a target node with a master node, said target node having a clock and coupled to said raster node via a channel, said method comprising the steps of: at said master node: sending said target node a messc-ge indicating that it will send a predetermined signal at a predetermined time; sending said predetermined sional; at said target node: providing the time delay of said channel; receiving said message; receiving said predetermined signal; Mf adjusting said clock based on said predetermined time and said time delay.

7. A method for synchronizing a target node with a master node, said target node having a clock and coupled to said master node via a channel, said. method comp-cisinr, the steps of: at said master node: sending a first signal to said target node; at a point in time generally fixed with respect to step starting a first timer; at said target node: receiving said first signal; at a point in time generally fixed with respect to step starting a second timer; sending a second signal, to said master node; Mf at a point in time generally fixed with respect to step providing a holding time based on said second timer; sending said holding time to said master node; at said master node: receiving said second signal; Mi at a point in time generally fixed with respect to step providing an elapsed time 39 based ouil said first timer; map- S 44 4 5 S 5 S 1- 1 receiving said holdinq time; computing a time delay for the channel based on the difference between said elapsed time and said holding time; sending said time delay to said target node; sending said target node a message indicating that it will send a predetermined signal at a predetermined time; sending said predetermined signal; at said target node: receiving said time delay; receiving said message; receiving said predetermined signal; adjusting said clock based on said predetermined time and said time delay.

8. A method for synchronizing. a target node with a master node, said target node having a clock and coupled to said master node via a channel, said method comprising the steps of: at said master node: sending a first signal to said target node; at a point in time generally fixed with respect to step starting a first timer; at said target node: receiving said first signal; at a point in time generally fixed with respect to step starting a second timer; sending a second signal to said master node; at a point in time generally fixed with respect to step providing a holding time based on said second timer; at said master node: receiving said second signal; at a point in time generally fixed with respect to step providing an elapseu time based on said first timer; sending said elapsed time to said target node; at said target node: receiving said elapsed time; S( J9 V 9 9 M9aVw -21- computing a time delay for the channel based on the difference between said elapsed time and said holding time; at said master node: sending said target node a message indicating that it will send a predetermined signal at a predetermined time; sending said predetermined signal; at said target node: receiving said message; receiviig said predeterulined signal; adjusting said clock based on said predetermined time and said time delay.

9. A method for measuring time delay of a channel coupled between a master node and a carget node substantially as herein described with reference to the accompanying drawings. A method for synchronizing a target node with a I, master node substantially as herein described with S 20 reference to the accompanying drawings. l DATED: 4 December, 1991. PHILLIPS ORMONDE FITZPATRICK Attorneys for: MOTOROLA INC. 3326u 39 ~-22-