JPH02285679A - Semiconductor device for power use - Google Patents

Abstract

PURPOSE:To make it possible to avoid an adverse effect due to a parasitic transistor and to obtain a highly reliable semiconductor element for power use by a method wherein an insulating film of a film thickness thikcer than that of a gate insulating film in each active region cell is formed between a main current part and an emulation current part. CONSTITUTION:A plurality of active region cells are formed by insulated-gate type transistor cells (MOS transistor cells) 12 to 14, at least one of the active region cells is used as a main current part (a) and at the same time, another one of the active region cells is used as an emulation current part (b), a common drain electrode 22, which comes into contact to the main and emulation current parts (a) and (b), is formed and at the same time, individual source electrodes (a main current part source electrode and an emulation current part source electrode) 23 and 24, which respectively come into contact to the main and emulation current parts (a) and (b), are formed. In such a semiconductor element for power use, an insulating film 26 of a film thickness thicker than that of a gate insulating film 20 in each active region cell is formed between the above main and emulation current parts. Thereby, a parasitic transistor is prevented from being turned-ON and the erroneous operation of the element and a reduction in an element current level detection accuracy can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power semiconductor device having a main current section and an emulation current section that follows the current of the main current section.

[Prior Art] In order to limit the current of a power semiconductor device, it is necessary to sense the current level of the device.As a method of detecting the current level of the device, for example, Japanese Patent Laid-Open No. 60-94
It is shown in Publication No. 772 and USP 4,553,084.

According to this method, the main current section and the emulation current section are closely coupled electrically and thermally, and because these current sections are formed in the same manufacturing process, the current level of the emulation current section is the same as that of the element. It is almost exactly proportional to the current level of the main current section.

[Problem to be solved by the invention] However, the semiconductor element having such a structure has the seventh problem.
As shown in the figure, there is an anomalous transistor between the main current section 1 and the emulation current section 2 (Fig. 7 shows parasitics 1 to transistor channel section 3), and the anomalous transistor is shown in Fig. 8. Electrical connections are made as shown (References related to this include IEEE, IEDM83.16
・Here are 6). Under conditions in which this anomalous transistor turns on, there are adverse effects such as occurrence of element malfunction and deterioration of element current detection accuracy.

An object of the present invention is to provide a highly reliable power semiconductor device that avoids the adverse effects of parasitic l-landilis.

[Means for Solving the Problems] The present invention forms a plurality of active area cells using insulated gate transistor cells, at least one of the active area cells is used as a main current section, and the active area Another one of the cells is used as an emulation current section, and a common drain is formed in contact with the main current section and the emulation current section, and separate sources are formed in contact with the main current section and the emulation current section, respectively. The gist of the semiconductor device is a power semiconductor device in which an insulating film thicker than the insulating film of the active region cell is formed between the main current section and the emulation current section.

[Function] Parasitic formation between the main current section and the emulation current section in an insulating film that is thicker than the gate insulating film of the active area cell! ~The threshold voltage of the lungis increases,
Turning on of a strange transistor is suppressed.

[Example] An example embodying the present invention will be described below with reference to the drawings.

FIG. 2 shows a simplified cross-sectional view of a power semiconductor device, in which a silicon substrate 9 is divided into an active region 10 and a termination region 11. As shown in FIG. FIG. 1 is an enlarged view of a part of the active region 10 in FIG. 2. As shown in FIG.

In FIG. 1, a silicon substrate 9 has a large number of vertical D-Ms.
O3l ~ transistor cell 12, 13. '14 is placed. This MOS transistor cell 12.13.14
A plurality of active area cells are formed, with at least one of the active area cells serving as a main current section and another one of the active area cells serving as an emulation current section. In this example, MO3l~Langili cell 12.14
A main current section is formed by the MOS transistor cell 13, and an emulation current section is formed by the MOS transistor cell 13.

The specific configuration will be explained in detail below. A lightly doped N conductivity type region 15 is formed on a heavily doped N conductivity type region 15.
A conductivity type region 16 is formed.

This region 16 is epitaxially grown on the N conductivity type region 15.

Further, a P conductivity type region 17 is provided in the N conductivity type region 16, and this region 17 has two different resistivity parts 17a,
17b. A heavily doped N conductivity type region 18 is disposed within the P conductivity type region 17 . The P conductivity type region 17 is formed to have, for example, a rectangular or circular boundary when viewed from above, and the N conductivity type region 18 is formed to have, for example, a rectangular or circular boundary in the P conductivity type region 17 when viewed from above. Formed as a loop.

Gate electrode 19 is formed of N-type conductive polysilicon,
The gate is common to each cell 12, 13, and 14. The goo 1 to the electrode 19 are separated from the upper surface of the silicon substrate 9 by an insulating film 20 such as a silicon dioxide layer. Further, the upper and side parts of the gate electrode 19 are covered with an insulating layer 21. Then, as shown in section A in FIG.
It is separated from the silicon substrate 9 by.

Note that the gate electrode 19 may be formed of a heat-resistant conductive material such as MO or W.

A drain electrode 22 is formed on the underside of the silicon substrate 9, and the drain electrode 22 is formed of a deposited metal such as Ti--Ni (7), and has a common drain electrode 22 for each cell 12°13.14. Configure.

The main current section source electrode 23 is in contact with the main current section MO81 to Langiris cell 12.14, and the emulation current section source electrode 24 is in contact with the MOS transistor cell 13 of the emulation current section. This main current section source electrode 23 is separated from the silicon substrate 9 by an insulating layer 21 and connected to an external connection terminal (not shown). Note that the source electrode 23 may be in direct contact with the field ring 25 (see FIG. 2), in which case the field ring 25 will be at the same voltage as the source electrode 23.

In this embodiment, an insulating film 26 made of an oxide film or the like is provided below one gate electrode at the boundary line between the main current section and the emulation current section to prevent an abnormal transistor. . The thickness of this insulating film 26 is MOS
The film thickness is thicker than the insulating film 20 under the gate electrode 19 of the transistor cells 12, 13, and 14. More specifically, even if a normally used voltage of 5V is applied between the drains 1 to 1, the strange lateral 1 with the channel portion 3 shown in FIG.
~3000A as the insulation film thickness that does not turn on the transistor
That's all.

The film thickness and material of this insulating film 26 are preferably the same as the field insulating film 27 (see FIG. 2) formed of an oxide film or the like.
When forming the field insulating film 27, a mask (
(not shown), and thereby the insulating film 26 and the field insulating film 27 can be formed at the same time.

The parasitic transistor includes a P conductivity type region 17, an N conductivity type region 16, and a goo 1 in the main current section and the emulation current section.
~Insulating film 20. This is an MO3 type transistor formed from a gate electrode 19. In FIG. 8, the parasitic transistor is turned on and off depending on the gate voltage relative to the drain voltage, and the main current section source and the emulation current section source are made conductive or disconnected. When a voltage difference occurs between the main current section source electrode 23 and the emulation current section source electrode 24 under conditions where this parasitic transistor is turned on, a current flows through the parasitic transistor, increasing the element current of the power element. Accurate detection becomes impossible.

Furthermore, when the strange transistor is Enhancement 1~ type, when the main transistor is on,
Since the parasitic transistor is off, the influence is limited, such as when the parasitic transistor turns on during an on-to-off transition or when leakage from the parasitic transistor increases at high temperatures.

However, if the parasitic transistor is a depletion type, the parasitic transistor is always turned on during normal operation, causing a bypass current to flow and affecting accuracy. In the N-channel D-MOS with N-type transistors 1 to 1 of this embodiment, when the substrate concentration (concentration of the N-conductivity type region 16) is 1016 atms/cc or less, the threshold voltage is 1V or less, considering the influence of interfacial charge. However, 1015a
Below tms/cc, it tends to become depression type. Therefore, the substrate concentration (concentration of N conductivity type region 16)
In a high voltage element using a low voltage of around 101015at/CC or less, the effect of raising the threshold voltage by the insulating film 26 is significant.

In this way, in this embodiment, the MOS transistor cell-2,
13 and 14 (insulated gate type transistor cells) to form a plurality of active area cells, at least one of the active area cells is used as a main current section, and another one of the active area cells is used as a main current section. is the emulation current section, forms a common drain that contacts the main current section and the emulation current section, and forms separate sources that contact the main current section and the emulation current section, respectively. MOS transistor cells 12, 13,
Insulating film 26 thicker than the insulating film 20 of No. 14 Goo 1
was formed. As a result, it is possible to increase the threshold voltages of the parasitic transistors 1 to 1 and create a structure in which the parasitic transistors are not turned on. Therefore, malfunction of the element and deterioration of element current level detection accuracy can be prevented, and reliability can be improved.

It should be noted that the present invention is not limited to the above-mentioned embodiments. For example, although the cells were formed using MOS transistors in the above-mentioned embodiments, the cells may be formed using IGBT-FGTOs. When using this IGBT and GTO, the drain in the embodiment means "anode" and the source means "one cathode".

Further, as shown in FIG. 3, a P conductivity type region 28 (a diffusion layer of a conductivity type opposite to that of the source) may be provided under the insulating film 26. In other words, in order to provide the insulating film 26 for preventing stray transistors, the distance between the main current section and the emulation current section becomes long, which tends to cause a decrease in the drain-source breakdown voltage of the main current section and the emulation current section. This can be prevented by the conductivity type region 28. In other words, P conductivity type region 2
8 connects the depletion layer when a high voltage is applied between the drain and source (electric field relaxation).

In this case, when viewed from above, the P conductivity type region 28 is
It is necessary to form it inside the edge. That is, the third
In the figure, the parasitic transistors are placed inside by a distance ρ so that the channels of the parasitic transistors are not connected. Further, the P conductivity type region 28 is the P conductivity type region 17 of the MOS transistor cells 12, 13.14 and the field ring (P region) 25.
are formed at the same time. That is, when forming the P conductivity type regions 17a and 25 on the silicon substrate 9, this can be easily achieved by changing the mask for forming the P conductivity type regions 17a and 25. and P conductivity type region 17a.

25 can be formed simultaneously.

That is, as shown in FIG. 4(a), P is applied to the silicon substrate 9.
After simultaneously forming the conductivity type regions 17a and 25.28, a thick insulating film 26.27 is formed (FIG. 4(b)).
A thin insulating film 20 is formed (FIG. 4(C)). and,
As shown in FIG. 4(d), after forming the Ps type region 17b, the goo 1 to 1 made of polysilicon is placed on the insulating film 20.
After forming the electrode 19, the N conductive shadow region 18 is formed and the insulating layer 21 is placed (FIG. 4(e)), and the source electrodes 23 and 24 are placed (FIG. 4(f)).

Therefore, the number of manufacturing steps is increased, and therefore, the power semiconductor device according to this embodiment is only slightly more expensive than the conventional device.

Furthermore, one of the problems with semiconductor devices is passivation cracks. This is because when a chip is packaged in a resin mold, cracks occur in the passive region due to the difference in linear expansion coefficient between the mold resin and the silicon chip. This passivation crank is more likely to occur at a location away from the center of the chip than at the center of the chip, and
As shown in Figure 5, when measuring the size of the location where a crack C occurs in the aluminum on the board, as shown in Figure 6, when the width of the aluminum wiring is 50 μm or more, the maximum length of the crack It has been confirmed that L max becomes very large and passivation cracks are likely to occur.

In this embodiment, the main current section source electrode 23 and the emulation current section source electrode 24 are made of a deposited metal such as aluminum. ,14
It is in contact with the cell, and is arranged so as to cover a wide area from the top surface of the cell. In addition, the main current section source electrode 23 has a large aluminum width and its edge is placed at the edge of the chip, so this edge is a part where passivation cracks are likely to occur, and the border with the emulation current section. The bottom part of the main current section source electrode 23 is a MOS
A transistor cell has an active layer (a region where a depletion layer extends), and if a passivation crack occurs in that part, it will lead to electrical leakage of the device or, in the worst case, destruction.

In this embodiment, as shown in FIG. 3, by arranging the edge of the main current part source electrode 23 above the thick insulating film 26, even if a passivation crack occurs in that part, the insulating film The cracks easily stop at 26 and do not easily reach the active layer of the silicon substrate 9. Furthermore, as shown in FIG. 2, since the edge of the main current section source electrode 23 is located above the thick field insulating film 27, even if a passivation crack occurs in that part, the insulating film 27 will not be damaged. The crack is easy to stop. Furthermore, the third
In the figure, the emulation current section source electrode 24 has a width of about 30 μm, and the edges of the source electrode 24 are cracked without forming passivation cracks.

Furthermore, as shown in FIG. 2, the edge of the main current section source electrode 23 is arranged on the field ring (P conductivity type region) 25. As a result, in the conventional example, USP4,53
As shown in Fiq, 1 of 2,534, when the edge of the wide aluminum electrode is on the N- region of the drain, when a crack occurs at this edge and reaches the silicon substrate, the crack will cause the drain If cracks occur in the N- layer (N conductivity type region) of the field ring, drain-source leakage occurs when a reverse bias is applied between the train and the source, but in this example, cracks occur in the field ring (P conductivity type region). 25, drain-source leakage can be suppressed.Similarly, as shown in FIG. Therefore, even if a crack occurs in this portion and reaches the silicon substrate 9, drain-source leakage can be suppressed.

[Effects of the Invention] As described in detail above, the present invention exhibits an excellent effect of avoiding the adverse effects of anomalous transistors and achieving high reliability.

[Brief explanation of drawings]

Figure 1 is an enlarged sectional view of the power semiconductor device of the example, Figure 2
The figure is a sectional view of a power semiconductor device, FIG. 3 is a sectional view of a separate power semiconductor device, FIGS. 4(a) to (f) are sectional views for explaining the manufacturing process, and FIG. 5 is a substrate Plan view, No. 6
The figure shows the relationship between aluminum wiring width and maximum crack length.
FIG. 7 is a sectional view of a power semiconductor element for explaining the prior art, and FIG. 8 is a circuit diagram for explaining an anomalous transistor. 12 is a MOS transistor cell, 13 is a MOS transistor cell, 14 is a MOS transistor cell, 19 is a gate electrode, 20 is a gate insulating film, 22 is a drain electrode, 2
3 is a main current section source electrode, 24 is an emulation current section source electrode, and 26 is an insulating film.

Claims (1)

[Claims] 1. A plurality of active area cells are formed using insulated gate transistor cells, at least one of the active area cells is used as a main current section, and another of the active area cells is used as a main current section. In a power semiconductor element, one of which is an emulation current section, a common drain is formed in contact with the main current section and the emulation current section, and individual sources are formed in contact with the main current section and the emulation current section, respectively, A power semiconductor device characterized in that an insulating film thicker than the gate insulating film of the active region cell is formed between the main current section and the emulation current section.