JPH02285428A - Control storage recovery processing system - Google Patents

Abstract

PURPOSE:To increase the recovery rate of error data by a microprogram by setting the microprogram again in a control storage part when a request flag is set in a reloading request trigger means. CONSTITUTION:When a trouble mode which can not be recovered by an error data recovery mechanism 11 is judged, a specific trouble mode detecting means 12 sets a request trigger indicating a request to reload the microprogram in the reloading request trigger means 13. Here, a recovery mechanism suppressing means 15 performs processing so that even if there is a request to actuate the error data recovery mechanism 11, the error data recovery mechanism 11 is not actuated, so the multiple error occurrence of a control storage part 10 due to the correction processing of the error data can be prevented from being advanced. When this request trigger is set, on the other hand, a request trigger monitoring means 22 instructs a loader 21 to reload the microprogram and then the normal microprogram is set again in the control storage part 10. Consequently, the reliability of the microprogram can be improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a control memory recovery processing method for recovering error data of a microprogram developed in a control memory unit of a general-purpose instruction processing unit, and aims to improve the recovery rate of error data. , a control storage unit that stores a microprogram initialized by a service processor; and, when there is an error in the data stored in the control storage unit, correct the data to normal data according to a preset check code and check word. In a general-purpose instruction processing device equipped with an error data recovery mechanism, a specific failure mode detection means detects the occurrence of a failure mode that cannot be recovered by the error data recovery mechanism; reload request trigger means for setting a program reload request flag; recovery mechanism suppressing means for suppressing operation processing of an error data recovery mechanism when the reload request flag is set; is configured to reset the microprogram in the control storage unit when the request flag is set in the reload request trigger means.

[Industrial application field]

The present invention relates to a control full memory recovery processing method for recovering error data of a microprogram developed in a control memory unit of a general-purpose instruction processing device, and in particular, to a control memory recovery processing method that can increase the recovery rate of error data. It is related to the method.

The arithmetic control unit in the general-purpose instruction processing 'A' location reads out the microprogram developed in the control storage unit, controls the arithmetic unit, and executes instructions. This microprogram is loaded from the service processor, but the memory means for the control storage section is generally the RA.
Since M is used, there is a problem that the probability of error is higher than that of general logic. Therefore, it is necessary to take measures to improve the recovery of erroneous data of microprograms expanded into the control storage unit as much as possible.

[Conventional technology]

When reading and using the microprogram in the control storage section, parity checks and E
A check using a check code such as a CC check is executed to ensure the normality of read data. As is well known, ECC checks using Hamming codes are capable of detecting and correcting 1-bit errors in 1 word, as well as detecting 2-bit errors in 1 word. Furthermore, one check word is provided for each check block provided by dividing the control memory to be recovered into one or more blocks (when allocated to the control memory to be recovered, and when allocated outside the control memory to be recovered). ), calculate the exclusive OR for each bit of all words in the check block including the check word, and set the value of the check word so that the result is "O". It is also possible to correct two-bit errors in one word by employing a checksum method.

In other words, if the two-bit error is limited to a single word, using the checksum method, the exclusive OR can be calculated for each corresponding bit of all words in the check block, including the check word. For example, the bit position where the error resides will take the value "1". From now on, we will use EO in bit correspondence between this result and the error data.
By finding R, error correction can be realized.

For fixed faults in control memory (stuck-at faults such as "0'stuck-at" and "1° stuck-at" that cannot be recovered by rewriting),
one or more alternate data storage mechanisms (e.g. registers)
At the same time, the address of this alternate data storage mechanism and an alternate address valid pinpoint indicating whether or not this alternate data storage mechanism is in use are provided, and recovered data is obtained through ECC correction processing and checksum correction processing. In some cases, a method is adopted in which the recovered data is stored in a replacement data storage mechanism. Note that when a plurality of alternate data storage mechanisms are provided, a plurality of addresses of the alternate data storage mechanisms, alternate address effective focus, etc. are also provided in corresponding formats.

In addition, the control memory recovery process is not limited to the instruction processing time, but an operation configured to read the microprogram from the control memory unit according to a predetermined constant cycle and execute the above-mentioned recovery process when there is erroneous data. By employing a diagnostic recovery processing mechanism, the normality of data read from control memory is guaranteed to be improved.

[Problem to be solved by the invention]

However, in the conventional technology that uses such a combination of ECC correction processing and checksum correction processing, ECC
When checksum processing is performed by detecting 2-bit error data that cannot be recovered by correction processing, if there is another error data in the checksum block,
This means that erroneous data cannot be recovered. This problem similarly occurs even when a replacement data storage mechanism is provided to cope with fixed failures.

FIG. 4 shows a failure mode that can be recovered using the conventional technique, and FIG. 5 shows a failure mode that cannot be recovered using the conventional technique. Here, FIG. 4(a) shows an example in which a 1-bit error in the accessed word can be recovered to a normal one by ECC correction processing, and FIG. 4(b) shows an example in which a 2-bit error exists in the accessed word. Figure 4(C) shows an example in which the checksum can be restored to normal by the checksum correction process when there is no error in other words of the checksum block. An example is shown in which when the faulty word is a fixed fault, it can be handled by using an alternate data storage mechanism. In addition, Figure 5(a) shows that if there is a 2-bit error in the accessed word and errors also exist in other words in the checksum block, recovery can be achieved even if the checksum correction process is used in combination. FIG. 5(b) shows an example in which the failure mode of FIG. 5(a) occurs when an alternate data storage mechanism is used.

As described above, with the conventional technology, it may not be possible to recover erroneous data of the microprogram in the control storage section.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a control B memory recovery processing method that can increase the recovery rate of error data of a microprogram developed in a control memory unit of a general-purpose instruction processing device. That is.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, 1 is a general-purpose instruction processing device equipped with the present invention, 2 is a service processor prepared for the general-purpose instruction processing device 1, and IO is a control storage unit;
11 is an error data recovery mechanism that detects errors in the data stored in the control n storage unit IO and corrects errors according to preset check codes and check words. Something that restores certain stored data to regular data, 1
2 is a specific failure mode detection means provided in the error data recovery mechanism 11, which detects the occurrence of a failure mode that cannot be recovered by the error data recovery mechanism 11; 13 is a reload request trigger means, which is a specific failure mode detection means; 12 sets a request flag for reloading the microprogram when the occurrence of an unrecoverable failure mode is detected; 14 is a recovery processing control mechanism that is executed at the time of microinstruction execution or according to a predetermined cycle; 15 is a recovery mechanism suppressing means provided in the recovery processing control mechanism 14, which is activated during the inspection cycle to control the recovery process of the error data recovery mechanism 11, and a request flag is set in the reload request triggering means 13. 16 is an arithmetic unit which is controlled by a microprogram read from the control storage unit 10; 20 is a microdisk; 21 is a loader which loads the microprogram held in the micro disk 20 into the control storage 10; 22 is a request trigger monitoring means; It is activated when receiving a failure occurrence sent from the general-purpose instruction processing device 1 or at a monitoring cycle according to a predetermined cycle, and monitors whether or not a request flag is set in the reload request trigger means 13. It is.

[Effect]

In the present invention, when determining that the failure mode is a failure mode that cannot be recovered by the error data recovery mechanism 11, the specific failure mode detection means 12 sets a request trigger in the reload request trigger means 13 indicating a request to reload the microprogram. When this request trigger is set, the recovery mechanism suppressing means 15 performs processing such that the error data recovery mechanism 11 is not activated even if there is a request to activate the error data recovery mechanism 11. This suppression processing makes it possible to prevent the progression of multiple errors in the control storage unit 10 due to the correction processing of error data again. On the other hand, when this request trigger is set, the request trigger monitoring means 22 instructs the loader 21 to reload the microprogram. This instruction processing causes the regular microprogram to access the control memory IO.
It will be reset to .

As described above, in the present invention, when error data in a microprogram that cannot be recovered by the error data recovery mechanism 11 is found, the control storage unit 10 is reloaded with a normal microprogram. This makes it possible to improve the reliability of the microprogram used by the processing device 1.

〔Example〕

Hereinafter, the present invention will be explained in detail according to examples.

FIG. 2 shows the configuration of an embodiment of the present invention for correcting error data of a microprogram stored in the control storage section 10 described in FIG. 1.

In the figure, 30 is an address latch circuit that holds address data for accessing the control storage unit 10, 31 is a multiplexer that selects address data to be input to the address launch circuit 30,
32 is an error data address latch circuit which holds the address data of error data; 33 is a replacement data register (there may be more than one) which is used as a replacement memory in the event of a fixed failure; 34 35 is an alternate address latch circuit (there may be more than one) that holds the address of the alternate data register 33, and 35 is an alternate address valid bit (there may be more than one) that is used by the alternate data register 33. 36 is a comparator (there may be more than one comparator), which indicates whether or not the address data of the address launch circuit 30 and the address data of the alternate address latch circuit 34 match. A multiplexer 37 determines whether or not the replacement address valid bit 35 indicates that it is in use, and a microinstruction that reads from the control storage unit IO or a microinstruction that reads from the replacement data register 33. It outputs either one of the following. This alternate data register 33 and alternate address latch circuit 34
A fixed failure recovery mechanism is configured by the alternate address valid bit 35 and the comparator 36, and the comparator 36 indicates that the alternate address valid pin 35 is in use.
Further, when the address data of the address launch circuit 30 and the address data of the alternate address latch circuit 34 match, the multiplexer 37 is controlled to use the alternate delta register 33. Note that the next address for accessing the control storage unit 10 included in the microinstruction output from the multiplexer 37 is determined by the multiplexer 31.
By being input to the address latch circuit 30, the address is inputted to the control storage unit 10 manually.

3rd is the ECC check circuit, multiplexer 3
A reload detection circuit 39 is composed of two launch circuits and one AND circuit, and performs an ECC check on the microinstruction outputted from the microinstruction circuit 7. 40 is a reload request trigger circuit which is detected by the reload detection circuit 39. 41 is a syndrome which holds which bit position has an error when 1-bit error data is detected by the ECC check circuit 38; 42 is a decoder; If there is an error, set “1” to the bit with error, and set °0 to the remaining bits.
43 is a first EOR circuit that performs a correction process for 1-bit error data by calculating the exclusive OR between the output of the decoder 42 and error data; 44 45 is a second EOR circuit that performs exclusive OR processing for checksum correction processing; 45 is a check word register that stores a check word for checksum correction processing; AN
The D circuit is for manually inputting "O" to the second EOR circuit 44, and 47 is a write register for holding micro-instructions to be written into the control storage unit 10 and for storing erroneous micro-instructions. A multiplexer 48 holds error data, and a write register 4
7 selects data to be manually input, and 49 is a recovery process control circuit that controls the entire recovery process.

Next, the operation processing of the present invention configured as described above will be explained.

As microinstructions are read out from the control storage section 10 according to the address data of the address launch circuit 30, the control of the arithmetic unit 16 explained in FIG. 1 is executed. At this time, the second EOR circuit 44
According to the input "O" output from the AND circuit 46, the read data is processed so as to flow directly into the write register 47. During execution of this process, if the ECC check circuit 38 detects that the data is erroneous, the recovery process control circuit 49 interrupts the process of successively reading data from the control storage unit 10 and starts recovery process for the erroneous data. Process as follows. At this time, due to this interruption process, the write register 47 latches the error data, and the error data address latch circuit 32 latches the address data of the error data.

When the error data is 1-bit error data, the multiplexer 48 selects the first EOR circuit 43 according to the recovery processing control circuit 49, and the error data recovery process is executed by selecting the first EOR circuit 43 according to the recovery process control circuit 49. This is executed by inverting the erroneous bits in the data by exclusive ORing with the output of the decoder 42. Then, this corrected data is written to the address position of the error data address launch circuit 32 according to the recovery process control circuit 49, thereby realizing the recovery process. When the data is a 2-bit error, the multiplexer 4 first selects the check word register 45 according to the recovery processing control circuit 49, so that the check sum check word is latched into the write register 47.

Subsequently, according to the recovery processing control circuit 49, the control storage unit lO
The data of the checksum block including the error data is sequentially read from the block, and the second EOR circuit 844 calculates the exclusive OR for each corresponding bit of all words in the block including the check word. It will be executed. Here, during this process, AN
When “l” is input to the D circuit 46, the updated exclusive OR operation result is sent to the second EOR circuit 4.
4 will be configured to be input.

The correction data to be obtained as a result of the final exclusive OR operation is then collected by the recovery processing control circuit 4.
9, the error data is written to the address position of the address latch circuit 32, thereby realizing the recovery process.

On the other hand, when another error data is detected in the checksum block during execution of the checksum correction process, a flag is set in the reload request trigger circuit 40 according to the process of the reload detection circuit 39. This flag indicates that the failure mode cannot be recovered even by checksum correction processing. Although not shown in the embodiment, a waiting mechanism is provided so that when the ECC check circuit 38 detects erroneous data, a recovery processing state is secured. Then, the general-purpose instruction processing device 1 issues a message to the service processor 2, similar to other failures.
The process will be processed to notify the user of the occurrence of a failure. .

Even if there is a request to correct the error data subsequent to the recovery process, the recovery process control circuit 49 detects that the flag is set in the reload request trigger circuit 40, and then corrects the error data. Proceed to prevent execution of correction processing. This suppression processing makes it possible to prevent the progression of multiple errors in the control storage unit 1O due to the correction processing of error data again.

The service processor 2 is a general-purpose instruction processing device 1.
When a failure notification is received from the reload request trigger circuit 4, the scanout mechanism is used to process the error log and the reload request trigger circuit 4
Check whether the flag is set to 0. With this check process, the reload request trigger circuit 4
When detecting that the flag is set to 0, the service processor 2 resets the same microprogram as the initialized microprogram in the control storage unit 10. This resetting process is performed by manually inputting the microprogram corresponding to the write register 47 via the multiplexer 4B while sequentially inputting address data to the address latch circuit 30 via the multiplexer 31, as in the initial setting. It will be executed.

As described above, in the present invention, when the error data of the microprogram in the control storage unit IO cannot be recovered, the service processor 2 sets the microprogram again to recover the error data. .

In the above explanation, the error data recovery process that is executed during the control process of the arithmetic unit 16 has been explained. The same process is applied when checking whether there is a file or not and performing recovery processing. That is, when the general-purpose instruction processing device 1 detects that there is unrecoverable error data in a predetermined test cycle, it sets a flag in the reload request trigger circuit 40 and ends the process. Then, when the service processor 2 detects that the flag is set in the reload request trigger circuit 40 by periodically monitoring the presence or absence of the flag in the reload request trigger circuit 40, the service processor 2 stops the general-purpose instruction processing device 1 and The error data recovery process is realized by resetting the microprogram in the control storage unit 10, and the general-purpose instruction processing device 1 is restarted.

FIG. 3 shows a schematic flowchart executed by the recovery processing control circuit 49.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to significantly increase the recovery rate of error data of a microprogram developed in the control storage section of a general-purpose instruction processing device compared to the conventional method.

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a flowchart executed by the present invention, FIG. 4 is an explanatory diagram of failure modes that can be recovered by conventional technology, FIG. 5 is an explanatory diagram of a failure mode that cannot be recovered using the conventional technology.

In the figure, 1 is a general-purpose instruction processing unit, 2 is a service processor, 10 is a control storage unit, 11 is an error recovery mechanism, 12
13 is a specific failure mode detection means, 13 is a reload request trigger means, 14 is a recovery processing control mechanism, 15 is a recovery mechanism suppressing means, 16 is an arithmetic unit, 20 is a micro disk, 21 is a loader, and 22 is a request trigger monitoring means. .

Claims (1)

[Claims] A control storage unit (10) that stores a microprogram initialized by a service processor (2);
A general-purpose instruction comprising an error data recovery mechanism (11) that recovers the stored data to normal data according to a preset check code and check word when there is an error in the data stored in the storage unit (10). Processing device (1)
, a specific failure mode detection means (1) detects the occurrence of a failure mode that cannot be recovered by the error data recovery mechanism (11).
2); reload request trigger means (13) for setting a microprogram reload request flag when the occurrence of an unrecoverable failure mode is detected by the specific failure mode detection means (12); When the request flag is set in the reload request trigger means (13), the error data recovery mechanism (11)
), the service processor (2) is equipped with a recovery mechanism suppressing means (15) for suppressing the operation processing of the control storage unit (10) when a request flag is set in the reload request triggering means (13). ) is a control memory recovery processing method characterized by processing to reload a microprogram.