JPH02284224A - Digital comparator - Google Patents

Abstract

PURPOSE:To detect the coincidence of digital data by using abbreviated element configuration at high speed by constituting a multi-input logical gate of the bipolar transisor (TR) of multi-emitter configuration. CONSTITUTION:The multi-input logical gate G2 is constituted of the bipolar TR Q1 of the multi-emitter configuration. As for the TR Q1, by pulling up each emitter to a supply potential Vcc side respectively by n-channel MOS TRs Mn21 to Mn 28, and simultaneously, by pulling up their common base to the supply potential Vcc side through a resistor R1, the total logical sum of logic by each emitter is outputted from a collector side. Thus, the number of elements and the number of gate stages at the part of the multi-input logical gate is abbreviated, and the coincidence of the digital data of multi-bit length can be detected at high speed by using the abbreviated element configuration which is easy to form even in a semiconductor chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital comparator, and furthermore, to a technology that is effective when applied to detecting coincidence of digital data with a large number of bits. The present invention relates to a technology that is effective for use in semiconductor RAMs that have built-in functions such as functions and error detection.

[Prior Art] For example, in a semiconductor RAM having a built-in function such as a cache function or an error detection function, a digital comparator is formed to detect whether or not multi-bit length digital data matches in order to configure the above functions. (For example, Nikkei BP
Published by Nikkei Electronics November 16, 1987
(See Date nc, 436J, page 103).

This digital comparator, as shown in Figure 2,
Multi-bit length digital data (A.

~A7) and (Do~D7), a large number of exclusive logic gates 011~G18 that detect the presence or absence of data coincidence for each bit, and all bits (Xo~X7) are used.
) A multi-input logic gate G that detects the presence or absence of data matching at
2. With such a configuration, a detection output out indicating whether or not the respective bit patterns of the two digital data (Ao=A7) and (Do-D7) match each other is obtained. This match detection operation performs a hit determination as to whether the data at the accessed address is in the cache memory or error determination such as a parity check.

[Problem to be solved by the invention] However, the above-mentioned technology has the following disadvantages.

That is, the digital comparator described above is replaced with a semiconductor R.
If an AM is constructed using only MOS transistors, a large number of p-channel MO8) transistors Mpx and N-channel MOS transistors Mnx are required just for the multi-input logic gate G2, as shown in FIG. Become. For this reason, it has been quite difficult to integrate the digital comparator into a semiconductor chip where the layout area is severely restricted.

Further, although the multi-input logic gate G2 shown in FIG. 3 is constructed of only one stage, such a construction is not practical in practice. In the multi-input logic gate G2 shown in Fig. 3, as many as nine MOS transistors are connected in series between the power supplies vcc and Vee. Then, each MOS
) - There is a possibility that the operating voltage divided between the drain and source of the transistor becomes low and normal operation cannot be performed.

Therefore, in reality, as shown in Figure 4, two logic gates are used.
The multi-input logic gate G2 of the digital comparator is assembled by cascading more than one stage. Therefore, the number of elements of the digital comparator increases further, and the number of logic gate stages for coincidence detection also increases, causing problems in that the operation of coincidence detection becomes slow.

An object of the present invention is to develop a technology that enables high-speed matching detection of multi-bit length digital data using a simplified element configuration that is easy to form even in a semiconductor chip with severe layout area constraints. It is about providing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, among exclusive logic gates and multi-input logic gates used to detect coincidence of digital data with multiple bit lengths, the exclusive logic gate is constructed with MOS transistors, and the multi-input logic gate is constructed with a multi-emitter structure. It is composed of bipolar transistors.

[Effects] According to the above-mentioned means, the number of elements and gate stages in the multi-input logic gate that detects the presence or absence of data matching in all bits can be greatly reduced, so it can be used in semiconductors with severe layout area constraints. With a simplified element configuration that is easy to form within a chip, the purpose of detecting coincidence of multi-bit length digital data at high speed is achieved.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a digital comparator to which the technology of the present invention is applied.

The digital comparator shown in the figure is integrated to detect errors in a semiconductor RAM.
In order to detect a match between o = A7) and (Do~D7), a large number of exclusive logic gates Gll~018 that detect the presence or absence of a data match for each bit, and all bits (X
o to X7).

Here, the above-mentioned large number of exclusive logic gates Gll-018 are respectively p-channel MOS transistors MpH, M
p12 and n-channel MOS transistor Mn 11
．． Mn 12. It is composed of Mn13 to Mn16. MpH and Mn11 and Mp12 and Mn12 each form a CMOS inverter. An exclusive OR gate is formed by this CMOS inverter and Mn13 to Mn16.

The multi-input logic gate G2 is constituted by a bipolar transistor Q1 having a multi-emitter structure. This bipolar transistor Q1 having a multi-emitter structure has each emitter connected to a power supply potential V c by an n-channel MO8)-transistor M n 21 to M n 28.
By pulling up to the c side and pulling up the common base to the power supply potential Vce side via the resistor R1, the total OR of the logic by each emitter can be output from the collector side. In other words, it operates as a multi-input OR gate. Therefore, each emitter of Ql is connected to the output of the exclusive logic gate Gll~018 (X o =
By connecting to
A coincidence detection output Out is obtained by x6 x x7). In this case, a high level of the output out indicates a match, but if no match is detected in any one bit, that is, the outputs of the exclusive logic gates 011 to 018 (X o =
X 7) 17) If any one of them becomes a low level, the above output out cannot become a high level.
In this way, a multi-input logic gate having one logic stage is actually and qualitatively formed using one element.

The coincidence detection output obtained from the common collector of bipolar transistor Q1 is converted into a logic signal of a predetermined level by inverter IVI and output.

Inverter 1. Vl is constituted by a bipolar transistor Q2 that operates as a switch and a p-channel MOS transistor Mp31 that operates as a load, and converts the coincidence detection output out to a predetermined level and outputs it.

As described above, the exclusive logic gate 011 used for detecting coincidence of multi-bit digital data
.
11 to 018 are composed of MOS transistors, and the multi-input logic gate G2 is a circuit with a composite element structure composed of bipolar transistors with a multi-emitter structure, so that the number of elements and the number of gate stages in the multi-input logic gate G2 can be reduced. It can be greatly simplified.

This allows for a simplified element configuration that is easy to form even within a semiconductor chip with severe layout area constraints.
Match detection of multi-bit length digital data can be performed at high speed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the multi-emitter bipolar transistor Q1 may be one in which the collectors of two or more multi-emitter bipolar transistors are commonly connected.

The above explanation has mainly been about the application of the invention made by the present inventor to semiconductor RAM, which is the background field of application, but the invention is not limited thereto. It can also be applied to devices called microcomputers.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, it is possible to achieve the effect that coincidence detection of multi-bit length digital data can be performed at high speed with a simplified element configuration that is easy to form even in a semiconductor chip where layout area is severely restricted.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit of a digital comparator according to an embodiment of the present invention, FIG. 2 is a diagram showing a logical configuration of a digital comparator built in a semiconductor RAM, etc., and FIG. 3 is a diagram showing a circuit of a digital comparator according to an embodiment of the present invention. FIG. 4 is a diagram showing a conventional multi-input logic gate used to actually construct a digital comparator. Gll~G18... Exclusive logic gate, MpH, M
p12...p channel MOSF-transistor, M
ni~Mn16. Mn21-Mn28...N-channel MOS transistor, G2...Multi-input logic gate, Ql...Bipolar transistor with multi-emitter structure, Ao=A7°DO~D7...Digital.
Data, out... Match detection output. Figure Figure Figure

Claims (1)

[Claims] 1. In order to detect the coincidence of digital data of multiple bit lengths, a large number of exclusive logic gates are used to detect the presence or absence of data coincidence for each bit, and a large number of exclusive logic gates are used to detect the presence or absence of data coincidence in every bit. A digital comparator composed of a multi-input logic gate for detection, wherein each of the plurality of exclusive logic gates is composed of a MOS transistor, and the multi-input logic gate is composed of a bipolar transistor with a multi-emitter structure. A digital comparator featuring: 2. By pulling up each emitter of the bipolar transistor with a multi-emitter structure that constitutes a multi-input logic gate to the high level side, and also pulling up their common base to the high level side, the voltage from the common collector to each emitter is 2. The digital comparator according to claim 1, wherein the digital comparator is configured to obtain a total logical OR. 3. The digital comparator according to claim 1 or 2, wherein the exclusive logic gate and the multi-input logic gate are integrated on the same semiconductor chip.