JPH02279100A - Memory cartridge - Google Patents

Abstract

PURPOSE:To generate a pseudo stereo music easily by storing left/right channel data and selecting the right output or the left output according to the left/right channel data. CONSTITUTION:A sound length correlation data, an interval correlation data and left/right channel data are stored in advance in a 1st storage means so as to express a music with a music score table, for example. Then the sound length correlation data, correlation data and left/right channel data are read in a prescribed timing from the music score table according to the progress of the program in a 2nd storage means. The interval from a sound source signal generating means is decided according to the read interval correlation data and the duration time of the interval is set according to the sound length correlation data. The switching of the right output or the left output by switching means 681L-684L, 681R-684R is applied according to the left/right channel data. Thus, a series of music is generated as pseudo stereo sound.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory cartridge, and is particularly applicable to a video game machine, a portable liquid crystal game machine, etc., which has a pseudo-stereo sound generator that switches the sound source signal and outputs left and right outputs. The present invention relates to a memory cartridge that is removably installed in a video game machine.

[Prior art]

Conventionally, video game machines of this type have generated digitally stored audio signals as monaural sounds in order to generate sound effects, but there have been no devices that generate stereo sounds.

[Problem to be solved by the invention]

By applying the above-mentioned conventional technology, it is possible to digitally store left and right audio data in a memory and generate stereo sound using a voice synthesis method using computer technology. However, in this case, the memory capacity is almost twice as large as when generating monaural sound, and separate left and right voice synthesis circuits (sound sources) are required, making the circuit configuration complex and expensive. Become.

Note that there is Japanese Utility Model Application Publication No. 58-66800 that generates pseudo stereo sound, but this generates pseudo stereo sound from the received signal of an AM tuner, and it is effective for video game machines. It cannot be used to generate sound.

Therefore, the main object of the present invention is to provide a novel memory cartridge for use in a game machine equipped with a pseudo-stereo sound generating device that can generate pseudo-stereo sound with a simple circuit.

[Means to solve the problem]

The present invention provides a sound source signal generating means for generating a sound source signal according to data given from a memory cartridge, and an input terminal thereof connected to an output of the sound source signal generating means, and an output terminal of the sound source signal generating means connected to a first and a second sound signal output section. A memory cartridge that is detachably attached to a game machine main body and includes a switching means that is connected to the sound source signal generating means and selectively outputs the output of the sound source signal generating means to the first or second audio signal output section by a switching operation, a first storage means for pre-storing data correlated to note length, pitch and left and right so as to represent a series of music; and a first storage means for reading the data from the first storage means at a predetermined timing. The memory cartridge is provided with a second storage means for storing a program, and sets the tone length correlation data, pitch correlation data, and left and right data in the game machine main body according to the read data.

[Effect]

In a game machine, the sound source signal generated by the sound source signal generating means is selectively switched to the first
Alternatively, the signal is outputted to the second audio signal output section, thereby producing pseudo-stereo sound. 1st
In the storage means, note duration correlation data, pitch correlation data, and left/right data are stored in advance to represent a series of music, for example, in the form of a musical score table, and the musical score is stored in accordance with the progress of the program in the second storage means. The tone length correlation data, pitch correlation data, and left and right data are read from the table at a predetermined timing. The pitch from the sound source signal generating means is determined according to the read pitch correlation data, and the duration of the pitch is set according to the pitch correlation data. According to the left and right data, a switching operation of the right output or the left output in the above-mentioned switching means is performed.

In this way, a series of music is generated as pseudo-stereo sound.

〔Effect of the invention〕

According to this invention, left and right data are stored in the memory cartridge, and the right output or the left output is selected according to the left and right data, so that pseudo-stereo music can be easily generated.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

〔Example〕

FIG. 2 is a perspective view showing an example of a portable liquid crystal game device to which the present invention can be applied. This portable liquid crystal game device (hereinafter simply referred to as "game device") 10 includes a main body 12, and an LCD panel 14 on which display segments are arranged in dots according to a dot matrix method is provided on the upper surface of the main body 12.

An insertion opening (not shown) is provided at the upper part of the back surface of the main body 12, and a memory cartridge 16 is removably inserted into the insertion opening as shown by the two-dot chain line in FIG. The program R of this memory cartridge 16 is
As will be explained in detail later, the OM (not shown) stores game program data, as well as tone length data, pitch data, and left and right data for generating pseudo-stereo sound. Therefore, when the memory cartridge 16 is installed in the game device 10, the game program is executed, images for the game are displayed on the LCD panel 14, and music for the game is generated as pseudo-stereo sound. Ru.

A cross key switch 18 is provided on the top surface of the main body (2) to be operated when moving the game character displayed on the CD panel (14).

This cross key has four direction indicators, and by pressing any one of them, the game character can be moved up or down, or to the left or right.

Referring to FIG. 3, the above-mentioned memory cartridge 16 includes:
It is connected to a CPU 22 built in the case 12 through a 32-bin connector 20 . The CPU 22 includes a CPU core 24, and the CPU core 24 connects to each bus 2.
32 bin connector 2 by 6a, 26b and 26c
Connected to 0. Therefore, memory cartridge 16
When the CPU core 24 and the memory cartridge 16 are installed, the CPU core 24 and the memory cartridge 16 are connected.

The CPU core 24 also has a first
A key matrix such as the cross key switch 18 shown in the figure is connected. In connection with the CPU core 24, an internal RAM 2B and an internal ROM 30 are provided, and an internal RO
M30 is accessed by the CPU core 24 only when the first memory space is selected by the memory switching circuit 32.

The CPU core 24 outputs display data to the LCD controller 38 via the line buffer 36 under the control of the DMA controller 34 . The LCD controller 38 is then connected to a display RAM 42 via an LCD display RAM interface 40. Although not shown, the display RAM 42 includes a character RAM and a VRAM. Therefore, the LCD controller 38 converts the display data output from the CPU core 24 into an LCD drive signal from the display RAM 42. That is, display data from the CPU core 24 is stored in the character RAM and VR.
Specify the address of AM and write the characters RAM M and V
A character signal and an object (background) signal are output from the RAM, and the respective signals are combined by the LCD controller 38 to become an LCD drive signal.

This LCD drive signal is then given to an LCD common driver 46 and an LCD segment driver 48 via an LCD drive signal buffer 44. Therefore, the LCD common driver 46 and the LCD segment driver 48 display an image on the LCD panel 14 in accordance with the display data from the CPU core 24.

Note that a brightness volume 50 is provided, and this brightness volume 50 is connected to an LCD buffer amplifier 52, so that by operating the brightness volume 50, the L
The brightness on the CD panel 14 can be adjusted.

Further, the memory switching circuit 32 causes the address data from the CPU core 24 to be set to “0OFFH”, although the details are omitted.
” (however, the lowest “°H” indicates hexadecimal representation), select the first memory space indicated by the diagonal line upward to the right in Figure 4, and set the address data to “0”.
100H” or later, the address data is “”7FFF
The second memory space indicated by the downward diagonal line in FIG. The memory configuration is as shown by diagonal lines in Figure 4. In other words, the second
When the memory space of is selected, the address of the memory cartridge 16 “°0100H”~” 7 F F
The program stored up to "FH" becomes executable.

Note that character RAM, VRAM, and each of the below-mentioned 8-bit NR50 to NR52 and NR50 to NR5
Since the memory switching circuit 32 does not act on the various registers including 2 and the internal RAM, they can always be accessed by the CPU core 24.

An oscillation circuit 24a is connected to the aforementioned CPU core 24, and upon receiving the output of this oscillation circuit 24a, the sound circuit 5
41, 542, 543 and 544, respectively, create different types of sound source signals. Incidentally, as such sound circuits 541 to 544, for example, the circuit shown in FIG. 5 can be used.

In FIG. 5, a sound circuit 541 is connected to another sound circuit 54.
2 to 544, but in other sound circuits 542 to 544, the register number ""i"
Since the only difference is (NR50 to NR52), only the sound circuit 541 will be explained here and other explanations will be omitted.

After the basic clock f from the oscillation circuit 24 mentioned above is divided into 1/4 by the 1/4 frequency divider 74, the AND gate 76
is given to one input. The most significant bit D7 of register NR14 is used as the initial register 78,
When the initial register 78 is set to 1'', the R-S flip-flop 80 is set and the output of the 1/4 frequency divider 74 is applied to the frequency counter 82 via the AND gate 80.

Frequency counter 82 is configured as a programmable frequency divider, the frequency division ratio of which is set by frequency setting register 84. As a frequency setting register, register NR
A total of 11 bits, including all 13 bits Do-D7 and the lower 3 bits Do-D2 of NR14, are used. In this way, frequency data, that is, pitch correlation data is set in the frequency counter 82.

The duty ratio setting register 86, which is the upper two bits of register NRII, has a duty ratio of, for example, 12.5%, 2
Data to select 5%, 50% or 75% °00~1
1 is set. According to the duty ratio set in the duty ratio setting register 86, the duty circuit 88
changes the duty ratio of the output of the input frequency counter 82. As a result, the tone color of the pitch outputted from the frequency counter 82 is changed. The output of this duty circuit 88 is applied to one input of an AND gate 90.

Furthermore, the length clock (256H) from the oscillation circuit 24a is
z) is provided to a length counter 94 which is set by a length setting register 92. As the length setting register 92, the lower 6 bits DO to D5 of the register NRII are used. The length counter 94 outputs "1°" while counting the length clock by the value set in the length setting register 92, and the output is given to one input of the AND gate 60.As a result, D/A converter 9
6 receives the output of the duty circuit 88 for the time length set by the length counter 94. Therefore, the length setting register 92 and length counter 94 determine the length of one note or rest (16 minutes, 8 minutes, 4 minutes, 2 minutes, etc.).
), that is, the tone length is set.

The lower 3 bits DO to D2 of the register NR12 are used as the envelope step N register 98, and one step is set in 1/64 seconds, which is the minimum unit time when gradually decreasing or increasing the amplitude of the generated sound output. The number N of steps is set. The set number of steps N is determined by the envelope clock (6) from the oscillation circuit 24a.
4Hz) to the 1/N frequency divider 100. Therefore, the 1/N frequency divider 100 outputs "1" for counting the clock by the set number of steps N.

That is, the 1/N frequency divider 100 provides a count input to the envelope counter 102 at each timing when the amplitude is gradually decreased or increased.

The envelope counter 102 includes an envelope initial value register 104 which is the upper 5 bits of the register NR12.
sets the initial value of the envelope. Therefore, the envelope counter 102 has a 17N frequency divider 1
Each time a count input from 00 is given, it is incremented from the set initial value. The count result is given to the D/A converter 96. Note that the up/down register 106 (this is the fourth bit D3 of the register NR12) distinguishes whether the D/A converter 96 gradually increases or decreases.

The D/A converter 96 outputs the pulse train output from the duty circuit 88 as an analog sound output having an amplitude that depends on the count value of the envelope counter 102. This sound output becomes the output of this sound circuit 541.

Note that the decoder 108 uses the envelope initial value register 1.
04 data and the data of the up/down register 106, and when the initial envelope value is zero and the down direction is specified, the decode output is provided as the reset input of the RS flip-flop 80, and the D/
Provided as a disabling signal for the A converter 96. Therefore, in this state, the operation of this sound circuit 541 is stopped.

Similarly, sound outputs can be obtained from other sound circuits 542-544.

Each of the sound source signals output from the sound circuits 541 to 544 is processed by the sound control circuit 5 and output as two pseudo-stereo sound signals. Two audio signals output from the sound control circuit 5 are amplified by a sound amplifier 60 and then given to a speaker 62 or headphones 64. In addition, sound amplifier 6
0, a volume adjustment volume 66 is provided.

Referring to FIG. 1, sound control circuit 58 is illustrated in detail. The sound control circuit 5 includes a pair of analog switches 681L and 681R, 6B2L and 6B2R, 683L and 683R, 684L and 6, respectively, which receive the respective outputs or sound source signals of the sound circuits 541, 542, 543, and 544.
84R to each input terminal. The output terminals of the analog switches 681L, 6B2L, 683L and 684L are commonly connected to the input of the electronic volume 72L, and the other analog switch 681R.

The output terminals of 6B2R, 683R and 684R are commonly connected to the input of electronic volume 72R.

And electronic volume? The respective outputs of 2L and 72H, that is, audio signals, are amplified by two amplifiers 60L and 60R included in sound amplifier 60, respectively, and then output as first and second audio outputs S01 and SO2. In this example, the amplifier 60
The output from L is used as a left signal, and the signal from amplifier 60R is used as a right signal.

A register NR52 included in the CPU core 24 to control on or off of the sound circuits 541 to 544.
is used. This register NR52 is an 8-bit register, and when the most significant bit D7 is set to "1", all the sound circuits 541 to 544 are activated.
When "0" is set, everything is in a stopped state. and,
The lower four bits DO-D3 are used as sound circuit on flags, and when the sound circuits 541-544 are on, l'' is written in the corresponding bits.

Analog switches 681L to 684R are CPU core 2
It is controlled by register NR51 included in 4. This register NR51 is also an 8-bit register, and the lower 4
When bits DO, DI, D2 and D3 are set to 1°, analog switches 681L, 682L, 683
L and 684L are turned on, and the upper 4 bits D4. D5
．． When D6 and D7 are set to "1," analog switches 681R, 682R, 683R, and 684R are turned on, respectively.
When "0°" is set, the corresponding analog switch is turned off, and at this time, the sound source signals from the sound circuits 541 to 544 are not applied to the electronic volume 72L or 72R.

2 bits p3 and D7 of register NR50 provided in CPU core 24 are connected to analog switches 70L and 70.
Used to control R on or off. Analog switches 70L and 70R receive external sound source signal V.
This is to give IN to the electronic volume 72L or 72R. For example, if a sound source circuit is provided externally in addition to the sound circuits 541 to 544, the sound source signal is
input as analog switch '70L or 70
Turned on or off by R.

According to the lower 3 bits Do-02 of register NR50,
Controls the output level of the electronic volume 72L. That is, by setting these 3 bits to "000-111", the output level of the electronic volume 72L is controlled from the minimum to the maximum. Also, register N
“000-111” in another 3 bits D4-D6 of R50
By setting , the output level of the electronic volume 72H is controlled from the minimum to the maximum.

Address “0” of the memory cartridge 16 shown in FIG.
Analog switches 681L to 684R are set or written to appropriate bits of appropriate registers according to program data previously stored in 100H to 7FFFH and described later.
The above-mentioned control is performed.

In this embodiment, the sound circuit 541 is used as a melody sound source, and the sound circuits 542 to 544 are used as rhythm sound sources. Regarding the four bars shown in FIG. 6, the analog switches 681L and 681R are both turned on during this period so that the same melody is output on the left and right sides for these four bars. Therefore, the pins I-Do and D4 of the register NR51 are both “1°”.
' may be set.

Regarding the first rhythm sound source generated by the sound circuit 542, in the first measure, the audio output is s.

1 is output, and the audio output S02 is not output.

Therefore, in this first measure, as described later, bit D1 of register NR51 has "1°" and bit D5 has "0".
degrees are respectively set, the analog switch 682L is turned on, and the analog switch 682R is turned off. In the second measure, register NR51 (7) bits DI and D5 are both set to "l" and the two analog switches 68
2L and 682R are both turned on. Therefore, the audio output s.

l and 302 are both output. In the third measure, contrary to the first measure, bit D1 of register NR51 is set to “0”.
Since "°1" is written in the bit D5, the analog switch 682L is turned off and the analog switch 682R is turned on, so that the audio output SO1 is not output and the audio output SO2 is
is output. The same applies below.

Looking at the second rhythm sound source generated by the sound circuit 543, in the first bar, bit D2 of register NR51 is set to "1" and pitch I-D6 is set to 0°, so analog switch 683L is set. is turned on, the analog switch 683R is turned off, and therefore the audio output SQL is output, but the audio output SO2 is not output.In the second measure, on the contrary, the register NR51's pitch 1-
"0" is written to D2, and "1" is written to bit D6, the analog switch 683L is turned off, and the analog switch 683R is turned on. Therefore, the audio output SQL is not output, but the audio output 502 is output. The same applies below.

Regarding the third J rhythm sound source formed by the sound circuit 544, in the first bar, "t" is written to bit D3 of register NR51, "0'" is written to bit D7 of the memory cartridge, and analog switch 68 is written.
4L is turned on and analog switch 684R is turned off. Therefore, in the first bar, the audio output Sol is output and the audio output SO2 is not output.In the second bar, on the contrary, bit D3 of register NR51 is set to "0", bit D7 is set to "'l", Analog switch 684L
is turned off, and analog switch 684R is turned on.

Therefore, the audio output Sol is not output, and the audio output S
02 is output. The same applies below.

In this way, the melody sound from the sound circuit 541 and the rhythm sound from the sound circuits 542-544 are turned on or off as appropriate by the analog switches 681R-684R, and the four sound source signals are synthesized, and the electronic volume 72L and 72R. As a result, the output levels are individually controlled by the electronic volumes 72L and 72R, and separate left and right audio outputs Sol and SO2 in which the melody and rhythm are synthesized are output to the amplifier 60L.
and output from 60R.

Next, a program for controlling the generation of such music will be described. First, the program ROM (not shown) of the memory cartridge 16 contains the following frequencies (
A note (pitch) data table, a note (note length) data table, and a left/right data table are each stored in advance.

In the frequency data table, address FREQD+
O and FREQD+1 are set to "00°" and "00", respectively, and these two addresses represent a rest.Additionally, the addresses FREQD+2 and F
Data “01°” and “AB” are stored in REQD+3, which represents the pitch of the sound, that is, the pitch C. In the same way, pitch C# is set at addresses FREQD+4 and FREQD+5, and pitches D#, E, . . . are set at the following addresses.

Further, data "°06" is stored at address 0NPU+0 of the note data table, and thereby a note length corresponding to a sixteenth note (or rest) is set at address 0NPU10. In the same way, for subsequent addresses, write eighth notes.

The note lengths of quarter notes, half notes, whole notes, dotted quarter notes, dotted half notes, etc. (or their equivalent rests) are set.

Furthermore, the program ROM of the memory cartridge 16 stores in advance a musical score data table shown below.

This musical score data table is shown for the specific musical sound 2 (rhythm 1) shown in FIG.
From the description below, other sounds 1. It will be easily understood that similar musical score data tables are stored in advance for Sound 3 and Sound 4 as well. Note that in the musical score data table below, the note (rest) number indicates the consecutive number of notes or rests in each measure shown in Sound 2 of FIG. 6.

Music score data table address GAKUFU+0, GA
The three addresses KUFU+1 and GAKUFU+2 indicate note (or rest) number 11 of sound 2 in FIG. That is, address GAKUFU+
For O, this note or rest number 11 represents a quarter rest, so set the note data table address 0NPU+2, or "02", and set the address CAKUFU+1 to the frequency data table address FREQD+O, or "oo". Address GAKUFU+2 is set to data "01" of the left and right data tables. Similarly, address GAKUFU+3. of the musical score data table.
Data for note (rest) number 12 is set in GAKUFU+4 and CAKUFU+5. That is,
Address GAKUFU+3 contains note (rest) number 12.
represents a quarter note, so set the note data table address 0NPU+2, or "02", and set the address GA.
Since the pitch of this quarter note is "E 11" in KUFU+4, the address FREQD of the frequency data table is
+A Set “OA”.

Address GAKUFU+5 contains the previous address GAKU
Similarly to FU+2, set the left and right data of °“01”. Similarly, three consecutive addresses GAKUF
Add address 0 of the note data table to the first address of U.
Set NPU, set address FREQD of the frequency data table to the next address, and set left and right data to the last address.

Next, the music routine will be explained with reference to FIG. In the first step S1 of the music routine, the start address GAKUFU+O of the musical score data table is set, the note trace counter CUNTM formed in the CPU core 24 is cleared, and the length counter 94 shown in FIG. Data "01" is set in a timer TIM formed in the CPU core 24 so as to count the length of a note or rest. Note that the data "01" initially set in the timer TIM is set at the beginning of the music routine, and determines the timing at which data of the first note or rest is read.

Then, in step S2, the timer TIM is decremented, and in step S3, it is determined whether the timer TIM has timed up, that is, whether TIM=O. Then, the process returns to step S2 and the decrement of the timer TIM is repeated until TIM=O.

Initially, "0" is set as the note trace counter CUNTMO value n. Then, in step S4,
According to its note trace counter CUNTMO value n,
From the address GAKUFU+n of the music score data table,
Read address H (ONPU+H) of the note data table.

In step S5, it is determined whether the data H in the previous step S4 is "FF". That is, in this step S5, it is determined whether the music routine ends. If the process is not completed, each step after step S6 is executed, and note length data, frequency data, and left/right data are set in each register, that is, the CPU core 24, for each note (or rest).

In step S6, note (or rest) data, that is, note length data L is read from address 0NPU+H of the note data table. Then, in step S7, the timer TIM is set to the note length data "18°" for note (or rest) number 11 of sound 2 in FIG. 6, for example. In this way, by steps 34 to S7, the note (or rest)
Data, that is, tone length data is set.

In the next step S8, the note trace counter CU
Increment NTM. Therefore, the note trace counter CUNTM becomes "n+1'", and according to the value of the counter, the address GAK of the musical score data table is
The data of UFU+n, that is, the address Q of the frequency data table (FREQD+Q) The frequency data X is read from the address FREQD+Q of the frequency data table (step 310), and in step Sll, the address FREQD+Q+ of the frequency data table
Read data Y@ from 1.

Then, in step 312, x−y=.

In other words, it is determined whether the data of the read frequency data table is rest data or musical note data. If it is musical note data, that is, if it is determined as "YES'" in step S12, then in step S13, the frequency data X read out in step SIO is set in the frequency setting register 84 shown in FIG. 5, that is, register NR13. Then, the frequency data Y read out in step Sll is read into the register NR14. If it is determined in step S12 that it is a rest, in step S14, "0000" is set in the envelope initial value register 104 in FIG. 5, that is, the upper 4 bits D4 to D7 of register NR12, and The down register 106, that is, the bit D3 of the register NR12, is set to "O". As a result, a decoder signal is output from the decoder 108, and the D/
Sound output from A converter 96 is stopped.

Note that "i" here refers to the sound circuits 541 to 5.
In this way, steps 58 to 513 (or 514)
Accordingly, frequency data is set in the sound circuit shown in FIG.

Then, in the next step S15, the note trace counter CUNTM is incremented. Step S1
6, data D from address GAKUFU+n+2 of the musical score data table is read out according to the count value n+2 of the note trace counter CUNTM. Then, in step 317, the read data is set in the register NR51 shown in FIG. In this way, left and right data are set through steps 315 to 517.

In addition, in the above-mentioned score data table, left and right data were stored for every note or rest, but now the left and right data is written only when there is a change in the previous left and right data. This will allow you to save memory capacity.

Finally, in step 31B, the counter CUNTM is incremented and the process returns to step S2.

It goes without saying that the present invention is applicable not only to the portable game machine described in the embodiment, but also to other game machines and other electronic devices.

(Margin below) Musical score data table

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a perspective view showing an example of a portable liquid crystal game device to which the present invention can be applied. FIG. 3 is a block diagram showing the overall configuration of the apparatus shown in FIG. 1. FIG. 4 is an illustrative diagram showing the memory map of FIG. 2. FIG. 5 is a circuit diagram showing an example of the sound circuit included in FIG. 3. FIG. 6 is a musical score representing concrete music generated by the embodiment of FIG. FIG. 7 is a flow diagram showing a music routine prestored in the program ROM. In the figure, 24 is a CPU core, 541 to 544 are sound circuits, 58 is a sound control circuit, and 681L
~684L, 681R~684R. 70L and 70R are analog switches, 72L and 72R are electronic volumes, 60.60L and 60R are sound amplifiers, 82 is a frequency counter, 84 is a frequency setting register, 92 is a length setting register, 94 is a length counter, NR
II, NR12, NR13, NR14, NR50, NR
51 and NR52 indicate registers. Patent Applicant Nintendo Co., Ltd. Agent Patent Attorney Yama 1) Yoshihito Drawing Book III No. 1 @ Figure Graph Graph Procedural Amendment C''ji Side Display of August 22, 1999 Incident 1999 Patent Application Name of invention No. 101027 Relationship to the case of the person who amended the memory cartridge Patent applicant address 60 Fukuinakami Takamatsu-cho, Higashiyama-ku, Kyoto-shi, Kyoto Prefecture Name
Name: Nintendo Co., Ltd. Representative Hiroshi Yamauchi! 5416 Osaka (06) 229-0531 residence
Address: 2-6-6-6, Fushimi-cho, Chuo-ku, Osaka City, Drawing 7 to be amended, contents of amendments Figures 2 and 7 will be revised as shown in the attached sheet. Written amendment to the above procedures (voluntary) August 22, 1999 Display of the case 1999 Patent application No. 101027 Name of the invention Memory cartridge Amendment to the case Patent applicant address Fukuinakami, Higashiyama-ku, Kyoto-shi, Kyoto Prefecture Takamatsucho 60 name
Name: Nintendo Co., Ltd. Representative Hiroshi Yamauchi Address: 85416 Osaka (06) 229-0531
Address: 2-6-6 Fushimi-cho, Chuo-ku, Osaka City Drawing 6° Contents of correction Figures 1 and 3 to 6 will be corrected as shown in the attached sheet. that's all

Claims (1)

[Scope of Claims] 1. A sound source signal generating means for generating a sound source signal according to data from a memory cartridge, and an input terminal thereof is connected to an output of the sound source signal generating means, and an output terminal thereof is connected to a first and second sound source signal. A memory that is detachably attached to a game machine main body and includes switching means that is connected to a signal output section and selectively outputs the output of the sound source signal generation means to the first or second audio signal output section through a switching operation. A cartridge, comprising: a first storage means for storing in advance data correlating with note length, pitch, and left and right so as to represent a series of music; and a first storage means for storing the data from the first storage means at a predetermined timing. The second to remember the program to read with
a storage means for setting the tone length correlation data, pitch correlation data, and left and right data in the game machine main body according to the read data, and setting the sound source signal of the game machine main body according to the tone length correlation data and pitch correlation data. A memory cartridge, wherein the generating means is controlled, and the switching means is controlled according to the left and right data. 2. The first storage means includes a tone length correlation data table and a pitch correlation data table, and the tone length correlation data table stores in advance tone length correlation data representing each of a plurality of usable tone lengths. In the pitch correlation data table, pitch correlation data representing each of a plurality of usable pitches is stored in advance, and the first storage means further includes a musical score data table representing the series of music, The addresses of the tone length correlation data table and the pitch correlation data table and the left and right data are stored in advance in the musical score data table, and the tone length correlation data, pitch correlation data, and left and right data are read out according to the program. The memory cartridge according to claim 1, wherein: