The best at present complete electronic game computer that one exemplary embodiment provided by the present invention is at first described.Then provide the more detailed description of microcomputer architecture in this most preferred embodiment, comprise the memory organization of the demonstration of the demonstrative structure of microcomputer and microcomputer.Then, provide the detailed description of the sound generator of most preferred embodiment.About sound generator, the total structure and the operation of most preferred embodiment sound generator are at first described, comprise in the mode that is fitted to each other and use a plurality of independent sound generating circuits better, to produce pseudostereo.Secondly, provide the demonstrative structure of a plurality of independent sound generating circuits and the detailed description of operation.Then provide executable demonstration programme control step and can be by the microcomputer access of most preferred embodiment description in order to the relevant exemplary data structure of generation delegation music.At last, provide the description of the stereo/monophonic sounds translation circuit of demonstration.
Fig. 1 is for showing best at present one exemplary embodiment, the i.e. elevation view of exemplary handheld formula liquid crystal electron game machine shell according to the present invention.This hand-hold type liquid crystal game machine (hereinafter referred to as " game machine ") 10 comprises the casket 12 that disposes liquid crystal display (LDC) screen 14, and described LCDs is included in the some display segment that its front portion or upper face are arranged according to dot matrix way.
Shielding 14 relative positions with LCD on the back of casket 12 or lower surface forms and inserts mouthfuls 68.Can with external ROM cartridge 16 plug-in types be inserted into this insertion mouthfuls 68.More particularly, in inserting mouth 68, dispose 32 pin connectors 20.Insert mouth 68 by external ROM cartridge 16 is injected, the connector (not shown) that external ROM cartridge 16 printed circuit board edges form is connected with this connector 20 with the form of mechanical connection to be electrically connected.Like this, external ROM cartridge 16 can connect/removably link with game machine 10.
As mentioned before, external ROM cartridge 16 is " a memory cartridge ", and the game device 10 that this memory cartridge is inserted wherein is " a main device ".Cartridge 16 and main device 10 constitute electronic game computer.Different memory cartridge 16 can be injected and insert mouthfuls 68 so that different program control instructions to be provided, thereby change the recreation of being played.
Externally comprised external ROM 16a (seeing Fig. 9 A) in the ROM cartridge 16.The program control instruction district 310 stored games of ROM16a externally.In addition, well-known, cartridge also can comprise additional storage arrangement (for example, expansion RAM, bank controller (MBC), or the like).When external ROM cartridge 16 is inserted game machine 10, just carry out games, make on LCD screen 14, to demonstrate image, produce game music by loud speaker 11 or by the earphone that is connected with socket 64.
In box 12, also dispose 6 pin connectors 65, utilize this connector this game machine to be connected with other machine, make when outside cartridge comprises multiselect hand games, just can carry out the contest between the multiselect hand by appropriate cable.
The user input apparatus that in most preferred embodiment, will comprise corss key switch 18 be configured in box 12 positive or above left-hand portion below the LCD screen 14, as shown in Figure 1.Corss key switch 18 has four direction specifying part or contact, presses wherein any, for example, just may make character shown on display 14 upwards or downwards or left or move right.In addition, as shown in Figure 1, at casket 12 positive or above LCD screen 14 below the position, right side dispose two push-button switch 70a and 70b.Shield 14 shown game character when carrying out various predetermined function when needs are controlled at LCD, can handle this two button 70a and 70b.For example, when push-button switch 70a pressed, shown character may jump, and maybe when pressing the button switch 70b, this character can it seems as if throw stone or delivery or throw various other objects.Come device corss key switch 18 to make it and can operate by left-handed thumb like this, the right hand and the right hand are collaborative to be clipped in casket 12 in the hand, and push-button switch 70a is become with the 70b device and can be operated by the thumb of the right hand.
And, the positive of the casket 12 of game machine 10 or above starting switch 72 and selector switch 74 are housed.Starting switch 72 as seen in Figure 1 and selector switch 74 are installed in the zone 78 of corss key switch 18 and push-button switch 70a and 70b below.These switches 72 and 74 are installed so that the thumb of arbitrary hand is operated in the available left hand and the right hand concentratedly (when holding the casket 12 of game machine 10 with the right hand leftward).In other words, can be operated switch 72 and 74 and be need not obviously to change the position of hand.For example, by using the menu screen to use selector switch 74 to select to show the mode of operation of recreation.About this point.Available selector switch 74 is selected in several ranks of playing games.In addition, the function of " weapon " that the selection game character can be able to be used is assigned to and selects switch 74.
Operation start switch 72 starts selected recreation.So, usually needn't operation start switch 72 and selector switch 74 during playing.Yet, also be assigned to starting switch 72 owing to will suspend (PAUSE) function, so when requiring recreation can press starting switch 72 when temporarily stopping.To after this time-out, start recreation, can press starting switch 72 once more.And, might under program control, make starting switch 72 and selector switch 74 have many other functions, in the process of playing games, dynamically change the function that is assigned to these switches thereby make.
On this external casket 12 on/off switch 1 is housed also, cell potential lamp 13, contrast adjustment 50 and volume regulate 66.
The core of game device 10 is microcomputers 22 (detailed schematic diagram of electronic circuit in the game device) shown in Figure 2.Microcomputer 10 comprises CPU24, realizes as just the VLSI integrated circuit microprocessor chip of its available commercial existing microprocessor such as Z80 type of example.CPU24 is by sequential parts 25a, control bus 26a, address buffer 25b and address bus 26b, data buffer 25c and data/address bus 26c (these buses and related device also are connected CPU with work RAM or scratchpad memory 23) be connected with 32 pin cartridge connectors 20 (thereby making it to be connected with other element with the interior memory of cartridge 16).When external ROM cartridge 16 meshed with game machine 10, CPU24 combined with external ROM cartridge 16 and collaborative work.
Now more specifically with reference to figure 2A, address decoder 33 in CPU24 and the most preferred embodiment and memory select (body switching) circuit 32 to match so that at the various devices of address space internal gating (for example, the inside ROM30 in the cartridge 16, internal RAM 28 and external ROM 16a) of CPU.In addition, address decoder 33 can be used to allow in CPU24 gating other square frame shown in Figure 2 contained various external control registers (for example, the control register in the sound generator 58) or can carry out this function by other similar address decoder.
Shown in Fig. 2 A, CPU24 preferably comprises inner 8 general and special register, and 16 programmed counting is according to device PC and 16 s' stack pointer SP.Register A can be used as accumulator and another register F can be used as flag register.CPU24 preferably has the dependent instruction set that allows to comprise following content: various 8 and 16 move instructions of carrying out between register or register pair; Various 8 and/or 16 s' arithmetic operation instruction (for example, ADD, SUB, AND/OR, INC, DEC, or the like), various displacements/ring move operational order (for example with the content of registers of defined left/right ring moves), the control operation instruction of various positions (for example, the illustrated position of set in illustrated register), condition and unconditional transfer instruction, above these of subroutine call and return and various program control operation (for example, start, stop, do-nothing operation or the like) are those skilled in the art and know.
Carry out such certain operations in the most preferred embodiment under the control of the program control instruction of CPU24 in being stored in memory cartridge 16, thereby the response user provides the demonstration of playing games by user input apparatus 18 formed user input signals on display 14.In addition, CPU guide sound tone generator 58 produces under the control that is stored in program control instruction identical described in the cartridge 16 and the corresponding music and/or the sound of playing games.
Refer again to Fig. 2, provide clock pulse to CPU24 by the oscillating circuit 24b that responds quartz crystal unit 24a.Clock pulse divider 24c produces a kind of or how towards clock pulse speed, and can be programmed to this divider 24c by CPU24, will be divided by by the clock pulse ratio on request that oscillating circuit 24b produces.
Also can equip programmable external hardware timing circuit 24d, make CPU can judge the moment that current required time has been crossed at interval.In most preferred embodiment, CPU24 can pack into the numerical value that has the express time siding-to-siding block length timing circuit 24d and start this timer.Automatically minute at interval and when this time interval past tense, this timing circuit can produce interrupt signal for this timing circuit 24d, and this interrupt signal is added to CPU24 (for example, by interrupt control unit 24i) come the CPU time of fire alarming is pass by at interval.Like this, CPU just has the timing ability and need not to use software timing circulation (it may take CPU processing time and resource).If be ready, this timing circuit 24d also can be used for the timing (will make cutline) by sound generator 58 note that produces.
In most preferred embodiment, under the control of dma controller 34, CPU24 outputs to lcd controller 38 with video data by line buffer 36.Lcd controller 38 is connected to display random access memory 42 by LCD display random access memory interface 40 and control address and data/address bus.
Lcd controller 38 under CPU24 control, but carry out work by the control/status register of various addressings, described control/status register is arranged in the cpu address space shown in Fig. 3 A-3D usually.For example, these registers can comprise following these registers: the LCD display register, the lcd controller status register, level and vertical volume register, LCDC (lcd controller) vertical row marker register and mobile object and background drawing board (for example, in 2 dense darkness that can the identify four kinds of tone colors) data register of going up.The LCD display register is controlled the character of this demonstration, and the current state of status register indication lcd controller.It is effective can making every some institute's corresponding data of background video data by the data of volume register on the change horizontal vertical.The current vertical row that will shown by the data that display driver transmitted is pointed out and controlled to the vertical row marker register.The part or the window of X and Y the window's position register pair LCD viewing area are controlled, shown in present OBJ (film) character and BG (background) character data in the LCD viewing area.
Lcd controller 38 will be transformed to from the LCD drive signal of display random access memory 42 outputs from the demonstration related data of CPU24 output.More particularly, the address from video data designated character RAM and the VRAM (visual RAM) of CPU24 makes character (or object) signal and background signal export from character RAM and VRAM.Corresponding LCD drive signal is synthesized by lcd controller 38.
The LCD drive signal is added to LCD public driver 46 and LCD segment driver 48 by LCD drive signal buffer 44.So,, can shield on 14 according to demonstration related data display graphics at LCD from CPU24 by means of LCD public driver 46 and LCD segment driver 48.For example, the pixel of LCD screen definable 144 * 160 or the matrix of point, each pixel or point have corresponding unique " intersection " public electrode/segment electrode combination.LCD public driver 46 drives the row that links to each other with common electrode, and for example, this driver can be the integrated circuit of the LH5076F of Sharp company type.LCD segment driver 48 for example, can be the integrated circuit of the LH5077F type of Sharp company.These display drivers receive the data from LCD drive signal buffer 44, the data that this LCD drive signal buffer then receives from CPU24 by display random access memory 42, LCDRAM interface 40 and lcd controller 38 indirectly.
In addition, intensity level control 50 is connected with LCD buffer amplifier 52 and makes it to regulate the intensity of the demonstration that is produced by LCD plate 14.
Refer again to Fig. 2 A, the reset signal of self-resetting circuit 55 adds to CPU24 and storage-selection circuit 32 in the future.(see figure 1) when the mains switch of game machine 10 is connected, the output reset signal is so just reset to CPU24 and storage-selection circuit 32 when initial.Then, export read signal RD and write signal WR, and these signals suitably are input to external ROM cartridge 16, internal RAM 28, inner ROM30 and storage-selection circuit 32 from CPU24.In addition, address decode signal is added to storage by address decoder 33 select circuit 32.
Below, with reference to figure 3A-3B, describe exemplary cpu address space in detail, be stored in the character of the data in internal storage 30 and the external memory storage cartridge 16.Shown in Fig. 3 A and 3B, inner ROM30 has by address " 0000H-00FFH " specified, first memory block corresponding with first quite little address space." H " points out that these addresses represent with hexadecimal number.In first storage area stores first character that is used to show, for example the sign " Nintendo " and external memory storage reliability decision program.
External ROM cartridge 16 comprises external ROM 16a.Shown in Fig. 3 C and 3D, the storage space of external ROM 16a is divided into by second specified memory block of address " 0000H-0FFH " (it is same corresponding with the defined address of above-mentioned first address space), and by the 3rd specified memory block of address " 0100H-7FFFH " (second address space).In the zone of the address that originates in the 3rd memory block " 0100H " in the external memory storage cartridge of permission, store second character data (it is identical with first character data).In the remaining area of the 3rd memory block, store games.Preferably, in the later several bytes of the second character data storage area storage such as the sign manufacturing firm code, game name, cartridge type, memory span, or the like auxiliary data.In addition, when the desired memory space of games was big, second memory block of available external ROM 16a (" 0000H-00FFH ") stored this routine data of this recreation.
Sound generator 58 shown in Figure 2 also can be by CPU24 according to being controlled in 16 program stored control commands of cartridge.In most preferred embodiment, sound generator 58 comprises the independent sound generating circuit that many CPU can be controlled alone or in combination, to produce multiple sound simultaneously.These registers reside in the unit F F00 (16 system) of memory space shown in Fig. 3 B and the section of " various register " between the FF80 (16 system).CPU24 by suitable control data is write be physically located within the sound generator but can be by CPU direct addressin, be arranged in the eight bit register in cpu address space, thereby guide sound tone generator 58.
In most preferred embodiment, the register interface of this sound generator takies address FF10-FF26 in the cpu address space, and it is as follows specifically to take situation:
Register NR10-NR15 (controls first sound generating circuit and is positioned at address FF10-FF14;
Register NR21-NR24 (controlling second sound generating circuit) is positioned at address FF16-FF19;
Register NR30-NR34 (controlling the 3rd sound generating circuit) is positioned at address FF1A-FF1E;
Register NR41-NR44 (control falling tone sound generation circuit) is positioned at address FF20-FF23; And
Register NR50-NR52 (output to each sound generating circuit provides whole sound control) is positioned at address FF24-FF26.
Above mentioned some register is write and other read/writable only.Just the sonorific various parameters of may command are (for example by directly control data being write suitable sound control register (below will be briefly described it) for CPU24, the frequency range parameter of specific sound generation circuit, waveform duty cycle, the sound duration, the multinomial count parameter of envelope feature, sound frequency, specific sound generation circuit, specific sound is to the distribution and the audio output level of specific output channel).
Fig. 4 is the more detailed schematic diagram of sound generator square frame 58 shown in Figure 2.Sound generator square frame 58 in most preferred embodiment comprises: a plurality of sound generator circuit 541-544, an analog multiplexer square frame 200, left and right solid-state volume controll block 72L, 72R, left and right channel audio amplifier 60L, 60R and stereo/monophony are selected circuit 202.
In most preferred embodiment, under the control of the content of the control register NR10-NR44 of sound generator circuit 541-544 in the address space of aforesaid CPU24, produce sound signal independently of one another.By the NR50 of the register in the address space of CPU24-NR52 control analog multiplexer 200 so that the output signal of each sound generator circuit 541-544 is sent among left passage volume control 72L and the right passage volume control 72R one or both.As promptly being illustrated in more detail, the output to each sound generator circuit 541-544 under program control of the multiplexer 200 of simulation provides independently multipath conversion control.As an example, the output of a sound generating circuit optional to left passage volume control 72L path and the output of another sound generating circuit is optional to right passage volume control 72R, and again the output of another sound generating circuit may be selected to the volume control of a left side and right passage, any (all these appointments can change under program control) in also having the output of another sound generating circuit then two volumes of gating controlling.
The output signal of volume control 72L, 72R is amplified by left passage audio amplifier 60L and right passage audio amplifier 60R respectively.Output with audio amplifier 60 is added to stereo/monophony selection circuit 202 successively then, makes it to be applicable to inner mono speaker 120 or is applicable to optional outside stereophone 64 by earphone socket 122.
Analog multiplexer 200 receives the corresponding output signal (that is sound-source signal) of sound generating circuit 541-544.Analog multiplexer 200 comprises and is used for a pair of analog switch of sound generating circuit 541-544 separately.For example, analog switch 681L, 681R are corresponding to sound generating circuit 541; Analog switch 682L, 682R are corresponding to sound generating circuit 542; Analog switch 683L, 683R are corresponding to sound generating circuit 543; Analog switch 684L, 684R are corresponding to sound generating circuit 544.Each output to an analog switch in the analog switch (for example, analog switch 681L, 682L, 683L, 684L) is connected with left audio frequency bus 300 usually.Left audio frequency bus 300 is connected with the input of volume controll block 72L successively.Similarly, each output (for example, analog switch 681R, 682R, 683R, 684R) then be connected (that is, making all these its outputs of the analog switch of mentioning have public connection) with right audio frequency bus 302 to another analog switch in the analog switch.Right audio-frequency bus 302 links to each other with the output of right passage volume controll block 72R successively.The corresponding output of solid volume controll block 72L, 72R (that is two voice signals) is amplified also by a left side and right channel amplifier 60L and 60R respectively and is exported as the first and second voice output S01, S02 thereafter.In the embodiment shown, the output S01 from amplifier 60L can be used as left channel sound signal, and will be used as right channel sound signal from the output S02 of amplifier 60R.
Fig. 4 A for describe shown in Fig. 4 exemplary register NR50, NR51 and the theory diagram of NR52.Register NR50-NR52 is used for controlling some running parameter of sound generating circuit 541-544, analog multiplexer 200 and volume control 72L, 72R in most preferred embodiment.Although in Fig. 4, described a plurality of register NR50A-NR50C, but, the register that in fact NR50A-NR50C comprises the single multidigit shown in Fig. 4 A (for example, 8), similarly, in fact a plurality of register NR52A-NR52B shown in Figure 4 comprises single long numeric data register NR52 shown in Fig. 4 A.
Register NR52A-NR52B (comprising single 8 registers that operationally are coupled with CPU24 in most preferred embodiment) is used for control and allows/forbid sound generating circuit 541-544.Shown in Fig. 4 A, the Must Significant Bit D7 of register NR52 can be used to allow/forbid all sound generating circuits 541-544.If the Must Significant Bit D7 of register NR52 is set to logic level 1, all sound generating circuits 541-544 become exercisable so, similarly, if logic level " zero " value is write the Must Significant Bit D7 of register NR52, then forbid all sound generating circuits 541-544.Minimum 4 D0-D3 of register NR52 are used as the connection sign of the sound generating circuit of each sound generating circuit 541-544, and can make it individually to allow or forbid each sound generating circuit according to the logic level values that writes these 4 D0-D3.
In most preferred embodiment, the state of analog switch 681L-684L, 681R-684R is controlled by register NR51, also shows its detailed schematic diagram among Fig. 4 A.In most preferred embodiment, register NR51 also is 8 bit widths.Minimum 4 D0-D3 of register NR51 correspond respectively to analog switch 681L-684L and control these analog switches connect or close (promptly by or not by) respectively with the output of left audio frequency bus 300 corresponding sound generating circuits 541-544.Similarly, the highest 4 D4-D7 of register NR51 control analog switch 681R-684R respectively and connect or close (so that right audio frequency bus 302 is sent or do not delivered in the output of the circuit of enable voice generation controllably 541-544 respectively).
For example, suppose position D0 and the D4 (for example, they correspond respectively to analog switch 681L and 681R) that the logic level null value is write register NR51.The logic level null value control analog switch 681L that is stored in lowest order D0 closes---effectively the output of sound generating circuit 541 and the input of the solid-state volume controll block of left passage 72L disconnected whereby.Equally, the logic level zero of register NR51 position D4 storage is controlled the input disconnection that analog switch 681R makes sound generating circuit 541 and the solid-state volume controll block of right passage 72R effectively.Therefore, as long as the value of this two " zero " position is stored among the register NR51, the output of sound generating circuit 541 is just neither delivered to left channel output end S01, does not also deliver to right channel output end S02.Logic level 1 is write register NR51 position D0 to be controlled analog switch 681L left passage output S01 is delivered in the output of sound generating circuit 541; The position D4 that logic level 1 is write register NR51 controls analog switch 681R right passage output S02 is delivered in the output of sound generating circuit 541; The value of logic level 1 is write a D0 and D4, then control analog switch 681L and 681R a left side and right audio signal output terminal S01, S02 are delivered in the output of sound generating circuit 541 respectively.
In brief, each corresponding position in two of register NR51 storages in the most preferred embodiment and the sound generating circuit 541-544, these two positions are controlled the analog switch 681 that is connected with sound generating circuit, selectively the output of sound generating circuit are sent or do not delivered to output S01, S02.If these two positions are logic level zero, any among sound output S01, the S02 do not delivered in the output of sound generating circuit so.As wherein 1 for logic level 1 in addition 1 be logic level zero, one (output of which the termination receipts sound generating circuit among audio signal output terminal S01, the S02 depends on who is a logic level 1) among sound output S01, the S02 only delivered in the output of sound generating circuit so.On the other hand, if two positions all are changed to logic level 1, then audio signal output terminal S01, S02 receive the output signal from corresponding sound generation circuit.
At (shown in Fig. 4 A) in the most preferred embodiment, in fact register NR50A-NA50C shown in Figure 4 comprises single eight bit register NR50.Two position D3, the D7 of register NR50 are used to switch on and off another group analog switch 70L, 70R, and the input of these two analog switches is connected with the signal VIN that obtains from outside sound source.For example, in most preferred embodiment, can provide the additional sound source signal by sound generation source rather than sound generating circuit 541-544.The sound-source signal that this outside provides is transfused to as signal VIN, can be delivered to selectively on left audio frequency bus 300 and the right audio frequency bus 302 by analog switch 70L, 70R respectively.Its open/close state of analog switch 70L, 70R is selected by register NR50 position D3, D7 respectively successively.
6 of the residues of register NR50 are used to control the degree by solid-state volume control 72L, the added amplification of 72R in the most preferred embodiment.Like this, in an exemplary embodiment, register NR50B as shown in Figure 4 comprises lowest order D0-D2 of register NR50, and register NR50C shown in Figure 4 comprises the position D4-D6 of register NR50 shown in Fig. 4 A.By 2 system numerical value " 000 "-" 111 " are set to the territory of these three positions, might control the output level of solid-state volume controll block 70L, 72R with 8 grades from the minimum to the maximum.Therefore, for example, numerical value " 000 " is write register NR50 lowest order D0-D2 in the most preferred embodiment, control solid-state controll block 72L provides minimum radius with regard to the input of giving left channel amplifier 60L level (, can be zero amplitude) as requiring.Similarly, numerical value " 111 " is write register NR50 position D4-D6, then control the solid-state volume controll block of right passage 72R and make that the enhancing degree of supplying with the solid-state volume controll block of left passage signal by right passage audio frequency bus 302 is minimum, thereby offer the output of right channel sound signal output S02 maximum (the loudest) signal level.
Together with reference to figure 4 and Fig. 6, as an example, sound generating circuit 541 can be used as melody source (" sound 1 ") now, so that first segment shown in Figure 6 or first row of exemplary melody to be provided.Remaining sound generating circuit 542-544 can be used for producing the rhythm sound of more following three music measures shown in Figure 6.Certainly, also can any desired compound mode use sound generating circuit 541-544, with produce multiple melody (that is, the contraposition sound), melody and harmony together, the combination of music and effects,sound, or the like.
In music score shown in Figure 6, the sound that the music row that is marked with S01 occurs corresponding to left passage, and the music row that is marked with S02 is corresponding to the sound that occurs on right passage.Fig. 6 illustrates the note of description in a usual manner and the standard music score of rest.4 shown trifle music are as example (can play the melody of desired any length although should be understood that system described herein, its length only is subject to memory span).
During all 4 trifles, be controlled to be analog switch 681L and 681R logical as for 4 trifle music shown in Fig. 6 first segment (" sound 1 "); So that during all 4 trifles will by sound generating circuit 541 the melody output signal takes place outputs to two amplifier 60L, 60R.Like this, during all 4 trifles, will write D0 and the D4 position of register NR51 to data value " 1 ".
On the contrary, shown in the joint that indicates " sound 2 " among Fig. 6, the output of sound generating circuit 542 then replaces between a left side and right passage S01, S02.Like this, the output of sound generating circuit 542 is provided for sound output S01 rather than sound output S02 during the 1st trifle; During the 2nd trifle, offer two sound output S01, S02, and during the 3rd trifle, only offer sound output S02 rather than sound output S01, during the 4th trifle, offer two outputs of S01, S02.Therefore, in the 1st trifle, CPU writes the position D1 of register NR51 with data value " 1 " and numerical value " 0 " is write the position D5 of register NR51.In the 2nd trifle, numerical value " 1 " is write the position D1 and position D5 of register NR51,682L, 682 R boths connect and two output channel S01, S02 are delivered in the output of sound generating circuit 542 to make simulation open also.During the 3rd trifle, opposite with the 1st trifle, " 0 " is write register NR51 position D1 and " 1 " is write register NR51 position D5, analog switch 682L is closed and analog switch 682K is connected the output supply output channel S02 rather than the output channel S01 of sound generating circuit 542 (so that with).
Similarly, " sound 3 " this delegation of music score points out that the output of sound generating circuit 543 replaces between passage S01 and S02 as shown in Figure 6.That is, during the 1st trifle, analog switch 683L connects (by logic level " 1 " is write register NR51 position D2) and analog switch 683R closes (writing register NR51 position D6 by the numerical value with logic level " 0 ").So,, the output of sound generating circuit 543 is added to voice output passage S01 rather than voice output passage S02 in the 1st trifle.But during the 2nd trifle, on the contrary, then respectively with numerical value " 0 " and " 1 " so write the position D2 of register NR51 and D6 to close analog switch 683L and to connect analog switch 683R., only the output with sound generating circuit 543 offers voice output passage S02 and does not offer voice output passage S01.
Use similar approach, by at the position D3, the D7 that during the trifle numerical value " 1 " and " 0 " are write register NR51, then during the 2nd trifle, numerical value " 0 " and " 1 " are write D3, the D7 of register NR51 respectively, and during the 3rd trifle, numerical value " 1 " and " 0 " are write the D3 that puts in place, D7, or the like, thereby the output of the such gating sound generating circuit 54 of bottom line music score as shown in Figure 6.
Very clear, register NR50-NR52 normally is written in parallel to, so that for example all D0-D7 of register NR51 are usually each when rewriteeing, any channel allocation position will change.
Like this, the melody sound that is produced by sound generating circuit 541 according to exemplary music shown in Figure 6 and switched on and off selectively by means of analog switch 681L-684R by the rhythm sound that sound generating circuit 542-544 produced according to the demonstration music is suitably mixed these 4 sound-source signals and offer solid-state volume respectively by a left side and right audio frequency bus 300,302 and controls 72L, 72R.The output level of these mixed signals is controlled by solid-state volume controll block 72L, 72R so that the voice output signal S01 that separates of left and right audio channel and S02 (wherein combination or the synthetic sound that melody and rhythm are arranged) can be exported from amplifier 60L, 60R independently according to the content of register NR50 position D0-D2, D4-D6.By amplification quantity with respect to another volume controll block, to an amplification quantity change in the volume controll block 72, might change the spatial relationship that earphone (64) wearer felt (making that as if sound source to move with respect to the position of user's head).
Fig. 5 is the detailed theory diagram as exemplary sound generating circuit 541-544 one of them demonstrative structure.Although a sound generating circuit only is shown among Fig. 5, but in structure, operating aspect, 4 sound generating circuits 541-544 can be similar each other, in any case and, to the wherein description of 1 sound generating circuit, to this field those skilled in the art, all be enough to provide details about all 4 circuit.Therefore, this paper only need describe in 4 sound generating circuits one in detail.In most preferred embodiment, in fact sound generating circuit 541-544 is not mutually the same, because some of them generation circuit comprises the enhancing ability that is used to produce various effects,sounds.For example, sound generating circuit 541 can comprise sweep oscillator, sound generating circuit 543 can not comprise duty ratio control, and sound generating circuit 544 can comprise the frequency selective network of multinomial counting clock type, and it is known that all these are all these those skilled in the art.
Refer now to Fig. 5, sound generating circuit 542 comprises various counters, divider and other element that is controlled by control register NR21-NR24.Briefly, element 74-94 is provided for starting/forbidding the clock signal that the content of envelope counter 102 is transformed to the conversion process of voice output signal by D/A converter 96.Like this, 74-94 pairs of elements and voice output signal, envelope counter 102 relevant time sequence parameters are controlled, and the amplitude of relevant elements 98-106 control sound output signals.As will be described, decoder 108 sound generating circuit 542 that is used for resetting.
Frequency is the time base that the reference clock signal (this signal is preferably provided by controlled xtal osc 24a and related elements shown in Figure 2 in most preferred embodiment) of f offers sound generating circuit 542 shown in Figure 5.For example, this clock frequency signal can be 4.194,304MHZ in most preferred embodiment.In addition, for example, the clock signal (frequency that for example, has 64Hz and 256Hz) by fixed frequency that clock frequency f frequency division is obtained adding also can offer sound generating circuit 542.
In most preferred embodiment, reference clock signal f is added to the input (for example, can comprise a pair of trigger that constitutes 2 digit counters) that removes 4 division circuits 74.Remove 4 circuit 74 in a well-known manner with clock frequency f divided by 4, and the frequency signal that this removes is added to an input of AND gate 76.Another input of AND gate 76 links to each other with the Q output of trigger 80.In most preferred embodiment, trigger 80 is used for by effectively the clock frequency f gating (by AND gate 76) that removes being brought in startup and forbidden sound generating circuit 542 to the input of frequency counter 82.Value according to the highest order D7 of register NR24 (referring to Fig. 5 b) is come set flip-flop 80.Like this, when logic level " 1 " was write register NR24 highest order D7, trigger 80 set made the AND gate conducting thus so that from removing of divider 74 output clock frequency signal pass to the input end of clock of frequency counter 82.In most preferred embodiment, trigger 80 responds the output of decoders 108 and resets, as what be about to be illustrated.
In most preferred embodiment, the frequency (pitch) of the audio output signal that frequency counter 82 controls are to be produced.In most preferred embodiment, frequency counter 82 comprises the programmable frequency divider of a conventional structure.Determined by the frequency data that are included in register NR23 and the NR24 by frequency counter 82 performed frequency ratios.Particularly, minimum 3 D0-D3 of register NR24 comprise three highest orders of 11 bit frequency data values, and all 8 D0-D7 of register NR23 be used for this frequency data value than the least-significant byte part.Shown in exemplary electrical circuit in, the 11 bit frequency data values that are stored among register NR23, the NR24 are controlled frequency counter 82, to produce the output signal of frequency f d.
Fd=4194304/ (4 * 2
3(2048-X)) wherein fd is unit with Hz, and X is 11 a frequency values.This frequency data value X control is by the pitch (that is, " interval ") of sound generating circuit 542 signal that produces.
The output of frequency counter 82 is added to the input of duty circuit 88.Duty circuit 88 is provided with the content of register 86 according to duty ratio, and the duty ratio of the audio output signal that produced by sound generating circuit 542 is controlled.Shown in exemplary electrical circuit in, duty ratio is specified by two highest order D6-D7 of register NR21.As everyone knows, waveform duty cycle relate to periodic waveform for the time quantum of logical (ON) with respect to the time quantum of periodic waveform for disconnected (OFF).Therefore, 50% duty ratio (is provided with the highest order D6 of register NR21-D7) mean that time that periodic waveform is logical and the time of breaking are the same with numerical value " 00 ".In most preferred embodiment, numerical value " 11 " is write register NR21 highest order D6-D7 select waveform duty cycle to be 75% (output waveform that produces, its logical time is 1.5 times of disconnected times) like this.Use similar fashion, numerical value " 01 " is write register NR21 highest order, and (D6-D7) just can produce duty ratio and be 25% waveform (that is, this waveform is half of time of breaking for the logical time), and data value " 01 " is write this two highest orders, just can produce the waveform of duty ratio 12.5%.As everyone knows, the change of sound signal duty ratio has changed the tone color of this sound signal, has the possibility that same frequency signal is provided many alternative sounds thus.
In most preferred embodiment, duty circuit 88 is the custom circuit structure, and this circuit can change by the duty ratio of frequency counting according to device 82 periodic signal that provides, thereby in the above 4 duty ratio 1 is provided.
The output of duty circuit 88 offers an input of AND gate 90, the output of this AND gate gating duty circuit under the control of the length gating signal that is produced by length counter 94.Length counter 94 should continue gating signal according to the content generation that length is provided with register 92.In most preferred embodiment, length is provided with the lowest order D0-D5 of register NR21 shown in the register 92 actual Fig. 5 of the comprising B.Length is provided with the divisor of the content control length counter 94 of register 92, and this counter plays conventional programmable divider effect the length clock frequency signal of 256Hz is carried out frequency division.In most preferred embodiment, duration of a sound territory D0-D5 of register NR21 controlled according to the duration of the sound that following relational expression is produced the sound generating circuit 542 with 64 scales.
The duration=(64-T1) * (1/256) second, wherein " duration " be the length of musical sound, and T1 is the specified value of D0-D5 by register NR21.By the output via AND gate 90 gating duty circuit 88, the sound duration that 94 pairs of sound generating circuits of length counter 542 produce is controlled.Like this, sound generating circuit 542 can automatically " be closed " when each note finishes to save CPU and be paid cost by in the suitable time sound generating circuit being closed.Write length by the numerical value that will be fit to register 92 is set, CPU can control sound generating circuit 542, (for example to produce for example any note that requires the duration of a sound, 1/16 note, 1/8 note, 1/4 note, minim or whole note), and similarly, also can be in this way the length of music rest be provided with.
To be added to the permission input of digital-to-analogue (D/A) converter 96 in the synthetic gating signal that AND gate 90 outputs produce.In fact D/A converter 96 produces with the corresponding analog electrical output of voice output of sound generating circuit 542 flat, and the sequential of its generation is controlled by the output signal (and depending on institute discussed above selected frequency, duty ratio and duration) of AND gate 90.Can be to the fixing amplitude of some note, but can automatically increase or reduce described amplitude by D/A converter 96 signal that produces, thus in most preferred embodiment other note of generation or the sound.
The parallel data input of 98-108 pairs of D/A converters 96 of envelope counter 102 and related elements provides parallel data, so that with respect to the time, to controlling (" envelope " of sound relates to the amplitude envelops that comprises sound) automatically by the amplitude " level " of the voice output signal that converter produced.
It is slow that (for example, envelope clock signal 64Hz) is added to the input of programmable 1/N divider 100 in most preferred embodiment.Select by the content of envelope interval number register 98 by the divisor that 1/N divider 100 is provided.In most preferred embodiment, envelope interval number register 98 comprises minimum 3 D0-D2 of register NR22.In most preferred embodiment, 1/64 second prestissimo of sound envelope " amplitude " for a change.Yet the content of envelope interval number register 98 is selected the rate of change of each interval voice output amplitude according to following relational expression.
Second interval duration=N * (1/64), wherein N was the numerical value of being stored among register NR22 meta D0-D3.In most preferred embodiment, " 000 " numerical value of being stored in these has stopped the operation (so that the amplitude of D/A converter 96 voice output that produces is remained unchanged) of envelope counting.
The speed of the output signal control envelope counter 102 increasing or decreasings counting of 1/N divider 100.From envelope initial value register 104 4 initial value being packed into concurrently, (most preferred embodiment, this initial value register comprises 4 highest order D4 of register NR22-D7) to envelope counter 102.In addition, increase/subtract register 106 (in most preferred embodiment, it comprises the position D3 of register NR22) select envelope counter 102 to increase progressively counting or countdown (two kinds of selections are provided like this: it originates in initial value and is incremented to peaked amplitude again, and originate in initial value be reduced to zero amplitude again).In most preferred embodiment, increase/subtract the counting direction of register 106 may command envelope counters 102, perhaps alternately producing input signal points out how the D/A converter explains the numerical value (that is, weaken or strengthen) that is added to it by envelope counter 102 for D/A converter 96, this input signal.
Like this, envelope counter 102 begins counting from the initial value that is provided by envelope initial value register 104, and increases progressively counting (or successively decreasing) with the determined speed of the output frequency of 1/N divider 100.When envelope counter 102 counting, its parallel output valve changes, and owing to be analog signal level by D/A converter 96 value transform that should walk abreast, and the amplitude that is produced the voice output signal by converter changes too so.
Decoder 108 receives the parallel data that provided by envelope initial value register 104 and by increasing/subtract the data that register 106 provides.106 pairs of these data decodings of decoder, and, when the envelope initial value is zero and specifies when successively decreasing direction that the output that decoder 108 will be deciphered is added to the RESET input and the D/A converter 96 of trigger 80.The effect of this reset signal is the operation (making it not output sound) of forbidding D/A converter 96 and forbids AND gate 76 (forbidding whole sound generating circuit 542 thus).
Contact Fig. 7 A-9D below describes the exemplary sequence control step and the related data structures of the operation that is used to control exemplary sound generator 58.
Now more specifically with reference to figure 9A, be used to control sound (the others that also have video game in addition take place, as control by the video game as shown in the LCD display 14, user's input that response is provided by controller 18, or the like) proper procedure control command 310 be stored among outside read-only memory (ROM) 16a in the storage cartridge 16.
In addition, in most preferred embodiment, ROM16a stores 3 and with sound relevant data structure takes place: frequency data table 312, duration of a sound tables of data 314 and music data table 316.Speak briefly, music data table 316 provides pitch for each sound generating circuit 541-544, " audio direction " shown in the duration of a sound and Fig. 6 (left passage, right passage or both).Frequency data table 312 is carried out mapping or the conversion between the digital value of the frequency configuration register 84 be stored in the pitch information in the music data table 316 and the sound generating circuit 541-544 of need packing into, with generation by the specified pitch of music data table 316.Duration of a sound tables of data 314 provides the duration information of being stated in the music data table 316 and need write mapping or conversion between the duration of a sound data that the duration of a sound is provided with register 92.
Fig. 9 B is the exemplary theory diagram of frequency data table 312 content shown in Fig. 9 A.In most preferred embodiment, define each pitch by the sequence that is stored in 4 16 system numerical value in the frequency data table 312.For example, the expression of music rest (promptly, voiceless sound) usable levels " 0000 ", C transfers available " AB01 " expression, and high semitone C transfers available " 0193 " expression, or the like.In most preferred embodiment, frequency data table 312 is that preface is stored these numerical value with the chromatic scale music score, promptly originate in the music body and end symbol, after meet C and transfer, increase progressively pitch (for example, C, C by every semitone
#, D, E
b(D
#), E, F, or the like).16 system data values of storage are with some digital values are corresponding like this in the frequency data table 312, promptly when these digital values being packed relevant into the frequency data register with sound generating circuit 541-544 (for example, as previously mentioned, the position D0 of position D0-D7 and the register NR24 of register NR23-D2) can cause producing the frequency that conforms to definition tone height by related sound generation circuit.That is to say that for example, when 16 system numerical value " AB01 " are write register NR23, during NR24, sound generating circuit 542 has generation the sound of frequency (pitch) C.By digital value being stored in the frequency data table 312, the programmer of writing program control command 310 need not to worry for forming must pack into the concrete digital value of sound control register of desired pitch.Will soon understand that the programmer only need specify the suitable allocation index from base address FREQD, (frequency data table 312 is from the base address) specifies desired suitable tone.Provide by frequency data table 312 then this address type value transform is become to be used to write for example automatic conversion of the proper data of register NR23 and NR24.
Similarly, 314 storages of duration of a sound tables of data and common used note duration are (for example, 16 dieresis or rest, 8 dieresis or rest, 4 dieresis or rest, minim or rest, whole note or rest, band point 4 dieresis or rest, band point minim or rest, or the like).In the one exemplary embodiment that illustrates, duration of a sound tables of data 314 begins storage from base address ONPU, and first entry storage that should the duration tables of data is corresponding to 16 hex value " 06 " of the 16 dieresis duration of a sound.That is, in most preferred embodiment, when the duration that will be worth " 06 " is packed minimum 6 of register NR21 noted earlier into, will make sound generating circuit 542 produce note or the rest of its length corresponding to 16 dieresis with certain predetermined fixed rate.Predetermined order is stored in the different duration of a sound commonly used in the duration tables of data 314.Therefore, the programmer need not to worry must write about obtaining the required duration of a sound the concrete value of sound length position D0-D5 of register NR21 (for instance).On the contrary, he only needs to specify suitable skew in the duration tables of data 314, just can select the duration of a sound that he will use in the duration of a sound commonly used.
Fig. 9 D is the exemplary schematic diagram of music data table 316.Music data table 316 shown in Fig. 9 D corresponding to " sound 2 " (second) of demonstration music shown in Figure 6 OK.Obviously, preferably similar to the data that other 3 row is provided, and the corresponding data of all these 4 row music are read from R0M16a basically concurrently to produce 4 row music simultaneously.In most preferred embodiment, music data table 316 starts from base address BASE, and comprises 3 list items that become by 2 16 system arrays, and each list item is used for represented each note of Fig. 6 music score or rest.Skew in the duration tables of data 314 that first 2 16 system data were consistent corresponding to the duration with note or rest.Second 2 16 system numbers are corresponding to the skew in the frequency data table 312 that is consistent with the requirement pitch.Last 2 16 system data (in most preferred embodiment, because as long as in fact 4 kinds of states of expression can be 1 binary numerical value) are specified " direction " (that is, left passage, right passage, binary channels or do not have passage) of this sound.
Like this, for example, the 1st note of the 1st trifle of " sound 2 " shown in Figure 6 music row is 4 fens rests.Therefore, the skew in first list item of the music data table 316 explanation duration of a sound tables of data 314 is " 02 ", corresponding to 4 dieresis or rest.The zero offset of the 2nd list item explanation audio data table 312 of music data table 316 is to specify 1 rest (opposite with note).The 1st trifle the 1st note the corresponding the 3rd and last list item are numerical value " 01 ", specify this sound only to prepare to deliver to output sound passage S01 and do not prepare to deliver to output sound passage S02.
Music data table 316 provides this data set sequence corresponding with melody or the capable sequence of notes of rhythm.Thereby, for example, in the music data table 316 32 the 16 following system numerical value of storage corresponding to the 2nd note of the 1st trifle of " sound 2 " shown in Figure 6 row, i.e. 4 dieresis transferred of E.The 1st 2 16 system numbers of this data set are " 02 ", specify the 4 dieresis duration of a sound, corresponding to the skew in the duration of a sound tables of data 314.The 2nd 2 16 systems of this data set are counted the skew " OA " in the assigned frequency tables of data 312, are equivalent to the E tone.The last numerical value of this data set is corresponding to audio direction " 01 ", and it is defeated to specify this note only to prepare to offer sound, goes out passage S01 and do not prepare to offer voice output passage S02.
Obviously, thus form is changed whole music row and be stored in the music data table 316 shown in available Fig. 9 D.To " play " by the represented music of this music score, only need order sense data collection with proposition in the music data table 316, with reference to duration of a sound tables of data 314 and frequency data table 312, so that the duration of a sound and pitch information are mapped as the respective value that is housed to suitable sound control register, then, with the actual generated data sound register of packing into.Note is in case stop, and can read from music data table 316 with the data set that next note is corresponding in the music sequence and repeats to have suffered journey once more to produce next note.This whole process can repeat continuously until the termination that arrives music data table 316 (at this moment, if be ready, can be once more from section start read music data table 316, to cause the repetition of melody again and again).
For being implemented in the principle flow chart of the exemplary sequence controlled step in the program control instruction 310 shown in Fig. 9 A, these program steps cause being stored in the sound of music row (example) control in the music data table 316 shown in Fig. 9 D together for Fig. 7 A and 7B.Obviously, several versions in the control of exemplary sequence shown in Fig. 7 A-7B step are preferably carried out (parallel basically) simultaneously and are produced the multirow music with the sound generating circuit 541-544 by each.In other words, the control of the exemplary sequence shown in Fig. 7 A-7B step is only controlled single sound generating circuit (for example, circuit 542).Should carry out other iteration in exemplary sequence step to control other sound generating circuit (for example, 541,543,544) by CPU24.
Once starting the routine shown in Fig. 7 A-7B, just the base address that obtains suitable music data table 316 (promptly, initial address) and with this base address write the memory pointer register (frame 350) that is used to specify specific music data table (obviously, in program ROM 16a, can store music data table 316 more than 1) so that the reproducible a plurality of different possible period or the sound to be provided.Remove note lock-on counter CNT (preferably register in the CPU24 or the unit among the RAM) then and to timer (for example, timer 24d shown in Figure 2) initialization (frame 352).When initial, the value of this timer can be changed to " 01 " so that the remainder of routine shown in successively decreasing immediately and carry out.Timer (frame 354) and judge that whether this value is zero (decision box 356) then successively decreases.Greater than zero, frame 354 timer that successively decreases is once more returned in control as this timer, and repeats frame 354,356 values up to this timer and be decremented to zero.By the circulation that frame 354,356 constitutes the duration of current note or rest is counted, obviously, this timing can be used the interruption of hardware timer 24d driving if necessary in a well-known manner.
Then by the base address being added current C NT value visits the 1st 2 the 16 system data of being stored in music data table 316, thereby access program ROM16a reads the content that is stored in this unit, and with these content stores to the temporary storage location that is called H (frame 358).Then, the content of H is compared with " FF " value, with the end item (decision box 360) that determines whether to arrive music data table 316, (in most preferred embodiment, can by 316 invalid skews indicate the end of this table to duration of a sound tables of data with numerical value " FF " or other).The content of supposing H is effective skew of duration of a sound tables of data 314, use the address of H conduct from the calculations of offset duration tables of data of the base address ONPU of this table so, with the synthetic address that calculates is that the contents of being stored in the duration of a sound tables of data 314 are read in the address, and with these contents timer (frame 362) of packing into.Like this, just come this timer of initialization with next note to be produced or the duration of a sound of rest.This searching value also can be packed into, and (for example NR11 position D0-D5) is so that make CPU24 need not close sound generating circuit when note finishes arriving for the sound length data territory of sound control register.
The numerical value of count-up counter CNT (frame 364) is with 16 system numbers of 2 of the next ones in the visit music data table 316 then.Next unit in the visit music data table, (for example, calculating an address according to base address and CNT sum) read its content and is stored to (frame 366) among the temporary transient preservation unit Q.Use the skew of the frequency data table 312 be stored in temporary transient preservation unit Q now, be used for addressing frequency data table 312 (frame 368,370).In most preferred embodiment, at this moment need two sequential cells of reading frequency tables of data 312, be enough to the information that explanation is stored in 11 bit frequency data among NR13-NR14 for example to retrieve.From frequency data table 312, retrieve these values and it is stored in temporary X, Y (frame 368,370), whether entirely serve as zero, this complete zero points out that sound current to be produced is rest but not note (decision box 372) if testing to judge to the content of temporary storage location X, Y then.If current sound is rest, produce sound (frame 374) to forbid sound generating circuit just remove the register 104,106 that increases/subtract of envelope initial value register and corresponding sound generation circuit (for example 542) so.On the other hand, if the searching value corresponding with certain pitch replaces rest (" N " outlet of decision box 372), just with the value of storing among temporary storage location X, the Y frequency configuration register 84 (frame 376) is set so, to determine to wait to produce the pitch of note.
Increase progressively CNT counter (frame 378) then, read the 3rd value (frame 380) that is stored in corresponding in the music data table 316 " audio direction ".Then these data that retrieve are tested, judge that whether it is corresponding to new outbound course data (decision box 382).In most preferred embodiment, though to the left side shown in Fig. 9 D or right " audio direction " data clearly being described by defined each all note of music data table 316 and rest, but wish that (for example, for saving the cause of memory) just just illustrates the audio direction data when the audio direction corresponding with specific sound generation circuit changes to some extent with respect to this sequence front note.Like this, in most preferred embodiment, because some data set of storage has only 22 16 system numbers rather than 3 (if audio direction is identical with last institute's musical notes, then omitting this audio direction data) in music data table 316.Decision box 382 shown in Fig. 7 B judges whether read new audio direction data, as reading, according to the suitable position that suitable sound control register is set by frame 380 resulting values (for example, register NR51 position D1, D5), (frame 384) and count-up counter CNT (frame 386) are to make it to point to the section start of next data set of being stored in music data table 316.On the other hand, if the value of being read by frame 380 is not new audio direction data, frame 386 is not carried out the increasing progressively of counter cnt so, and control turns back to frame 354,356 shown in Fig. 7 A.
In case control turns back to frame 354,356, the timer that successively decreases is to current note or rest timing.In case this duration goes over, once more to the processing of next note to be produced or rest repeat block 358-386.
Fig. 8 be shown in Figure 4 stereo/monophony selects the schematic block diagram of circuit 202.Select circuit 202 to receive, appropriate signals is sent to loud speaker 120 or gives stereophone 64 from the left channel sound signal S01 of amplifier 60L with from the right channel sound signal S02 of amplifier 60R.Especially, if stereophone 64 plugs are not connected with earphone socket 122, so, stereo/monophony selects circuit 202 that voice signal S01, the S02 of left and right passage mixed so that monophonic signal to be provided, and this monophonic signal is added to loud speaker 120.On the other hand, if stereophone 64 links to each other with earphone socket 122, so stereo/monophony select circuit 202 with left channel sound signal S01 be coupled to earphone left ear transducer, and right channel sound signal S02 is coupled to the auris dextra transducer of earphone.
In most preferred embodiment, the output of amplifier 60L as shown in Figure 4 similarly, is coupled to the output of amplifier 60R shown in Figure 4 the input of amplifier 114R by the input that series resistance 112L is coupled to amplifier 114L by series resistance 112R.Resistance 116L, 116R series connection is connected across the input of amplifier 114L, 114R.Connect the input coupling of node and the monaural amplifier 118 of resistance 116L, 116R.The effect of resistance 116L, 116R is that mixing (monophony) signal that S01 and S02 signal mix and will derive is offered amplifier 118.Amplifier 118 drives loud speaker 120.
Earphone socket 122 comprises left passage audio frequency contact 122L, right passage audio frequency contact 122R and pair of switches contact 122P.Predetermined with the headset plug 124 of earphone 124 couplings by earphone socket 122 acceptance and coupling.Earphone socket 122 for example can be the spill counterpart that matches with headset plug 124 as the plug-in type counterpart.Like this, headset plug 124 just can insert earphone socket 122 so that the output of earphone 64 with amplifier 114L, 114R is connected, thereby and can be afterwards remove this plug from this socket earphone and amplifier are disconnected.For example, the user may wish to listen to the sound (at this moment, headset plug 124 can insert socket 122) that is produced by sound generation frame 58 with earphone 64 sometimes.Other the time, the user may not wish to use earphone and headset plug 124 is extracted (so that listening to sound with loud speaker 120 rather than with earphone 64) from earphone socket 122.
Headset plug 124 comprises left passage contact 124L and right passage contact 124R, when plug cooperates with socket, the left passage audio frequency contact 112L of right passage contact 124L and headset plug forms and electrically contacts, and simultaneously, right passage contact 124R and headset plug left side passage audio frequency contact 112R form and electrically contact.Grounded part 124G preferably joins with ground.The left passage contact 124L of plug is connected to the left passage transducer of earphone 64 by left channel wire 126L, and the right passage contact 124R of plug is connected to the right passage transducer of earphone 64 by right channel wire 126R.
When headset plug 124 was inserted earphone sockets 124, contact 122P just was in contact with one another being electrically connected between the input that forms ground and sign-changing amplifier 130 and non-inverting amplifier 132.This ground connects the signal that makes inverting amplifier 130 produce logic level " 1 ", uses this signal to allow amplifier 114L, 114R work.The signal that also makes non-inverting amplifier 132 produce logic level " 0 " connection of this ground connection is used for forbidding amplifier 118 work.In this state, by amplifier 114L, 114R stereophonic signal is supplied with earphone 64 and forbidden loud speaker 120 by contact 122L, 122R and 124L, 124R.
On the other hand, in case headset plug 124 and earphone socket 122 disconnections, contact 112P no longer is connected with each other.Move logic level " 1 " in the input of the pull-up resistor 128 that links to each other with electromotive force of source with the input of sign-changing amplifier 130 and non-inverting amplifier 132.The high level of this logic level makes sign-changing amplifier 130 hand over logic level " 0 " signal to be added to amplifier 114R, 114L (forbidding this two amplifier work thus) and to make noninverting amplifier 132 that logic level " 1 " signal is added to amplifier 118 (allowing this amplifier work thus).In this case, go out monophonic signal and be added to loud speaker 120 by amplifier 118 synthetic (mixing).Because earphone does not link to each other with seat, amplifier 114L, 114R are not added to signal earphone socket contact 112L, 112R.
Although described the present invention in conjunction with thinking the most practical and illustrated embodiments at present, but be appreciated that, the present invention is not limited to the disclosed embodiments, and opposite, the present invention is intended to cover various modification and the equivalent construction in the spirit and scope that are included in claims.