JPH02278425A - Bit field controller - Google Patents

Abstract

PURPOSE:To shorten the time required for supply of an address for fetch of an instruction through execution of a necessary process by supplying the control data to a process means from a control data output means in parallel with an instruction fetching action carried out by a central arithmetic process means. CONSTITUTION:When an instruction stored in a prescribed area of an instruction store means 2 is fetched, a fetching address is supplied to the means 2 as well as to a control data output means 4. In addition, a control means 3 supplies the control data to a process means 5 from the means 4 in parallel with an instruction fetching action carried out by a central arithmetic process means 1 so that the output of data is granted through the means 4. Thus it is possible to shorten the time required for supply of the fetching address through execution of a necessary process.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a bit field control device, and more specifically, a programmable logic device (hereinafter abbreviated as PLD) in a part of an external memory space. The present invention relates to a bit field control device suitable for controlling a large number of bits by mapping processing means such as the above.

<Prior art and problems to be solved by the invention> Conventionally, the central eL'! of microcomputers, etc. In various fields, a large number of control lines are controlled quickly and in parallel using a J processing unit (hereinafter abbreviated as CPU).
U data memory space, I10100 specific area P
A configuration in which the data is allocated to the LD is adopted. FIG. 5 is a block diagram schematically showing a conventional example, in which the CPU (31)
The address output from the program memory (33) and a plurality of P L
D (34), and C
Data is exchanged between the PU (31) and the program memory (33) through a data bus (35). Control data output from the CPU (31) is sent to the program memory (33) and a plurality of PLDs (3) through the control bus (36).
4).

Therefore, as is conventionally known, a program memory (33) and a plurality of PLDs (34) based on the timing of each signal line of a control bus (36) of a CPU (31).
), it is possible to perform fairly fine control with a single access.

However, in the above configuration, the program memory (
33) Since the address bus for the data memory space or the address bus for the I10100 is shared, in general, if a predetermined instruction is to be executed, the common bus must be used in a time-sharing manner. Therefore, there is a possibility that instruction fetching and external data space or I10100 accesses must be performed alternately many times, and the instruction fetch cycle occupies a considerable amount of time, reducing the overall system processing speed. cannot be improved. For example, when executing the instruction LD A, (6000H) using Zilog's 280 in order to access address 6000)1, it is not possible to randomly access a wide range of addresses consecutively. Therefore, it is necessary to fetch 3 bytes of instructions 32H, 00H, and 60H, so unless refresh cycles are taken into consideration, 3 instruction fetches and one instruction execution would be required.

If you want to solve this kind of problem, you can use the program
It would be possible to separate the address bus for memory and the address bus for external memory space or I/O space, but this increases the number of pins of the CPU (31) and increases the size of the package, resulting in a significant increase in cost. It will be accompanied.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a bit field control device capable of improving processing speed in a system that shares an address bus for program memory and an address bus for external memory space or I10100.

Means for Solving the Problems> In order to achieve the above object, the bit field control device of the present invention is allocated to a predetermined area of the instruction storage means and for controlling the processing means. The control data output means includes control data output means for outputting data, and control means for allowing data output from the control data output means only when a predetermined area of the instruction storage means is accessed.

However, the predetermined area of the instruction storage means is an area that does not require an instruction execution cycle for an external bus and stores a series of instructions that define the processing procedure of the processing means, and the control data output means An address determined based on access data for the means is stored as control data, and the processing means is preferably a programmable logic device.

Further, it is preferable that the control data output means reads and stores an address from another medium at the time of initialization, and that the control means also outputs a control signal to permit writing.

In these cases, the controller further includes data temporary holding means for supplying the address outputted from the central processing means to the processing means as control data, and
It is more preferable that the control means allows data output from either the control data output means or the data temporary holding means.

With the bit field control device having the above configuration, when the central processing means controls the processing means mapped in the external memory space to perform a desired processing operation, generally, Instruction fetching and instruction execution can be performed by supplying an address for fetching an instruction from the central processing unit to the instruction storage means and then supplying an address for accessing the external memory space or I10 space. .

However, when fetching an instruction stored in a predetermined area of the instruction storage means, the address for fetching is not only supplied to the instruction storage means, but also supplied to the control data output means. Since the control means is controlled to permit data output from the data output means, the central processing means performs an operation of supplying control data from the control data output means to the processing means in parallel with the instruction fetch operation. Therefore, the time required from supplying an address for fetch to executing the necessary processing can be shortened.

According to the second invention, when an instruction stored in a predetermined area of the instruction storage means is fetched, a corresponding PLD is selected based on the address output from the control data output means and the predetermined area is fetched. The instructions that can be processed and taken into the central processing means not only do not require execution cycles on the external bus, but are also a series of instructions that define the processing procedure, so the above processing can be performed as necessary. After executing, you can return to normal processing.

Furthermore, according to the third aspect of the invention, the control data output means enters a write-permitted state at the time of initialization and reads addresses from other media, so that the flexibility of the control data output means can be increased. That is, by changing the medium from which the address is read, the contents of the control data output means can be easily changed, and the system can be easily adapted to various types of processing.

Furthermore, according to the fourth aspect of the invention, the general processing of sequentially performing instruction fetch and instruction execution by the central processing means can be performed, and the versatility of the system can be increased.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of the bit field control device of the present invention, which includes a CPU (1), a program memory (2) as an instruction storage means, and a decoder (3) as a control means. ), a read-only memory (hereinafter abbreviated as ROM) (4) as a control data output means, and a plurality of PLDs (5) as processing means.

Then, the address output from the CPU (1) is sent to the program memory (2) via the address bus (6).
, decoder (3) and ROM (4), as well as CPU (1) and program memory (2).
) through a data bus (7). In addition, control data output from the CPU (1) is passed through the control bus (8) to the program memory (2), decoder (3) and PLD.
(5), and the address output from the ROM (4) is supplied to each PLD (5) through the PLD address (9).

As shown in FIG. 2A, the program memory (2) is a mapped specific area (2a) that partially overlaps with the ROM (4).
Only instructions that do not require an instruction execution cycle for external buses such as NOP "RETURN" are stored, and arbitrary instructions ("LDA, B", etc.) are stored in the remaining general area (2b). There is. The above ROM (4) is shown in Figure 2B.
As shown in the figure, the PLD (5) is allocated to the specific area (2a) according to χ·I, and corresponds to each address.
Contains the address to be supplied to.

The decoder (3) sends a decoded signal corresponding to whether the access is to the specific area (2a) or the general area (2b) based on the address output from the CPU (1) to the ROM (4). output as a state control signal ``2'' and an output permission signal 0I'.

The operation of the bit field control device having the above configuration is as follows.

For example, a specific nfI area (2) of program memory (2)
a) Addresses 8000H, 8001H, 8002H8
"NOP" is stored in 003H, "RET" is stored in address 8004H, and 4032H and 4032H are stored in corresponding addresses of ROM (4), respectively.
, 5611H, 4001H, 5422H and 4000
If H is stored, the addresses 8000H, 8001H, 8002H, 80 are sequentially stored starting from CPU (1).
By outputting 03H, program memory (2
), the CPU (11) repeats only instruction fetching.Then, by outputting the above address, the decoder (3) reads the specific area (2a
) is recognized and output permission signal π is R.
Since the data is supplied to OM(4), 4032H, 5611H, 400IH,
5422H is supplied to PLD (5) to perform preset processing in parallel with instruction fetch. After that, CPU (1) to 8004H
By outputting , the "RET" instruction is taken in, so processing is performed to complete the series of processing, and at the same time, ROM (4) sends 4 to PLD (5).
Supply 000H.

After performing a series of processes corresponding to the specific area (2a) as described above, for example, from CPU (1) to 2011
- of program memory (2) by outputting H
It is possible to take in the instruction "LDA, B" from the crotch area (2b) and execute this instruction. That is, CPU (“NOP” in 11)
It is only necessary to fetch one byte, and the ROM (4
) is the corresponding P based on the address stored in
By operating L D (5), any address can be randomly accessed. Then, the instruction "LDA, B" can be executed based on data obtained as a result of randomly accessing arbitrary addresses.

As is clear from the above explanation, the CPU (13) uses the external bus only during instruction fetching, and executes instructions in parallel with instruction fetching. P L D at extremely short time intervals.
Simultaneous control of multiple bits according to (5) can be performed. Furthermore, it is possible to incorporate the bit field control device having the above structure into a graphic vibe line, etc., which can greatly contribute to improving the drawing speed.

<Embodiment 2> FIG. 3 is a block diagram showing another embodiment of the bit field control device of the present invention. The difference from the above embodiment is that data can be written in place of the ROM (4). Static random access memory (SR)
(abbreviated as AM) (11) and the data output from the program memory (2) to the data bus (7) are transferred to the SRAM (I+> The only point is that it can be written to.

Further, in this embodiment, the decoder (3) sends the state control signal 3- and the output permission signal 0 knee to the SRAM (1).
1), and also recognizes that it is the time of initialization and supplies a write permission signal π and an output permission signal π to the S RAM (11) and the buffer (12), respectively.

Therefore, in this embodiment, a necessary address is written from the program memory (2) to the SRAM (11) at the time of initialization, and thereafter the same operation as in the above embodiment can be performed. As a result, there is no need to change the contents of the SRAM (11) when changing the system specifications! 11, it is only necessary to change the contents of the program memory (2).

Furthermore, as is clear from the above explanation, instead of supplying the address from the program memory (2) to S RAM (11), the address is supplied from another external medium to S RAM (1
1), it is also possible in this case to supply instructions to the program memory (2) from an external medium.

<Embodiment 3> FIG. 4 is a block diagram showing still another embodiment of the bit field control device of the present invention. The difference from the embodiment of FIG. 3 is that the output from the CPU (1) is The address is passed through the PLD address bus (9).
The buffer (13) for supplying to (5) is further
The only point is that However, although the decoder (3) also supplies the output permission signal ◇ knee to the buffer (13), output from only either the S RAM (11) or the buffer (13) is permitted. be done.

Therefore, in this example, S RAM(1
In a state in which output from the buffer (13) is permitted, the same effect as described above can be achieved, and conversely, in a state in which output from the buffer (13) is permitted, the same operation as in the conventional example can be performed. As a result, software developed in the conventional example can be used as is, and versatility can be significantly increased.

<Effects of the Invention> As described above, the first invention enables instruction fetching by the central processing means even if the program memo J space bus, data memory space, and I10 weight bus are not separated. By performing the operation of supplying control data from the control data output means to the processing means in parallel with the operation, the instruction fetch address (a unique feature that can shorten the time required from military supply to execution of necessary processing) be effective.

The second invention also has the unique effect of being able to shorten the time required from supplying an address for instruction fetch to executing necessary processing.

The third finding is that by changing the medium from which the address is read, the contents of the control data output means can be easily changed, and the system can be easily adapted to various processes. play.

The fourth aspect of the invention has the unique effect that the central processing means can also carry out normal processing in which instruction fetching and instruction execution are performed sequentially, thereby increasing the versatility of the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the bit field control device of the present invention, FIG. 2 is a schematic diagram showing the relationship between the program memory and ROM, and FIG. 3 is the bit field control device of the present invention. FIG. 4 is a block diagram showing still another embodiment of the bit field control device of the present invention, and FIG. 5 is a block diagram schematically showing a conventional example. (1) CPU, (2) Program memory, (2a) Specific area, (3) Decoder, (4) ROM, (5) PLD . (6)...address bus, (11)...SRAM. (13)...Barafa

Claims (1)

[Claims] 1. A central processing means (1), an instruction storage means (2), and a processing means (5) mapped to an external memory space and having a defined processing procedure; In a system for operating a desired processing means (5) by supplying an address through a common bus (6), a predetermined area (2a) of the instruction storage means (2)
control data output means (4) (1) for outputting data for controlling the processing means (5);
1) and a control means (3) which allows data output from the control data output means (4) and (11) only when a predetermined area (2a) of the instruction storage means (2) is accessed. ) A bit field control device. 2. A predetermined area of the instruction storage means (2) (
2a) is an area in which a series of instructions that do not require an instruction execution cycle for an external bus and that define the processing procedure of the processing means (5) are stored, and the control data output means (4) and (11) are Instruction storage means (
2) stores an address determined based on the access data for the bit as control data, and the processing means is a programmable logic device (5). Field control device. 3. The above patent claim, wherein the control data output means (11) reads and stores an address from another medium at the time of initialization, and the control means (3) also outputs a control signal to permit writing. The bit field control device according to item 1. 4. It further has data temporary holding means (13) which supplies the address outputted from the central processing means (1) as control data to the processing means (5) as it is, and the control means (3) Data output means (4) (11
), the bit field control device according to any one of claims 1 to 3, which allows data output from one of the data temporary holding means (13).