JPH0764787A - Microcomputer - Google Patents

Abstract

PURPOSE:To provide a microcomputer capable of efficiently accessing respective resources in a system in which memory resources capable of rapid/slow access coexist. CONSTITUTION:The device is provided with an adressing mode accessing rapid and slow access memories 1 and 2 and instruction generating a bus cycle necessary for accessing the respective corresponding memory resources by means of the adressing mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microcomputer for accessing a memory having two or more different access times.

[0002]

2. Description of the Related Art FIG. 5 is a conceptual diagram showing a configuration of an address space in a microcomputer disclosed in Japanese Patent Laid-Open No. 2-310746. In the figure, 1 is a high-speed access memory (for example, SRAM) that can be accessed by one clock of the system clock of the microcomputer, and 2 is a low-speed access memory (for example, EPROM) that can be accessed by two clocks.
Is. The conventional microcomputer has a 64KB address space from address 0000 (H) to FFFF (H), and the 4KB area from address 0000 (H) to 0FFF (H) is allocated to high-speed access memory 1. The 60KB area from address 1000 (H) to address FFFF (H) is the low-speed access memory 2
Is assigned to.

The wait control register 3 in the CPU of this microcomputer stores the address information of the upper 4 bits. When the memory is allocated as described above, the content is set to "0000". When accessing such a memory, the CPU compares the contents of the upper 4 bits of the 16-bit effective address for accessing the memory with the contents of the wait control register 3 and executes a bus cycle by a bus cycle signal generation circuit (not shown). Occur. If they match, the memory is accessed in 1 clock, and if they do not match, the memory is accessed in 2 clocks.

In the above-mentioned embodiment, 0F from address 0000 (H)
Although the address FF (H) is used as the high-speed access memory 1, if the contents of the wait control register 3 are changed, an area that can be accessed in one clock can be arbitrarily set within the 64 KB address space.

[0005]

As described above, the conventional microcomputer requires a circuit for determining whether the memory designated by the effective address is the high speed access memory or the low speed access memory, and this circuit makes the determination. As a result, the execution time is delayed, and if a technique such as pipelining is used to reduce the execution time, the hardware becomes complicated.

The present invention has been made in view of such a problem, and by generating a bus cycle for accessing each memory from the information included in an instruction, it is possible to efficiently use a memory having a different access time with simple hardware. A first object of the present invention is to provide a microcomputer that can be physically accessed.

Further, an address is generated from a part of the instruction when accessing the high speed access memory and the information stored in the register, and an address is generated from a part of the instruction when accessing the low speed access memory. To provide a microcomputer capable of accessing a high speed access memory at a higher speed by making the instruction word length of an instruction when accessing an access memory shorter than the instruction word length of an instruction when accessing a low speed access memory. The second purpose.

Furthermore, it is possible to provide a microcomputer capable of accessing a high speed access memory by using a bus cycle from an addressing mode for accessing a memory having a slow access time and using the addressing mode for a low speed access memory. Is the third purpose.

[0009]

According to a first aspect of the present invention, a microcomputer having a plurality of addressing modes for accessing memories having different access times decodes information included in a memory access instruction. And a means for generating a bus cycle required to access each memory corresponding to the addressing mode.

The microcomputer according to the second invention is
In a microcomputer having a plurality of addressing modes for accessing a memory having different access times, a means for generating an address from a part of an instruction having addressing mode information for accessing a memory having a slow access time, and a fast access time And a means for generating an address from a part of an instruction shorter than the instruction having the information of the addressing mode for accessing the memory having the address and the information stored in a predetermined register.

A microcomputer according to the third invention is
In a microcomputer having a plurality of addressing modes for accessing memories having different access times, means for generating a bus cycle by the addressing mode for accessing a memory having a slow access time, and the bus cycle for a memory having a fast access time And a means for accessing using.

[0012]

According to the first aspect of the present invention, memories having different access times are accessed by generating a bus cycle corresponding to the addressing mode determined by decoding the information contained in the instruction.

In the second invention, the address is generated from a part of the addressing mode instruction for accessing the memory having a fast access time and the information stored in the register. In other words, the instruction can be shortened by the amount of information stored in this register, so that the high speed access memory can be accessed at higher speed.

According to the third aspect of the invention, by decoding the information contained in the addressing mode instruction for accessing the memory having the slow access time and generating the bus cycle, the bus having the fast access time can be accessed by the bus. Access using cycle.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a conceptual diagram showing the configuration of an address space in an embodiment of a microcomputer according to the present invention. In the figure, 1 is a high-speed access memory (for example, SRAM) that can be accessed by one clock of the system clock of the microcomputer.
It can be accessed by the clock. 2 is a low-speed access memory (eg EPROM) that can be accessed in 2 clocks
Is.

This microcomputer has an address space of 64 KB from address 0000 (H) to FFFF (H), and a 4 KB area from address 0000 (H) to 0FFF (H) is high speed access memory 1. The 60KB area from address 1000 (H) to address FFFF (H) is allocated to the low-speed access memory 2
Is assigned to.

FIG. 2 is an explanatory diagram of a direct page addressing mode for accessing the high speed access memory 1. When using the direct page addressing mode, the 8-bit direct page register 5 in the CPU of the microcomputer stores the 8-bit information obtained from the instruction as the upper 8-bit information of the 16-bit effective address 6.

The direct page addressing mode instruction is composed of an 8-bit opcode 3 and an 8-bit operand 4. This operand 4 becomes the lower 8 bits information of the effective address 6, and this operation code 3 becomes the information for generating the bus cycle of 1 clock.

FIG. 3 is an explanatory diagram of the absolute addressing mode for accessing the low speed access memory 2. The absolute addressing mode instruction consists of an 8-bit opcode 3 and a 16-bit operand 7. The operand 7 becomes the information of the effective address 6, and the operation code 3 becomes the information for generating the bus cycle of 2 clocks.

FIG. 4 is a block diagram showing a main part of the microcomputer according to the present invention. The instruction latch 8 temporarily holds the operation code 3 of the instruction given from the external ROM (not shown) in which the program is stored, and gives the held operation code 3 to the instruction decoder 9. The instruction decoder 9 decodes the opcode 3 and supplies the decoded opcode 3 to the micro ROM 10. When the decoded and obtained data is one clock access addressing, the micro ROM 10 activates the control line 11, and the bus cycle signal generation circuit 13 receives one clock bus cycle in response to the activation of the control line 11. Occur.

When the data decoded by the above-mentioned instruction decoder 9 is 2-clock access addressing,
The micro ROM 10 activates the control line 12, and the bus cycle signal generation circuit 13 generates two clock bus cycles in response to the activation of the control line 12. What is important in the above operation is that the information for controlling the bus cycle to be accessed is obtained from the opcode 3 rather than from the finally generated effective address 6.

The instruction for the direct page addressing mode is composed of an 8-bit opcode 3 and an 8-bit operand 4, and the instruction word length is 2 bytes. The effective address 6 is generated from the operand 4 and the direct page register 5 described above.

An instruction for the absolute addressing mode is composed of an 8-bit opcode 3 and a 16-bit operand 7, and the instruction word length is 3 bytes. The 16-bit information of this operand 7 becomes the information of the effective address 6. In this way, by making the instruction word length of the instruction for the direct page addressing mode shorter than the instruction word length of the instruction for the absolute addressing mode, it is possible to access the high speed access memory 1 at a higher speed.

On the other hand, the low speed access memory 2 can be accessed by setting the contents of the direct page register 5 from address 10 (H) to address FF (H) using the direct page addressing mode for high speed access memory. Although it is conceivable, in reality, it is impossible to access the low speed access memory 2 by using the direct page addressing mode because two clocks are required to access the low speed access memory 2.

As described above, as a measure for preventing the access to the low speed access memory 2 using the direct page addressing mode for the high speed access memory, 1 clock access and 2 clock access areas are defined by software. If the effective address 6 generated using the direct page addressing mode specifies the low speed access memory 2,
The area defined above may be checked and an assembler error or a compile error may be generated.

As another countermeasure, the direct page register 5 storing the upper 8 bits of the effective address 6 may be set to a value that cannot access the low speed access memory 2. In the case of FIG. 1, setting the upper 4 bits of the direct page register 5 to "0000" makes it impossible to access the low-speed access memory 2.

By the way, as described above, the operation code 3 included in the instruction for the absolute addressing mode is used.
Is decoded to generate a bus cycle which is accessed in 2 clocks. 2 in the address space of FIG.
Since the areas accessible by the clock are the high-speed access memory 1 and the low-speed access memory 2, it is possible to access the high-speed access memory 1 by using the absolute addressing mode for the low-speed access memory.

[0028]

As described above, according to the first invention, the memories having different access times are accessed without using the circuit for comparing the contents of the upper bits of the effective address with the contents of the wait control register as in the conventional device. To generate a bus cycle corresponding to the addressing mode required for this purpose, it is possible to access the memory efficiently even in a system in which memories with different access times coexist, and it is possible to downsize the microcomputer. is there.

Further, in the second invention, the instruction word length of the instruction for the direct page addressing mode is made shorter than the instruction word length of the instruction for the absolute addressing mode, so that the instruction is stored in a small storage area. Therefore, the high-speed access memory can be accessed at higher speed.

Further, according to the third invention, the operation code included in the instruction is used to generate the bus cycle for accessing in two clocks by using the absolute addressing mode for the low speed access memory. It is possible to access the access memory, and it is possible to access memories having different access times using the same addressing mode.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an address space of a microcomputer according to the present invention.

FIG. 2 is an explanatory diagram of instructions for a direct page addressing mode of the microcomputer according to the present invention.

FIG. 3 is an explanatory diagram of instructions for an absolute addressing mode of the microcomputer according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a microcomputer according to the present invention.

FIG. 5 is a conceptual diagram of an address space of a conventional microcomputer.

[Explanation of symbols]

 1 High-speed access memory 2 Low-speed access memory 3 Opcode 4 8-bit operand 5 Direct page register 6 Effective address 7 16-bit operand 8 Instruction latch 9 Instruction decoder 10 Micro ROM 13 Bus cycle signal generation circuit

Claims (3)

[Claims] 1. A microcomputer having a plurality of addressing modes for accessing memories having different access times, means for decoding the information included in a memory access instruction to determine the addressing mode, and the addressing mode. And a means for generating a bus cycle required to access each corresponding memory. 2. A means for generating an address from a part of an instruction having addressing mode information for accessing a memory having a slow access time, in a microcomputer having a plurality of addressing modes for accessing a memory having a different access time. And a part for generating an address from a part of an instruction shorter than the instruction having information of an addressing mode for accessing a memory having a fast access time and information stored in a predetermined register. The microcomputer according to claim 1. 3. A microcomputer having a plurality of addressing modes for accessing memories having different access times, a means for generating a bus cycle by an addressing mode for accessing a memory having a slow access time, and a fast access time. 2. The microcomputer according to claim 1, further comprising means for accessing a memory by using the bus cycle.