JPH02277333A - Demodulation circuit for non zero return type transmission - Google Patents

Abstract

PURPOSE:To improve the reliability of transmission by making the interval of synchronization of a received data narrow. CONSTITUTION:After a received data is inputted to a flip-flop 1, its output is fed to an input of a flip-flop 2 and the flip-flop processing from one output to other input is repeated for 8 times corresponding to a bit number of a data afterward. Through the processing above, the leading and trailing of the received data are detected through the processing. Then an OR output from the flip-flops 1, 2 connects to a preset input via NAMD gates 6, 7 and an ANB gate 8, sampling is applied by a 32MHz clock at the receiver side to generate a synchronization clock in 4MHz with respect to the received data. The clock is inputted to a CMI modulator 4 to read the received data outputted from the flip-flop 2.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention is applicable to non-return to zero (Non-Return) applications such as optical transmission.
turn to Zero; hereinafter abbreviated as NRZ)
The present invention relates to demodulation circuits on the receiving side in transmission systems, and in particular to generation of synchronized clocks.

89 Summary of the Invention The present invention provides a demodulation circuit on the receiving side of NR and Z system transmission such as optical transmission, by inputting and outputting received data a number of times corresponding to the number of bits of the received data, so that both the rising edge and the falling edge of the received data can be input and outputted. a plurality of D-type flip-flops that detect the detection output, and a counter that receives a preset input of the detection output and generates a synchronized clock;
By providing a modulator that reads received data using the synchronization clock, the present invention provides a technology that reduces synchronization intervals without adding significant parts and improves transmission reliability in any case.

C1 Conventional technology When transmitting and receiving signals using the NRZ method, such as optical transmission, there are problems such as a slight difference between the transmitter's clock and the receiver's clock, and waveform distortion called jitter. Therefore, conventionally, the receiving side has devised ways to perform reading in synchronization with the transmitted data to eliminate reception errors.

FIG. 3 is a block diagram of a demodulation circuit showing one example of this, in which synchronization of incoming data is performed on the receiving side.

In the figure, 31 and 32 are flip-flops, 33 is a counter, 34 is a CMI modulator, 35 is a NOT gate, and 36 is a NAND gate. In this circuit, 3 Mbp
The received data (2MRXD) sent at s is passed through the flip-flop 3132, and 32M clock on the receiving side is used to perform zumbling in synchronization with the rising edge of the received data, and the newly generated 4M synchronized clock (4M
MCK), the CMI modulator 34 receives the received data (2M
RIND).

D3 Problems to be Solved by the Invention As mentioned above, optical transmission is a field that utilizes the above circuit, but the reliability of optical receivers is generally It is necessary to control the amount of light to 40 to 60%, and there are also restrictions on lighting time and light-off time. In order to satisfy these conditions, the above-mentioned CM1 (Computer Manager) is used as a controllable demodulation circuit.
In the CMI modulator, as shown in Fig. 4, when the transmission data is -0-, only the first half is 1-.
If the transmitted data is -1-, the previous data is inverted and -1- or -0- continues alternately. For example, sending “7E” (5 data is “0111111
0'', but after CMI modulation, it becomes either ■ or θ shown in Figure 4, and this is the received data (2M
RXD).

Therefore, it has been experimentally confirmed that even if the same data is sent, two patterns, 1 or θ, occur depending on the timing between the power supply room and the bittern, and the reliability of θ, which has a wider signal interval, is lower.

The present invention was created in view of these problems, and
The object of the present invention is to provide a demodulation circuit that reduces the synchronization interval and improves transmission reliability in any case.

E Means for solving the problems The means for solving the problems described in - in the present invention are N
In the demodulation circuit for RZ transmission, there are multiple D-type flip-flops that detect both the rise and fall of received data by outputting it a number of times corresponding to the number of bits, and the detection output is preset input. The demodulation circuit includes a counter that generates a synchronized clock, and a modulator that reads received data using the synchronized clock.

F4 action The present invention creates a synchronous clock by synchronizing both the rising and falling edges of received data.
This narrows the synchronization interval of received data and improves the reliability of transmission.

The demodulation circuit of the present invention includes a plurality of D-type flip-flops, a counter, and a CMI modulator, and the received data is
Multiple flip-flops are input/output a number of times corresponding to the number of bits, and both the rise and fall times are detected, and the counter presets the detection output to read the received data every 2'. A synchronous clock is generated, and the CMI modulator reads received data using this synchronous clock. Since the synchronization clock is created at both the rising edge and the falling edge of the received data, the synchronization interval is narrow and the reliability of transmission is improved.

G. Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention.

In the figure, 1 is a first flip-flop, 2 is a second flip-flop, 3 is a counter, 4 is a CMI modulator, 5 is a NOT gate, 6 and 7 are NAND gates, and 8 is an AND gate.
It is a gate. Incidentally, the above flip-flops 1 and 2 are as follows:
It is a D type flip-flop.

In the figure, received data (2MRXD) is input to the first flip-flop l, and then its output is input to the second flip-flop l.
After that, one output is connected to the input of the other flip-flop 2, and the flip-flop process is repeated eight times in correspondence with the number of data bits. This process requires at least 2
This can be implemented by using D-type flip-flops. Through this process, the rising and falling edges of the received data (2MRXD) are detected.

Next, the OR outputs from the flip-flops 1 and 2 are connected to the preset input (LD) of the counter 3 via the NAND gate 6.7 and the AND gate 8, and zumbling is performed using the 32 MHz clock on the receiving side. 4M I-I Z synchronization clock for received data (4MC
K) is generated.

This synchronous clock (4MCK) is input to the CMI modulator 4, and the received data (2Mr (IND)) finally output from the second flip-flop 2 is read.

FIG. 2 is an explanatory diagram showing the waveform of a clock signal according to the present invention in comparison with that of a conventional example. In the figure, 0 indicates the clock preset, and ↑ indicates the read timing of the received data (2MRIND). As is clear from the figure,
Conventionally, the 4M synchronous clock (4MCK) is generated only when the received data (2MRXD) rises and falls, but in this embodiment, the 4M synchronized clock (4MCK) is generated only when the received data (2MRXD) rises and falls. Synchronous clock (4M
CK) is generated, and many of the read timings O, which were missed in the past, are captured.

In this example, the following effects are obvious.

(1) By synchronizing with the rising or falling edge of received data, the synchronization interval is reduced to 3/4 of the conventional one, and the reliability is improved to 133%. If the counter's LD large input is doubled to four times, the synchronization interval will be 2/4 and the reliability will be 200%.

(2) No significant addition of parts is required.

As described in detail of the H1 invention, according to the present invention, it is possible to provide a demodulation circuit that reduces synchronization intervals and improves transmission reliability without adding significant components.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of a clock signal, Fig. 3 is a block diagram of a conventional example, and Fig. 4 is a CM
It is an explanatory diagram of I modulation. 1.2.31.32...Flip-flop, 3°33
・Counter, 4, 34...CMI modulator, 535...
NOT gate, 6, 7, 36...NAND gate, 8
...AND gate. Written amendment to the procedure for two other persons (a. September 13, 1999)

Claims (1)

[Claims] (1) In a demodulation circuit for non-return-to-zero transmission, a plurality of D-type flip-flops that detect both the rise and fall of received data by inputting and outputting the received data a number of times corresponding to the number of bits; 1. A demodulation circuit comprising: a counter that receives a preset detection output and generates a synchronized clock; and a modulator that reads received data using the synchronized clock.