JPH02277315A - Cmos logic circuit - Google Patents

Abstract

PURPOSE:To attain high speed, low power consumption and small area by decreasing the current drive capability of P logic or N logic MOS transistor (TR) and controlling a gate of a precharge MOS TR with a clock pulse. CONSTITUTION:The speed of a change in an output level of an N logic 2 from H to L is increased and a change of a P logic 1 from an output level from L to H slows down. Then a precharge P-channel MOS TR QP1 whose source connects to an output of a logic gate and whose drain connects to a high level source is provided. Thus, the gate of the TR QP1 is controlled by a clock pulse d so that an output node is precharged to a level VDD before the P logic 1 changes from L to H.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to semi-conductor logic circuits, particularly CMO
This is used for S logic circuits.

(Prior Art) A CMOS logic circuit usually consists of a P-type transistor logic circuit (hereinafter referred to as "P logic") 11 that performs logic synthesis and a complementary N-type transistor logic circuit as shown in FIG. (Hereinafter referred to as "N logic".

) 12 at the same time. Additionally, the threshold voltage of a CMOS logic circuit is generally 1 when VSS is at ground potential.
/2×■DD (power supply potential). For example, in an inverter as shown in FIG.
OS) transistor Qp6 and N-type MO3) transistor QN
The ratio of the gate widths of transistors 6 and 6 is set to 2:1 so that their current driving powers are equal (in the figure, the number written next to the transistor indicates an example of the gate width (unit: μ).
m). same as below. ).

However, this logic circuit has the disadvantage that high-speed operation is hindered due to the large input gate capacitance of the circuit, and the circuit area also becomes large.

Therefore, in addition to such a CMOS logic circuit, a dynamic CMOS circuit as shown in FIG. 12 has been devised. This logic circuit consists of a P-type MOS transistor Qp7
Therefore, the output is precharged to VDD (this refers to charging in advance to VDD (high potential) or Vss (low potential); the same applies hereinafter). The device is characterized in that a logic is determined by the N logic 13 after this precharge is turned off. Therefore, there is an advantage that the input gate capacitance is less than half that of a normal CMOS logic circuit.

However, after the precharge is completed, that is, after transistor QP7 is turned off, this logic circuit changes the output to VDI.
') There are no transistors to maintain it. That is, after turning off the transistor Qr'7, the N logic 13
If there is a time delay before the logic circuit assumes logic, or if the output of the logic circuit is at a high level, VDD will not be maintained due to charge loss, resulting in the logic gate becoming unstable.

(Problem to be solved by the invention) As described above, conventional logic circuits have large input gate capacitances and cannot achieve high-speed operation, low power consumption, and small area. Even if a small dynamic logic circuit was used, the logic gate had the drawback of becoming unstable.

Therefore, an object of the present invention is to provide a CMOS logic circuit that is high speed, has low power consumption, has a small area, and is stable.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the CMOS logic circuit of the present invention has a first potential supply source connected between a first potential supply source and an output node, and to which an input signal is supplied. 1 conductivity type MO3)
a first logic circuit made up of a transistor; and a second logic circuit made up of a second conductivity type MOS transistor connected between the output node and the @2 potential supply source and supplied with the input signal. . Further, the current driving power of the first conductivity type MO8 transistor constituting the first logic circuit is smaller than that of the second conductivity type MO8+- transistor constituting the second logic circuit. Further, a first conductivity type MO3) transistor for precharging is provided whose source is connected to the first potential supply source and whose drain is connected to the output capacitor, and whose gate is controlled by a clock pulse. It is.

Further, a second conductivity type MOS transistor for preventing a DC bus is connected between the second logic circuit and the second potential supply source, and a clock for controlling the gate of the first conductivity type MOS transistor for precharging. A clock pulse having the same phase as the pulse is applied to the second conductivity type MO for preventing the DC path.
It is input to the gate of the S transistor.

Further, the first potential supply source is a high potential source, the second potential supply source is a low potential source, the first conductivity type is P type, the second conductivity type is N type, and the first logic circuit is P type. a CMOS logic circuit in which the logic and the second logic circuit are N logic; the first potential supply source is a low potential source; the second potential supply source is a high potential source; the first conductivity type is N type; Second
A CMOS whose conductivity type is P type, the first logic circuit is N logic, and the second logic circuit is P logic.
It is preferable to connect the logic circuits alternately in series.

(Function) According to such a configuration, the first logic circuit has a smaller M than the second logic circuit in terms of current driving force.
It is composed of OS transistors, and the output potential varies from high level (hereinafter referred to as rHJ) to low level (hereinafter referred to as rL).
It's called J. ) or from L to H at high speed. Further, a MOS transistor for precharging is connected to the output of this logic circuit, and its gate is controlled by a clock pulse. Therefore, the output potential changes rapidly from L to H or from H to L. Furthermore, since the current driving power of the transistors constituting the first logic circuit is small and the input gate capacitance is small, the logic circuit has low power consumption. Further, the circuit area for forming the transistor is small, and the area of the logic circuit can be reduced.

Furthermore, a MOS transistor for DC path prevention is connected between the second logic circuit and the second potential supply source,
Further, a clock pulse having the same phase as the clock pulse controlling the gate of the precharge MOS transistor is manually applied to the gate. Therefore, the MOS transistor for preventing a DC path is always turned off when the MOS transistor for precharging is on, and a DC path from the first potential supply source to the second potential supply source can be prevented.

Further, the first potential supply source is a high potential source, the second potential supply source is a low potential source, the first conductivity type is P type, the second conductivity type is N type, and the first logic circuit is P type. a CMOS logic circuit in which the logic and the second logic circuit are N logic; the first potential supply source is a low potential source; the second potential supply source is a high potential source; the first conductivity type is N type; By alternately connecting in series CMOS logic circuits in which the second conductivity type is P type, the first logic circuit is N logic, and the second logic circuit is P logic, the overall speed of the logic circuit is increased. .

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a CMOS logic circuit of the present invention.

The gate width of one or more transistors constituting P logic l is formed smaller than usual. That is,
The P logic 1 is composed of transistors that are smaller in terms of current driving power than the N logic 2. As a result, the threshold voltage of the logic gate is 1/2X (VD
D+vs) is set lower. Therefore, N logic 2 changes the output potential from H to L at high speed.

However, conversely, it is slow for P logic 1 to change the output potential from L to H. Therefore, a P-type MOS transistor Qp+ for precharging is provided whose source is connected to the output of the logic gate and whose drain is connected to a high potential source.

The gate of this transistor QP is set so that the output node can be precharged to VDD before the P logic 1 changes the output potential from L to H.
It is controlled by a clock pulse φ. That is, by turning on the transistor QPI, the change from L to H can be made faster.

Next, an embodiment in which the present invention is applied to an inverter will be described with reference to FIG. 2 and FIGS. 3(a) to 3(d). Note that FIG. 2 shows an inverter according to the present invention, and FIGS. 3(a) to 3(d) show operational waveform diagrams for explaining its operation.

Inverter I is made up of P-type MOS transistors QP2 and N
MOS transistor QNI. Further, the current driving power of the transistors Q1 and Q2 is formed to be smaller than that of the transistor QNI.

For example, the gate width of transistor QP2 is approximately 2 μms
The gate width of transistor QNI is formed to be approximately 10 μm. Therefore, the threshold voltage of inverter I is 1
/2X (VD o +Vs s ).

For example, if vDD is the power supply potential and 5 V SV s is the ground potential and Ov, the input voltage VIN is approximately 1.7
When , the output voltage VoυT becomes 2.5v. Therefore,
For input voltage VIN, output voltage v, U T is from H to L
, but the change from L to H is slow. (
(See Figures 3(a) and (b)). In addition, the inverter 11
The output is a P-type MOS transistor Q for precharging.
P3 is connected. And this transistor QP
The base of 3 is controlled by clock pulse φ. That is, the output voltage VOUT changes from L to H with respect to the input voltage V1N.
Before changing to VDD, the output node of inverter 11 becomes VDD.
will be precharged. Therefore, the output voltage V. It is possible to speed up the change of UT from L to H (see figure (c)
) and (d)).

According to the inverter having such a configuration, the output voltage voUT can be changed from H to L at high speed by lowering the threshold voltage of the logic gate. Further, by precharging the output node with the transistor QP3, it is possible to speed up the change of the output voltage voUT from L to H.

Furthermore, in contrast to a normal inverter (an inverter whose threshold voltage is set at 1/2X (VDD + Vss) as shown in FIG. 11 above; the same applies hereinafter), the inverter according to the present invention Since the driving force is smaller than that of the transistor QNI, the input gate capacitance is reduced, and further speeding up of the circuit can be achieved.

Furthermore, the small number of customers at the human-powered gate can contribute to reducing the power consumption of the circuit. Furthermore, since the transistor QP2 becomes smaller, the area of the circuit can be reduced.

Note that even if the precharge at the output node of the inverter 11 is cut off after the transistor QP2 is turned on, it will not affect the output voltage VOIIT in any way. This is because even if the precharge is turned off, the transistor Qp2 remains on although its current driving power is small, so that the output potential ■oυT can be maintained at VDD. Therefore, there is no need to worry about charge leakage as in a dynamic CMOS circuit.

By the way, the present invention is not limited to the above embodiments, and various modifications are possible. Therefore, the following figures 4 to 9
These modified examples will be explained with reference to the drawings.

In contrast to the CMOS logic circuit shown in FIG. 1, FIG. 4 shows a CMOS logic circuit constructed of one or more transistors in which N logic 3 is smaller than P logic 4 in terms of current driving power. It shows. That is, since the threshold voltage is set higher than 1/2×(VD n +Vs s ), the output changes quickly from high to high relative to the input, but changes from high to low slow. Therefore, the drain of an N-type MOS transistor QN2 for precharging whose source is connected to VSS is connected to the output of the logic gate. Therefore, by inputting a controlled clock pulse φ to the gate of the transistor QN2, the output can be changed from H to L at high speed.

Note that FIG. 5 shows an embodiment in which the CMOS logic circuit shown in FIG. 4 is applied to an inverter. Here, QP4 is a P-type MO3) transistor with a gate width of about 10 μm, QN3
is an N-type MOS) transistor with a gate width of about 1 μm, QN4
is an N-type MO8I for precharging with a gate width of approximately 10 μm.
- Each transistor is shown.

FIG. 6 shows that in the embodiment shown in FIG. 2, a DC path prevention device is installed between the transistor QNI and VSS to prevent a current path from VDD to VSS via the transistor QP3 during precharging of the output node. N-type MOS)
A transistor QN5 is provided. Here, the same parts as in FIG. 2 are given the same reference numerals. Note that a transistor is provided at the gate of the transistor QN5. A tarlock pulse φ having the same phase as the clock pulse φ that controls the gate of P3 is input. That is, the transistor QN5 is always turned off while the output node is being precharged by the transistor QP3.

FIG. 7 shows that in the embodiment shown in FIG. 5, when the output node is precharged, the transistor QN4 is
VDD and the transistor so that there is no DC path to VSS through it. P type M for DC pass protection I]2 between 24
OS transistor. , 5 are provided. here,
The same parts as in FIG. 5 are given the same reference numerals. Note that a transistor is provided at the gate of the transistor Q P 5. A clock pulse φ having the same phase as the clock pulse 7 that controls the gate of 8.1 is input. That is, the transistor Qp
s is always turned off while the output node is being precharged by the transistor QN4.

Furthermore, FIG. 8 shows that the output potential shown in FIG.
A CMOS logic circuit whose output potential changes from L to L at high speed and a CMOS logic circuit whose output potential changes from L to H at high speed shown in FIG. 4 are alternately connected in series. This makes the entire logic gate faster.

FIG. 9 shows an embodiment in which the CMOS logic circuit shown in FIG. 8 is applied to an inverter, and the inverter shown in FIG. In particular, the inverters shown in FIG. 5 whose output potential VoUT changes from L to H at a high speed are alternately connected in series. Here, the inverters connected in series may be those shown in FIG. 6 or FIG. 7.

Note that the embodiments shown in FIGS. 4 to 9 can also provide the same effects as the embodiments shown in FIGS. 1 and 2.

[Effects of the Invention] As explained above, the CMOS logic circuit of the present invention provides the following effects.

By reducing the current driving power of the P-logic or N-logic MOS transistor and controlling the gate of the precharge MOS transistor with a clock pulse,
Logic gates can be made faster. In addition, the P
Since the current driving power of the logic or N-logic transistor is reduced, the input gate capacitance is reduced to about 1/2 or less.

Furthermore, the circuit area for forming the transistor is reduced to about 1/2 or less. Moreover, dynamic C
There is no need to worry about charge loss like with MOS circuits. That is,
High speed, low power consumption, small area, and stable CMO
S logic circuit can be provided.

Further, by providing a MOS transistor for preventing a DC path and inputting a clock pulse in phase with the gate input of the precharging MOS transistor to its gate, a more stable logic circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a CMOS logic circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a case where the CMOS logic circuit of FIG. 1 is applied to an inverter, and FIG. FIG. 4 is a circuit diagram showing a CMOS logic circuit according to another embodiment of the present invention;
5 is a circuit diagram showing a case where the CMOS logic circuit shown in FIG. 4 is applied to an inverter, FIG. 6 is a circuit diagram showing a modification of the inverter shown in FIG. A circuit diagram showing a modified example of the inverter; FIG. 8 is a circuit diagram showing a logic circuit in which the CMOS logic circuits shown in FIGS. 1 and 4 are alternately connected in series; FIG. 9 is a circuit diagram showing the logic circuit shown in FIG. A circuit diagram showing the case where the circuit is applied to an inverter, Fig. 10 is a circuit diagram showing a conventional CMOS logic circuit, Fig. 11 is a circuit diagram showing a conventional inverter, and Fig. 12 is a circuit showing a conventional Dynamitsu 20M03 circuit. It is a diagram. 1.4...P logic, 2,3...N logic, Q
p+ ~QP7...P-type MOS transistor, QNI
~QN6...N-type MOS transistor. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) A first logic circuit configured of a first conductivity type MOS transistor connected between a first potential supply source and an output node and supplied with an input signal; and a second logic circuit constituted by a second conductivity type MOS transistor connected to the input signal and supplied with the input signal, wherein the current driving power of the first conductivity type MOS transistor is equal to the second conductivity type MOS transistor. A first conductivity type MOS transistor for precharging is provided, which is smaller than that of the MOS transistor, and whose source is connected to the first potential supply source and whose drain is connected to the output node, and whose gate is connected to the clock pulse. A CMOS logic circuit characterized in that it is controlled by. (2) A second conductivity type MOS transistor for DC path prevention is connected between the second logic circuit and a second potential supply source, and the gate of the first conductivity type MOS transistor for precharging is controlled. A clock pulse having the same phase as the clock pulse is applied to the second conductivity type MO for preventing the DC path.
2. The CMOS logic circuit according to claim 1, wherein the CMOS logic circuit is input to the gate of an S transistor. (3) The first potential supply source is a high potential source, the second potential supply source is a low potential source, the first conductivity type is P type, the second conductivity type is N type, and the first logic circuit is 3. The CMOS logic circuit according to claim 1, wherein the P logic and the second logic circuit are N logic, and the first potential supply source is a low potential source, the second potential supply source is a high potential source, and the first 3. The CMOS logic circuit according to claim 1 or 2, wherein the first conductivity type is N type, the second conductivity type is P type, the first logic circuit is N logic, and the second logic circuit is P logic. A CMOS logic circuit characterized in that it is connected in series to a CMOS logic circuit.