JPH0227658Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a video signal switching device that selects one of a plurality of video signals inputted simultaneously from a plurality of video input terminals and sends it to an output terminal.

Conventional video signal switching devices of this type include one that directly switches the video using an alternate selection type mechanical switch, and one that uses an analog switch as shown in FIG.

In FIG. 1, 2a to 2n are normally open push button type select switches, one end of which is connected to the + side power supply terminal 4, and the other end connected to one input terminal of each AND circuit 6a to 6n. There is.

The output terminals of the AND circuits 6a to 6n are respectively
It is connected to the set terminals of the RS flip-flops 8a to 8n, and also to the input terminal of the multi-input OR circuit 10.

The output terminal of the multi-input OR circuit 10 is connected to a reset pulse generation circuit 12, and when the output terminal of the multi-input OR circuit 10 becomes high level, the reset pulse generation circuit 12 generates a pulse that is sufficiently short compared to the synchronization pulse described later. A reset pulse RP is sent to the reset terminals of the RS flip-flops 8a to 8n.

The Q output terminals of the RS flip-flops 8a to 8n are connected to analog switches 18a to 18n interposed between the video signal input terminals 14a to 14n and the video signal output terminal 16.

Reference numeral 20 denotes a synchronization signal generation circuit, which sends a synchronization signal SS to the television camera video devices 22a to 22n connected to the video signal input terminals 14a to 14n to send out synchronized video signals, and also causes these video devices 22a to 22n to output synchronized video signals. A high-level synchronization pulse SP is sent to the other input terminals of the AND circuits 6a to 6n in synchronization with the vertical blanking signal VB sent from the AND circuits 6a to 6n. Note that 24 is a video signal output terminal 16
A receiver connected to the

The video signal switching device configured as described above operates as follows.

Assume that one of the RS flip-flops 8a to 8n, for example, RS flip-flop 8n, is in the set state.

In this state, the Q of RS flip-flop 8n is
Since the output terminal is at a high level, the analog switch 18n becomes conductive, and only the video signal sent from the video device 22n is supplied to the video signal output terminal 16.

Next, suppose that a select switch other than the select switch 2n, for example, the select switch 2a, is pressed in this state.

When select switch 2a is pressed, AND circuit 6a
One of the input terminals becomes high level, and at this time, a high level synchronization pulse is generated from the synchronization signal generation circuit 20.
When SP is supplied to the other input terminal, the output terminal of the AND circuit 6a becomes high level.

When the output terminal of the AND circuit 6a is at a high level, the output terminal of the multi-input OR circuit 10 is also at a high level.
Reset pulse from reset pulse generation circuit 12
RP is sent to each RS flip-flop 8a to 8n and all RS flip-flops 8a to 8
Let n be in the reset state.

If the select switch 2a is pressed and the synchronization pulse SP is supplied from the synchronization signal generation circuit 20 even after the reset is completed, the RS flip-flop 8a is in the set state.

When the RS flip-flop 8a enters the set state, the Q output terminal of the RS flip-flop 8a becomes high level and the analog switch 18a becomes conductive.
A video signal sent from the video device 22a can be received by the receiver 24 from the video output terminal 16.

In the video signal switching device configured in this way, the video devices 22a to 22n receive the vertical blanking signal VB.
While transmitting the signal, the RS flip-flops 8a to 8n are reset and set, and the analog switch 18
Since the signals a to 18n are switched, the switching noise generated at the time of switching does not stand out on the screen of the receiver 24.

However, in such a video signal switching device, when two or more select switches 2a to 2n are pressed at the same time, two or more RS flip-flops 8
There is a drawback that video signals from two or more video devices 22a to 22n are sent to the video signal output terminal 16 when video devices a to 8n are set.
Further, if chattering occurs in the select switches 2a to 2n, they may malfunction.

Furthermore, since a large number of AND circuits 6a to 6n and a multi-input OR circuit 10 are required, there is a drawback that the circuit becomes complicated.

This invention uses a simple circuit configuration to prevent two or more video signals input from multiple video signal input terminals from being selected at the same time, and to create a video signal switching device that does not disrupt the video or malfunction when switching. This is what we are trying to provide.

This invention will be explained below based on an illustrated embodiment. Note that the same parts as in the conventional example are given the same reference numerals, and the description thereof will be omitted.

In FIG. 2, reference numeral 40 denotes a mechanically operated alternate selection type switch group, and the individual switches 42a to 42e making up this switch group 40 have normally open contacts 44a to 44e and normally closed contacts 46a to 46, respectively.
e, it has common contacts 48a to 48e.

The common contact 48a of the switch 42a is connected to the + side power supply terminal 4 via a resistor 49, and the switch 42a
Common contacts 48b to 48e of switches 42a to 42e are normally closed contacts 46a of switches 42a to 42d, respectively.
to 46d. Also switch 42
The normally closed contact 46e of the switch 42a is connected to the normally open contact 44a of the switch 42a.

Normally open contacts 44a to 44e of switches 42a to 42e are light emitting diodes 50a to 50n, respectively.
and is connected to input terminals 54a to 54e of odd parity check circuit 52.

The odd parity check circuit 52 has an input terminal 5.
When an odd number of signals 4a to 54e become high level, a low level parity check signal PC is sent.
When an even number of signals are at high level, a high level parity error signal PE is sent from the output terminal.

The input terminals 54a to 54e of the odd parity check circuit 52 are connected to the D flip-flops 60a to 60e of the latch circuit group 58, respectively.
It is connected to an input terminal, and its output terminal is connected to one input terminal of an invert AND circuit 62.

The other input terminal of the invert AND circuit 62 receives a negative polarity synchronization pulse from the synchronization signal generation circuit 20.
SP is supplied, and the output terminals of the invert AND circuit 62 are connected to D-type flip-flops 58a to 58.
It is connected to the T input terminal of e.

Furthermore, D-type flip-flops 58a to 58e
Q output terminals of are connected to analog switches 18a to 18e, respectively.

The video signal switching device configured as described above operates as follows.

Now, at time _t0 shown in FIG. 3, the common contacts 48a to 48e of all switches 42a to 42e
It is assumed that the normally closed contacts 46a to 46e are connected.

In this state, the resistor 49, the common contacts 48a to 48e of each switch 42a to 42e, and the normally closed contact 4
Only the normally open contact 44a is connected to + via 6a to 46e.
It is connected to the side power supply terminal 4 and becomes high level.

When only the normally open contact 44a becomes high level, the light emitting diode 50a lights up, and the D input terminal of the D-type flip-flop 60a and the input terminal 54a of the odd parity check circuit 52 become high level.

Since the other input terminals 54b to 54e of the odd parity check circuit 52 are all at low level at this time, the output terminal of the odd parity check circuit 52 sends out a low level parity check signal PC, so that the invert AND circuit 62 One input terminal of is also at a low level.

At this time, when the negative polarity synchronization pulse SP is supplied from the synchronization signal generation circuit 20 to the other input terminal of the invert AND circuit 62, the output terminal of the invert AND circuit 62 becomes high level, and the D flip-flops 60a to 60e The T input terminal also becomes high level.

At this time, only the D input terminal of the D-type flip-flop 60a is at a high level, so only the Q output terminal of the D-type flip-flop 60a is at a high level, and the analog switch 18a becomes conductive, and the video equipment 2
The video signal from 2a is sent to the video output terminal 16.

This state continues until any of the switches 42b to 42e is operated.

Next, suppose that the switch 42b is pressed at time _t1 . When the switch 42b is pressed, as shown in FIG.
b and the normally open contact 44b are connected, and the light emitting diode 50b lights up.

During this minute time τ, the odd parity check circuit 52 sends a high level parity error signal PE to one input terminal of the invert AND circuit 62.

Therefore, during the minute time τ, the synchronizing signal generating circuit 2 is connected to the other input terminal of the invert AND circuit 62.
Even if the synchronization pulse SP is sent from 0, D
It is not supplied to the D-type flip-flops 60a to 60e, and the Q output terminal of the D-type flip-flop 60a remains at a high level.

Next, after a minute time τ has passed, the first generated synchronization pulse SP is output from the invert AND circuit 62, and the Q output terminal of the D-type flip-flop 60b is at a high level, and the D-type flip-flops 60a, 6
The Q output terminals 0c to 60e become low level, and the video equipment 22a to 22e output horizontal line cancellation signals.
While transmitting VB, analog switch 18a and analog switch 18b are switched.

Next, suppose that the switch 42d is pressed at time _t2 . When the switch 42d is pressed, the common contact 48
After d and normally open contact 44d are connected, switch 4
2b returns.

At this time, as shown in FIG. 3, the normally open contact 44
d and 44b may be connected to the + side power supply terminal 4 at the same time and become high level, but normally open contacts 44b and 4
While 4d is at a high level at the same time, the odd parity check 52 outputs a high level parity error signal PE to one input terminal of the invert AND circuit 62. During this period, the synchronization pulse SP is output to the synchronization signal generation circuit. 20, the output of the invert AND circuit 62 remains at a low level, and the analog switches 18b and 18d do not become conductive at the same time.

Next, suppose that chattering occurs when the switch 42e is pressed at time _t3 .

When chattering occurs, as shown in FIG. 3, the common contact 48e and the normally open contact 44e are intermittently connected, and the normally open contact 44e becomes intermittently at a high level. During this time, since the normally open contact 44d is always at a high level, the odd parity check circuit 52
sends a high level parity error signal PE to the invert AND circuit 62 only during the period when the common contact 48e and the normally open contact 44e are connected by chattering, and the common contact 48e and the normally open contact are connected by the chattering. 44e is in a disconnected state, a parity check signal PC is generated.

Therefore, even if a negative polarity synchronization pulse SP occurs during this period, the output of the invert AND circuit 62 becomes high level and the D-type flip-flop 60
The T input terminals of the D-type flip-flops 60a to 60e are supplied with new data when the parity check signal PC is generated, that is, the common contact 48e and the normally open contact 44d are supplied to the T input terminals of the flip-flops 60a to 60e. and is in a disconnected state. At this time, only the D input terminal of the D-type flip-flop 60d is at high level, so only the Q output terminal of the D-type flip-flop 60d remains at high level, and the Q output terminal of the D-type flip-flop 60e becomes high level. There isn't.

In addition, if the normally open contact 44e of the switch 42e and the common contact 48e are connected and the switch 42d returns while causing chattering while the synchronous pulse SP is being sent to the invert AND circuit 62, the odd parity check As described above, the circuit 52 sends out the low level parity check signal PC only when only the normally open contact 44e is connected to the + side power supply terminal 4. Therefore, since the invert-AND circuit 62 supplies high-level outputs to each of the D-type flip-flops 60a to 60e only at this time, the Q of the D-type flip-flop 60e increases.
Only the output terminal remains at high level.

Therefore, the Q output terminals of the two D-type flip-flops 60d and 60e become high level at the same time, and the video signals from the two video devices 22d and 22e are not sent out from the output terminal 16.

In either case, the synchronizing pulse SP output from the invert AND circuit 62 is output only when only one of the data input terminals of the D-type flip-flops 60a to 60e is at a high level, and the vertical blanking signal VB Since this occurs during transmission of the signal, the screen on the receiver 24 will not be disturbed when the analog switches 18a to 18e are switched.

As explained above, according to this invention, it is possible to prevent two or more video signals input from a plurality of video signal input terminals from being simultaneously sent out from a video signal output terminal with a simple circuit configuration, and to A video signal switching device that does not cause disturbance or malfunction can be realized. Moreover, when a certain mechanical switch is closed and you open it and try to close another mechanical switch, after both mechanical switches are closed, In the process of opening the closed mechanical switch,
Even if chattering occurs, this video signal switching device prevents one video signal from being intermittently supplied. Furthermore, when switching the video signal, it is sufficient to simply operate a mechanical switch, and the switching operation is simple.

In the above embodiment, the normally closed contacts 46a to 46d
Although the common contacts 48b to 48e are connected to each other, the common contacts 48b to 48e may simply be connected to the common contact 48a. In addition, D type flip-flop 6
In place of 0a to 60e, other latch circuits that perform similar operations may be used.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional video signal switching device, FIG. 2 is a circuit diagram of a video signal switching device based on this invention, and FIG. 3 is a timing diagram showing the operation timing of the video signal switching device based on this invention. be. 4...+ side power supply terminal, 14a to 14e...video signal input terminal, 16...video signal output terminal, 1
8a to 18e...Analog switch, 20...
Synchronous signal generation circuit, 22a to 22e...Video equipment, 42a to 42e...Switch, 52...Parity check circuit, 54a to 54e...Input terminal, 60a to 60e...D flip-flop, 62...Invert AND circuit.

Claims (1)

[Scope of utility model registration request] A synchronization pulse generation circuit, a plurality of video devices each generating a video signal whose vertical retrace period is synchronized with the synchronization pulse, and a video signal output terminal common to these video devices are each interposed. It includes a plurality of switching elements and a plurality of mechanical switches, and these mechanical switches are closed first when one of them is closed and another mechanical switch is closed. An alternate selection type switch in which the mechanical switch is opened and one end of each of the mechanical switches is connected to a power supply, and a plurality of input terminals are connected to the other end of each of the mechanical switches, and an odd number of input terminals are connected to the other end of each of the mechanical switches. a parity check circuit that generates a parity check signal when the mechanical switches are closed; an AND circuit that obtains an AND between the synchronization pulse and the parity check signal; a plurality of latch circuits each having a data input terminal connected to the other end of the expression switch, the logical product being supplied to the latch input terminal, and each supplying an output signal for closing a corresponding one of the switching elements; A video signal switching device comprising: